0hmX/am3352-ddr-track-a-local-dfm-wip-20261007
Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.
- Version
- 0.0.14
- License
- unset
- Stars
- 0
hdmi/validation-next/power-widening/new-ground-references.json
{
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"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
}
]
},
{
"id": "hdmi_power_via_1029",
"x": 59.84,
"y": -27.5,
"required_layers": [
"inner1",
"inner6"
],
"layers": [
{
"layer": "inner1",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner1_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.07853193127331932,
"actual_plane_annulus_contact_area_mm2": 0.07853193127331931,
"covered_annulus_fraction": 0.9999999999999998,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 320,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
},
{
"layer": "inner6",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner6_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.07853193127331932,
"actual_plane_annulus_contact_area_mm2": 0.07853193127331931,
"covered_annulus_fraction": 0.9999999999999998,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 319,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
}
]
},
{
"id": "hdmi_power_via_1031",
"x": 46.85,
"y": -26.75,
"required_layers": [
"inner1",
"inner6"
],
"layers": [
{
"layer": "inner1",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner1_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.07853193127331932,
"actual_plane_annulus_contact_area_mm2": 0.07853193127331931,
"covered_annulus_fraction": 0.9999999999999998,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 320,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
},
{
"layer": "inner6",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner6_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.07853193127331932,
"actual_plane_annulus_contact_area_mm2": 0.07853193127331931,
"covered_annulus_fraction": 0.9999999999999998,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 319,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
}
]
},
{
"id": "hdmi_power_via_1032",
"x": 48.55,
"y": -25.05,
"required_layers": [
"inner1",
"inner6"
],
"layers": [
{
"layer": "inner1",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner1_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.0785319312733193,
"actual_plane_annulus_contact_area_mm2": 0.0785319312733193,
"covered_annulus_fraction": 1.0,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 320,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
},
{
"layer": "inner6",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner6_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.0785319312733193,
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"covered_annulus_fraction": 1.0,
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],
"core_components_with_existing_ground_barrel_anchor": [
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],
"existing_ground_anchor_count": 319,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
}
]
},
{
"id": "hdmi_power_via_1033",
"x": 48.35,
"y": -23.65,
"required_layers": [
"inner1",
"inner6"
],
"layers": [
{
"layer": "inner1",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner1_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.07853193127331932,
"actual_plane_annulus_contact_area_mm2": 0.07853193127331931,
"covered_annulus_fraction": 0.9999999999999998,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 320,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
},
{
"layer": "inner6",
"actual_contact_pour_ids": [
"interface_plan_GND_EXT_inner6_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0"
],
"annulus_area_mm2": 0.07853193127331932,
"actual_plane_annulus_contact_area_mm2": 0.07853193127331931,
"covered_annulus_fraction": 0.9999999999999998,
"center_core_components": [
0
],
"core_components_with_existing_ground_barrel_anchor": [
0
],
"existing_ground_anchor_count": 319,
"representative_existing_ground_anchor_ids": [
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0"
]
}
]
}
],
"method": "Actual same-layer GND pour-to-drilled annulus intersections after final carve, plus via-center membership in0.1mm-eroded full same-layer GND metal component containing an unchanged existing GND barrel from the baseline main physical required-ground group. Names specify ownership but never create geometry contacts. Erosion uses the same via outer-disc convention as the independent contact/core tools; this is not EM or manufacture certification."
}
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