0hmX/am3352-ddr-track-a-local-dfm-wip-20261007
Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.
- Version
- 0.0.14
- License
- unset
- Stars
- 0
hdmi/validation-next/power-widening/connectivity.json
{
"input_sha256": "d5e8f9ace911e5989cb3b5224afe20091092f4b42c3344a8d1749f056230c98b",
"wire_width_convention": "outgoing_segment",
"method": "Independent same-layer copper geometry contacts using Shapely, 1 nm contact tolerance; plated barrels connected across declared layers; seven declared component-internal metal connections applied. Only directly wired source terminals count as routing requirements. Source net metadata specifies required groups and names shorts, never joins copper.",
"limitations": [
"No manufacturing tolerance, impedance, power integrity, firmware or silicon functional validation.",
"Copper disks include plated drill interiors; this can conservatively report an overlap where another copper object crosses a drill void.",
"Curves are the saved route/polygon tessellations."
],
"summary": {
"required_terminals": 1338,
"required_minimum_joins": 1087,
"remaining_minimum_joins": 55,
"source_groups": 251,
"copper_geometry_count": 14695,
"contact_count": 8635,
"shorted_physical_groups": 0,
"unhandled_shapes": []
},
"net_results": [
{
"nets": [
"GND"
],
"terminals": 385,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A5"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A9"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_CKn"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_BA1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_CASn"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_ODT"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D8"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D9"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_DQS1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D15"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D2"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_DQS0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"SYSBOOT0"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_14",
"pcb_port_709"
],
[
"pcb_port_hdmi_pcb_port_247"
]
]
},
{
"nets": [
"SYSBOOT4"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_15",
"pcb_port_717"
],
[
"pcb_port_hdmi_pcb_port_248"
]
]
},
{
"nets": [
"SYSBOOT8"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_16",
"pcb_port_725"
],
[
"pcb_port_hdmi_pcb_port_249"
]
]
},
{
"nets": [
"VDD_MPU"
],
"terminals": 19,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_WEn"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A4"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_CK"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A7"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A11"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_RESETn"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_CSn0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_DQM1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D10"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_DQSn1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_DQM0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D3"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_DQSn0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"SYSBOOT1"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_32",
"pcb_port_711"
],
[
"pcb_port_hdmi_pcb_port_239"
]
]
},
{
"nets": [
"SYSBOOT5"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_33",
"pcb_port_719"
],
[
"pcb_port_hdmi_pcb_port_240"
]
]
},
{
"nets": [
"SYSBOOT9"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_34",
"pcb_port_727"
],
[
"pcb_port_hdmi_pcb_port_241"
]
]
},
{
"nets": [
"SYSBOOT12"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_35",
"pcb_port_733"
],
[
"pcb_port_hdmi_pcb_port_246"
]
]
},
{
"nets": [
"DDR_BA2"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A3"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A12"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_CKE"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_VTP"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D11"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D13"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D4"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D6"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"SYSBOOT2"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_50",
"pcb_port_713"
],
[
"pcb_port_hdmi_pcb_port_231"
]
]
},
{
"nets": [
"SYSBOOT6"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_51",
"pcb_port_721"
],
[
"pcb_port_hdmi_pcb_port_232"
]
]
},
{
"nets": [
"SYSBOOT10"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_52",
"pcb_port_729"
],
[
"pcb_port_hdmi_pcb_port_233"
]
]
},
{
"nets": [
"SYSBOOT13"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_53",
"pcb_port_735"
],
[
"pcb_port_hdmi_pcb_port_238"
]
]
},
{
"nets": [
"RTC_KALDO_EN_N"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_BA0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A8"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A2"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A10"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_RASn"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_VREF"
],
"terminals": 10,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D12"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D14"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D5"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_D7"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"SYSBOOT3"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_68",
"pcb_port_715"
],
[
"pcb_port_hdmi_pcb_port_223"
]
]
},
{
"nets": [
"SYSBOOT7"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_69",
"pcb_port_723"
],
[
"pcb_port_hdmi_pcb_port_224"
]
]
},
{
"nets": [
"SYSBOOT11"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_70",
"pcb_port_731"
],
[
"pcb_port_hdmi_pcb_port_225"
]
]
},
{
"nets": [
"SYSBOOT14"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_71",
"pcb_port_737"
],
[
"pcb_port_hdmi_pcb_port_230"
]
]
},
{
"nets": [
"RTC_RESET_N"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"EXT_WAKEUP"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_A6"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_1V5"
],
"terminals": 68,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"V3V3"
],
"terminals": 101,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_HSYNC"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_86"
],
[
"pcb_port_hdmi_pcb_port_256"
]
]
},
{
"nets": [
"SYSBOOT15"
],
"terminals": 3,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_87",
"pcb_port_739"
],
[
"pcb_port_hdmi_pcb_port_222"
]
]
},
{
"nets": [
"HDMI_VSYNC"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_88"
],
[
"pcb_port_hdmi_pcb_port_257"
]
]
},
{
"nets": [
"LCD_PCLK"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_89"
],
[
"pcb_port_hdmi_pcb_port_254"
]
]
},
{
"nets": [
"PMIC_POWER_EN"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"CAP_VDD_RTC"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"V1V8"
],
"terminals": 50,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"VDD_CORE"
],
"terminals": 33,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"LCD_DE"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_104"
],
[
"pcb_port_hdmi_pcb_port_255"
]
]
},
{
"nets": [
"PMIC_INT_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"CAP_VDD_SRAM_CORE"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"WARMRST_N"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TRST_N"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"CAP_VBB_MPU"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_RGB_D22"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_177"
],
[
"pcb_port_hdmi_pcb_port_216"
]
]
},
{
"nets": [
"HDMI_RGB_D23"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_178"
],
[
"pcb_port_hdmi_pcb_port_217"
]
]
},
{
"nets": [
"SOC_CLK24"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TDO"
],
"terminals": 1,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TDI"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TMS"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"CAP_VDD_SRAM_MPU"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_RGB_D21"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_195"
],
[
"pcb_port_hdmi_pcb_port_215"
]
]
},
{
"nets": [
"TCK"
],
"terminals": 1,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_RGB_D18"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_212"
],
[
"pcb_port_hdmi_pcb_port_208"
]
]
},
{
"nets": [
"HDMI_RGB_D19"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_213"
],
[
"pcb_port_hdmi_pcb_port_209"
]
]
},
{
"nets": [
"HDMI_RGB_D20"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_214"
],
[
"pcb_port_hdmi_pcb_port_214"
]
]
},
{
"nets": [
"HDMI_RGB_D16"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_232"
],
[
"pcb_port_hdmi_pcb_port_206"
]
]
},
{
"nets": [
"HDMI_RGB_D17"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"EMU1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"EMU0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PWRONRST_N"
],
"terminals": 6,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"UART0_RX"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_DAT1"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_RX_ER"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_RXD1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"I2C0_SCL"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"UART0_TX"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_DAT0"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TX_EN"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TXD1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_RXD0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_CD_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"I2C0_SDA"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_DAT3"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_CLK"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_CRS_DV"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TXD0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_MDIO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_INT_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_RESET_GPIO_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_DAT2"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"MMC0_CMD"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_REFCLK"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_MDC"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"DDR_ZQ"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"SYS_5V"
],
"terminals": 21,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_PGOOD"
],
"terminals": 6,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_SW4A"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_SW4B"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_DC34_SEL"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_INT_LDO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_SW3"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_SW2"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_PB_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PMIC_SW1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"OSC24_OE"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"SD_CLK"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"USBC_VBUS_RAW"
],
"terminals": 16,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"USBC_CC1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"USBC_CC2"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TYPEC_VBUS_DET"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TYPEC_OUT1"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TYPEC_OUT2"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"TYPEC_3A_OK"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"INPUT_DVDT"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"INPUT_FAULT_N"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"INPUT_ILM"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_3V3_PRE"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_TX_EN"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_REFCLK"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_INT_N"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_LED0"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_RESET_N"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_3V3"
],
"terminals": 29,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_RX_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_RX_P"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_TX_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_TX_P"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_XI"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_RBIAS"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_MDIO_ISO"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_MDC"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_RXD1"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_RXD0"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_CRS_DV"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_RX_ER"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_TXD0"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_TXD1"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TX_EN_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TXD0_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TXD1_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_MDC_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_RXD0_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_RXD1_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_CRS_DV_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_RX_ER_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_REFCLK_ISO"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PHY_OSC25"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_TX_CT"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_RX_CT"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"CHASSIS"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_LED_GREEN_A"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_LED_YELLOW_A"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_RAMP_CT"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TX_EN_DAMPED"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TXD0_DAMPED"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"RMII1_TXD1_DAMPED"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_ISO_OE_N"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"ETH_MDC_DAMPED"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PG_LED_SENSE"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PG_LED_K"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"PG_LED_A"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_OVDD_3V3"
],
"terminals": 5,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_IVDD_1V2"
],
"terminals": 8,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_3V3"
],
"terminals": 7,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_HPD"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_DDC_SDA"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_DDC_SCL"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_CEC"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_PVCC_1V2"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_REXT"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TXC_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TXC_P"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_AVCC_1V2"
],
"terminals": 5,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TX0_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TX0_P"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TX1_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TX1_P"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_DVDD_1V2"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TX2_N"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_TX2_P"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_ENTEST"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_PCADR"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_RESET_N"
],
"terminals": 4,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_D23"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_35"
],
[
"pcb_port_hdmi_pcb_port_251"
]
]
},
{
"nets": [
"HDMI_D22"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_36"
],
[
"pcb_port_hdmi_pcb_port_228"
]
]
},
{
"nets": [
"HDMI_D21"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_37"
],
[
"pcb_port_hdmi_pcb_port_236"
]
]
},
{
"nets": [
"HDMI_D20"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_38"
],
[
"pcb_port_hdmi_pcb_port_244"
]
]
},
{
"nets": [
"HDMI_D19"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_39"
],
[
"pcb_port_hdmi_pcb_port_252"
]
]
},
{
"nets": [
"HDMI_D18"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_40"
],
[
"pcb_port_hdmi_pcb_port_213"
]
]
},
{
"nets": [
"HDMI_D17"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_41"
],
[
"pcb_port_hdmi_pcb_port_211"
]
]
},
{
"nets": [
"HDMI_D16"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_42"
],
[
"pcb_port_hdmi_pcb_port_220"
]
]
},
{
"nets": [
"HDMI_D15"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_43"
],
[
"pcb_port_hdmi_pcb_port_234"
]
]
},
{
"nets": [
"HDMI_D14"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_44"
],
[
"pcb_port_hdmi_pcb_port_242"
]
]
},
{
"nets": [
"HDMI_D13"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_45"
],
[
"pcb_port_hdmi_pcb_port_250"
]
]
},
{
"nets": [
"HDMI_D12"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_46"
],
[
"pcb_port_hdmi_pcb_port_227"
]
]
},
{
"nets": [
"HDMI_D11"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_47"
],
[
"pcb_port_hdmi_pcb_port_235"
]
]
},
{
"nets": [
"HDMI_D10"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_48"
],
[
"pcb_port_hdmi_pcb_port_243"
]
]
},
{
"nets": [
"HDMI_D9"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_49"
],
[
"pcb_port_hdmi_pcb_port_210"
]
]
},
{
"nets": [
"HDMI_PCLK_RX"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_50"
],
[
"pcb_port_hdmi_pcb_port_261"
]
]
},
{
"nets": [
"HDMI_D8"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_51"
],
[
"pcb_port_hdmi_pcb_port_219"
]
]
},
{
"nets": [
"HDMI_D7"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_52"
],
[
"pcb_port_hdmi_pcb_port_229"
]
]
},
{
"nets": [
"HDMI_D6"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_53"
],
[
"pcb_port_hdmi_pcb_port_237"
]
]
},
{
"nets": [
"HDMI_D5"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_54"
],
[
"pcb_port_hdmi_pcb_port_245"
]
]
},
{
"nets": [
"HDMI_D4"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_56"
],
[
"pcb_port_hdmi_pcb_port_253"
]
]
},
{
"nets": [
"HDMI_D3"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_57"
],
[
"pcb_port_hdmi_pcb_port_226"
]
]
},
{
"nets": [
"HDMI_D2"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_58"
],
[
"pcb_port_hdmi_pcb_port_212"
]
]
},
{
"nets": [
"HDMI_D1"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_59"
],
[
"pcb_port_hdmi_pcb_port_221"
]
]
},
{
"nets": [
"HDMI_D0"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_60"
],
[
"pcb_port_hdmi_pcb_port_218"
]
]
},
{
"nets": [
"HDMI_DE_RX"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_61"
],
[
"pcb_port_hdmi_pcb_port_260"
]
]
},
{
"nets": [
"HDMI_HSYNC_RX"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_62"
],
[
"pcb_port_hdmi_pcb_port_259"
]
]
},
{
"nets": [
"HDMI_VSYNC_RX"
],
"terminals": 2,
"physical_groups": 2,
"remaining_joins": 1,
"groups": [
[
"pcb_port_hdmi_pcb_port_63"
],
[
"pcb_port_hdmi_pcb_port_258"
]
]
},
{
"nets": [
"HDMI_1V2"
],
"terminals": 8,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_CEC_PULLUP"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_5V"
],
"terminals": 5,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_1V2_EN"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_5V_SUPPLY"
],
"terminals": 6,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_UTILITY"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_5V_FB"
],
"terminals": 3,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
},
{
"nets": [
"HDMI_5V_SW"
],
"terminals": 2,
"physical_groups": 1,
"remaining_joins": 0,
"groups": []
}
],
"shorts": [],
"ddr_terminal_inventory": [
{
"net": "DDR_A5",
"terminals": [
{
"component": "U1",
"ball": "B1",
"hints": [
"B1",
"DDR_A5_B1",
"pin2",
"2"
],
"nets": [
"DDR_A5"
]
},
{
"component": "U3",
"ball": "P2",
"hints": [
"P2",
"signal_A5",
"pin30",
"30"
],
"nets": [
"DDR_A5"
]
}
]
},
{
"net": "DDR_A9",
"terminals": [
{
"component": "U1",
"ball": "C1",
"hints": [
"C1",
"DDR_A9_C1",
"pin3",
"3"
],
"nets": [
"DDR_A9"
]
},
{
"component": "U3",
"ball": "R3",
"hints": [
"R3",
"signal_A9",
"pin47",
"47"
],
"nets": [
"DDR_A9"
]
}
]
},
{
"net": "DDR_CKn",
"terminals": [
{
"component": "U1",
"ball": "D1",
"hints": [
"D1",
"DDR_CKn_D1",
"pin4",
"4"
],
"nets": [
"DDR_CKn"
]
},
{
"component": "U3",
"ball": "K7",
"hints": [
"K7",
"signal_N_CK",
"pin58",
"58"
],
"nets": [
"DDR_CKn"
]
}
]
},
{
"net": "DDR_BA1",
"terminals": [
{
"component": "U1",
"ball": "E1",
"hints": [
"E1",
"DDR_BA1_E1",
"pin5",
"5"
],
"nets": [
"DDR_BA1"
]
},
{
"component": "U3",
"ball": "N8",
"hints": [
"N8",
"signal_BA1",
"pin77",
"77"
],
"nets": [
"DDR_BA1"
]
}
]
},
{
"net": "DDR_CASn",
"terminals": [
{
"component": "U1",
"ball": "F1",
"hints": [
"F1",
"DDR_CASn_F1",
"pin6",
"6"
],
"nets": [
"DDR_CASn"
]
},
{
"component": "U3",
"ball": "K3",
"hints": [
"K3",
"signal_N_CAS",
"pin42",
"42"
],
"nets": [
"DDR_CASn"
]
}
]
},
{
"net": "DDR_ODT",
"terminals": [
{
"component": "U1",
"ball": "G1",
"hints": [
"G1",
"DDR_ODT_G1",
"pin7",
"7"
],
"nets": [
"DDR_ODT"
]
},
{
"component": "U3",
"ball": "K1",
"hints": [
"K1",
"signal_ODT",
"pin10",
"10"
],
"nets": [
"DDR_ODT"
]
}
]
},
{
"net": "DDR_A1",
"terminals": [
{
"component": "U1",
"ball": "H1",
"hints": [
"H1",
"DDR_A1_H1",
"pin8",
"8"
],
"nets": [
"DDR_A1"
]
},
{
"component": "U3",
"ball": "P7",
"hints": [
"P7",
"signal_A1",
"pin62",
"62"
],
"nets": [
"DDR_A1"
]
}
]
},
{
"net": "DDR_D8",
"terminals": [
{
"component": "U1",
"ball": "J1",
"hints": [
"J1",
"DDR_D8_J1",
"pin9",
"9"
],
"nets": [
"DDR_D8"
]
},
{
"component": "U3",
"ball": "C3",
"hints": [
"C3",
"signal_DQU1",
"pin35",
"35"
],
"nets": [
"DDR_D8"
]
}
]
},
{
"net": "DDR_D9",
"terminals": [
{
"component": "U1",
"ball": "K1",
"hints": [
"K1",
"DDR_D9_K1",
"pin10",
"10"
],
"nets": [
"DDR_D9"
]
},
{
"component": "U3",
"ball": "D7",
"hints": [
"D7",
"signal_DQU0",
"pin52",
"52"
],
"nets": [
"DDR_D9"
]
}
]
},
{
"net": "DDR_DQS1",
"terminals": [
{
"component": "U1",
"ball": "L1",
"hints": [
"L1",
"DDR_DQS1_L1",
"pin11",
"11"
],
"nets": [
"DDR_DQS1"
]
},
{
"component": "U3",
"ball": "C7",
"hints": [
"C7",
"signal_DQSU",
"pin51",
"51"
],
"nets": [
"DDR_DQS1"
]
}
]
},
{
"net": "DDR_D15",
"terminals": [
{
"component": "U1",
"ball": "M1",
"hints": [
"M1",
"DDR_D15_M1",
"pin12",
"12"
],
"nets": [
"DDR_D15"
]
},
{
"component": "U3",
"ball": "B8",
"hints": [
"B8",
"signal_DQU6",
"pin66",
"66"
],
"nets": [
"DDR_D15"
]
}
]
},
{
"net": "DDR_D2",
"terminals": [
{
"component": "U1",
"ball": "N1",
"hints": [
"N1",
"DDR_D2_N1",
"pin13",
"13"
],
"nets": [
"DDR_D2"
]
},
{
"component": "U3",
"ball": "E3",
"hints": [
"E3",
"signal_DQL0",
"pin37",
"37"
],
"nets": [
"DDR_D2"
]
}
]
},
{
"net": "DDR_DQS0",
"terminals": [
{
"component": "U1",
"ball": "P1",
"hints": [
"P1",
"DDR_DQS0_P1",
"pin14",
"14"
],
"nets": [
"DDR_DQS0"
]
},
{
"component": "U3",
"ball": "F3",
"hints": [
"F3",
"signal_DQSL",
"pin38",
"38"
],
"nets": [
"DDR_DQS0"
]
}
]
},
{
"net": "DDR_WEn",
"terminals": [
{
"component": "U1",
"ball": "B2",
"hints": [
"B2",
"DDR_WEn_B2",
"pin20",
"20"
],
"nets": [
"DDR_WEn"
]
},
{
"component": "U3",
"ball": "L3",
"hints": [
"L3",
"signal_N_WE",
"pin43",
"43"
],
"nets": [
"DDR_WEn"
]
}
]
},
{
"net": "DDR_A4",
"terminals": [
{
"component": "U1",
"ball": "C2",
"hints": [
"C2",
"DDR_A4_C2",
"pin21",
"21"
],
"nets": [
"DDR_A4"
]
},
{
"component": "U3",
"ball": "P8",
"hints": [
"P8",
"signal_A4",
"pin78",
"78"
],
"nets": [
"DDR_A4"
]
}
]
},
{
"net": "DDR_CK",
"terminals": [
{
"component": "U1",
"ball": "D2",
"hints": [
"D2",
"DDR_CK_D2",
"pin22",
"22"
],
"nets": [
"DDR_CK"
]
},
{
"component": "U3",
"ball": "J7",
"hints": [
"J7",
"signal_CK",
"pin57",
"57"
],
"nets": [
"DDR_CK"
]
}
]
},
{
"net": "DDR_A7",
"terminals": [
{
"component": "U1",
"ball": "E2",
"hints": [
"E2",
"DDR_A7_E2",
"pin23",
"23"
],
"nets": [
"DDR_A7"
]
},
{
"component": "U3",
"ball": "R2",
"hints": [
"R2",
"signal_A7",
"pin31",
"31"
],
"nets": [
"DDR_A7"
]
}
]
},
{
"net": "DDR_A11",
"terminals": [
{
"component": "U1",
"ball": "F2",
"hints": [
"F2",
"DDR_A11_F2",
"pin24",
"24"
],
"nets": [
"DDR_A11"
]
},
{
"component": "U3",
"ball": "R7",
"hints": [
"R7",
"signal_A11",
"pin63",
"63"
],
"nets": [
"DDR_A11"
]
}
]
},
{
"net": "DDR_RESETn",
"terminals": [
{
"component": "U1",
"ball": "G2",
"hints": [
"G2",
"DDR_RESETn_G2",
"pin25",
"25"
],
"nets": [
"DDR_RESETn"
]
},
{
"component": "U3",
"ball": "T2",
"hints": [
"T2",
"signal_N_RESET",
"pin32",
"32"
],
"nets": [
"DDR_RESETn"
]
},
{
"component": "R_DDR_RESET",
"ball": "pin1",
"hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"nets": [
"DDR_RESETn"
]
}
]
},
{
"net": "DDR_CSn0",
"terminals": [
{
"component": "U1",
"ball": "H2",
"hints": [
"H2",
"DDR_CSn0_H2",
"pin26",
"26"
],
"nets": [
"DDR_CSn0"
]
},
{
"component": "U3",
"ball": "L2",
"hints": [
"L2",
"signal_N_CS",
"pin27",
"27"
],
"nets": [
"DDR_CSn0"
]
}
]
},
{
"net": "DDR_DQM1",
"terminals": [
{
"component": "U1",
"ball": "J2",
"hints": [
"J2",
"DDR_DQM1_J2",
"pin27",
"27"
],
"nets": [
"DDR_DQM1"
]
},
{
"component": "U3",
"ball": "D3",
"hints": [
"D3",
"signal_DMU",
"pin36",
"36"
],
"nets": [
"DDR_DQM1"
]
}
]
},
{
"net": "DDR_D10",
"terminals": [
{
"component": "U1",
"ball": "K2",
"hints": [
"K2",
"DDR_D10_K2",
"pin28",
"28"
],
"nets": [
"DDR_D10"
]
},
{
"component": "U3",
"ball": "A3",
"hints": [
"A3",
"signal_DQU7",
"pin33",
"33"
],
"nets": [
"DDR_D10"
]
}
]
},
{
"net": "DDR_DQSn1",
"terminals": [
{
"component": "U1",
"ball": "L2",
"hints": [
"L2",
"DDR_DQSn1_L2",
"pin29",
"29"
],
"nets": [
"DDR_DQSn1"
]
},
{
"component": "U3",
"ball": "B7",
"hints": [
"B7",
"signal_N_DQSU",
"pin50",
"50"
],
"nets": [
"DDR_DQSn1"
]
}
]
},
{
"net": "DDR_DQM0",
"terminals": [
{
"component": "U1",
"ball": "M2",
"hints": [
"M2",
"DDR_DQM0_M2",
"pin30",
"30"
],
"nets": [
"DDR_DQM0"
]
},
{
"component": "U3",
"ball": "E7",
"hints": [
"E7",
"signal_DML",
"pin53",
"53"
],
"nets": [
"DDR_DQM0"
]
}
]
},
{
"net": "DDR_D3",
"terminals": [
{
"component": "U1",
"ball": "N2",
"hints": [
"N2",
"DDR_D3_N2",
"pin31",
"31"
],
"nets": [
"DDR_D3"
]
},
{
"component": "U3",
"ball": "H3",
"hints": [
"H3",
"signal_DQL4",
"pin40",
"40"
],
"nets": [
"DDR_D3"
]
}
]
},
{
"net": "DDR_DQSn0",
"terminals": [
{
"component": "U1",
"ball": "P2",
"hints": [
"P2",
"DDR_DQSn0_P2",
"pin32",
"32"
],
"nets": [
"DDR_DQSn0"
]
},
{
"component": "U3",
"ball": "G3",
"hints": [
"G3",
"signal_N_DQSl",
"pin39",
"39"
],
"nets": [
"DDR_DQSn0"
]
}
]
},
{
"net": "DDR_BA2",
"terminals": [
{
"component": "U1",
"ball": "B3",
"hints": [
"B3",
"DDR_BA2_B3",
"pin38",
"38"
],
"nets": [
"DDR_BA2"
]
},
{
"component": "U3",
"ball": "M3",
"hints": [
"M3",
"signal_BA2",
"pin44",
"44"
],
"nets": [
"DDR_BA2"
]
}
]
},
{
"net": "DDR_A3",
"terminals": [
{
"component": "U1",
"ball": "C3",
"hints": [
"C3",
"DDR_A3_C3",
"pin39",
"39"
],
"nets": [
"DDR_A3"
]
},
{
"component": "U3",
"ball": "N2",
"hints": [
"N2",
"signal_A3",
"pin29",
"29"
],
"nets": [
"DDR_A3"
]
}
]
},
{
"net": "DDR_A12",
"terminals": [
{
"component": "U1",
"ball": "E3",
"hints": [
"E3",
"DDR_A12_E3",
"pin41",
"41"
],
"nets": [
"DDR_A12"
]
},
{
"component": "U3",
"ball": "N7",
"hints": [
"N7",
"signal_A12",
"pin61",
"61"
],
"nets": [
"DDR_A12"
]
}
]
},
{
"net": "DDR_A0",
"terminals": [
{
"component": "U1",
"ball": "F3",
"hints": [
"F3",
"DDR_A0_F3",
"pin42",
"42"
],
"nets": [
"DDR_A0"
]
},
{
"component": "U3",
"ball": "N3",
"hints": [
"N3",
"signal_A0",
"pin45",
"45"
],
"nets": [
"DDR_A0"
]
}
]
},
{
"net": "DDR_CKE",
"terminals": [
{
"component": "U1",
"ball": "G3",
"hints": [
"G3",
"DDR_CKE_G3",
"pin43",
"43"
],
"nets": [
"DDR_CKE"
]
},
{
"component": "U3",
"ball": "K9",
"hints": [
"K9",
"signal_CKE",
"pin90",
"90"
],
"nets": [
"DDR_CKE"
]
}
]
},
{
"net": "DDR_VTP",
"terminals": [
{
"component": "U1",
"ball": "J3",
"hints": [
"J3",
"DDR_VTP_J3",
"pin45",
"45"
],
"nets": [
"DDR_VTP"
]
},
{
"component": "R_DDR_VTP",
"ball": "pin1",
"hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"nets": [
"DDR_VTP"
]
}
]
},
{
"net": "DDR_D11",
"terminals": [
{
"component": "U1",
"ball": "K3",
"hints": [
"K3",
"DDR_D11_K3",
"pin46",
"46"
],
"nets": [
"DDR_D11"
]
},
{
"component": "U3",
"ball": "C2",
"hints": [
"C2",
"signal_DQU3",
"pin19",
"19"
],
"nets": [
"DDR_D11"
]
}
]
},
{
"net": "DDR_D13",
"terminals": [
{
"component": "U1",
"ball": "L3",
"hints": [
"L3",
"DDR_D13_L3",
"pin47",
"47"
],
"nets": [
"DDR_D13"
]
},
{
"component": "U3",
"ball": "A7",
"hints": [
"A7",
"signal_DQU4",
"pin49",
"49"
],
"nets": [
"DDR_D13"
]
}
]
},
{
"net": "DDR_D0",
"terminals": [
{
"component": "U1",
"ball": "M3",
"hints": [
"M3",
"DDR_D0_M3",
"pin48",
"48"
],
"nets": [
"DDR_D0"
]
},
{
"component": "U3",
"ball": "F2",
"hints": [
"F2",
"signal_DQL2",
"pin22",
"22"
],
"nets": [
"DDR_D0"
]
}
]
},
{
"net": "DDR_D4",
"terminals": [
{
"component": "U1",
"ball": "N3",
"hints": [
"N3",
"DDR_D4_N3",
"pin49",
"49"
],
"nets": [
"DDR_D4"
]
},
{
"component": "U3",
"ball": "F8",
"hints": [
"F8",
"signal_DQL3",
"pin70",
"70"
],
"nets": [
"DDR_D4"
]
}
]
},
{
"net": "DDR_D6",
"terminals": [
{
"component": "U1",
"ball": "P3",
"hints": [
"P3",
"DDR_D6_P3",
"pin50",
"50"
],
"nets": [
"DDR_D6"
]
},
{
"component": "U3",
"ball": "F7",
"hints": [
"F7",
"signal_DQL1",
"pin54",
"54"
],
"nets": [
"DDR_D6"
]
}
]
},
{
"net": "DDR_BA0",
"terminals": [
{
"component": "U1",
"ball": "C4",
"hints": [
"C4",
"DDR_BA0_C4",
"pin57",
"57"
],
"nets": [
"DDR_BA0"
]
},
{
"component": "U3",
"ball": "M2",
"hints": [
"M2",
"signal_BA0",
"pin28",
"28"
],
"nets": [
"DDR_BA0"
]
}
]
},
{
"net": "DDR_A8",
"terminals": [
{
"component": "U1",
"ball": "D4",
"hints": [
"D4",
"DDR_A8_D4",
"pin58",
"58"
],
"nets": [
"DDR_A8"
]
},
{
"component": "U3",
"ball": "T8",
"hints": [
"T8",
"signal_A8",
"pin80",
"80"
],
"nets": [
"DDR_A8"
]
}
]
},
{
"net": "DDR_A2",
"terminals": [
{
"component": "U1",
"ball": "E4",
"hints": [
"E4",
"DDR_A2_E4",
"pin59",
"59"
],
"nets": [
"DDR_A2"
]
},
{
"component": "U3",
"ball": "P3",
"hints": [
"P3",
"signal_A2",
"pin46",
"46"
],
"nets": [
"DDR_A2"
]
}
]
},
{
"net": "DDR_A10",
"terminals": [
{
"component": "U1",
"ball": "F4",
"hints": [
"F4",
"DDR_A10_F4",
"pin60",
"60"
],
"nets": [
"DDR_A10"
]
},
{
"component": "U3",
"ball": "L7",
"hints": [
"L7",
"signal_A10",
"pin59",
"59"
],
"nets": [
"DDR_A10"
]
}
]
},
{
"net": "DDR_RASn",
"terminals": [
{
"component": "U1",
"ball": "G4",
"hints": [
"G4",
"DDR_RASn_G4",
"pin61",
"61"
],
"nets": [
"DDR_RASn"
]
},
{
"component": "U3",
"ball": "J3",
"hints": [
"J3",
"signal_N_RAS",
"pin41",
"41"
],
"nets": [
"DDR_RASn"
]
}
]
},
{
"net": "DDR_VREF",
"terminals": [
{
"component": "U1",
"ball": "J4",
"hints": [
"J4",
"DDR_VREF_J4",
"pin63",
"63"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "U3",
"ball": "H1",
"hints": [
"H1",
"signal_VREFDQ",
"pin8",
"8"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "U3",
"ball": "M8",
"hints": [
"M8",
"signal_VREFCA",
"pin76",
"76"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "R_VREF_TOP",
"ball": "pin2",
"hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "R_VREF_BOT",
"ball": "pin1",
"hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "C_VREF_TOP",
"ball": "pin2",
"hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "C_VREF_0",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "C_VREF_1",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "C_VREF_2",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_VREF"
]
},
{
"component": "C_VREF_3",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_VREF"
]
}
]
},
{
"net": "DDR_D12",
"terminals": [
{
"component": "U1",
"ball": "K4",
"hints": [
"K4",
"DDR_D12_K4",
"pin64",
"64"
],
"nets": [
"DDR_D12"
]
},
{
"component": "U3",
"ball": "A2",
"hints": [
"A2",
"signal_DQU5",
"pin17",
"17"
],
"nets": [
"DDR_D12"
]
}
]
},
{
"net": "DDR_D14",
"terminals": [
{
"component": "U1",
"ball": "L4",
"hints": [
"L4",
"DDR_D14_L4",
"pin65",
"65"
],
"nets": [
"DDR_D14"
]
},
{
"component": "U3",
"ball": "C8",
"hints": [
"C8",
"signal_DQU2",
"pin67",
"67"
],
"nets": [
"DDR_D14"
]
}
]
},
{
"net": "DDR_D1",
"terminals": [
{
"component": "U1",
"ball": "M4",
"hints": [
"M4",
"DDR_D1_M4",
"pin66",
"66"
],
"nets": [
"DDR_D1"
]
},
{
"component": "U3",
"ball": "G2",
"hints": [
"G2",
"signal_DQL6",
"pin23",
"23"
],
"nets": [
"DDR_D1"
]
}
]
},
{
"net": "DDR_D5",
"terminals": [
{
"component": "U1",
"ball": "N4",
"hints": [
"N4",
"DDR_D5_N4",
"pin67",
"67"
],
"nets": [
"DDR_D5"
]
},
{
"component": "U3",
"ball": "H7",
"hints": [
"H7",
"signal_DQL7",
"pin56",
"56"
],
"nets": [
"DDR_D5"
]
}
]
},
{
"net": "DDR_D7",
"terminals": [
{
"component": "U1",
"ball": "P4",
"hints": [
"P4",
"DDR_D7_P4",
"pin68",
"68"
],
"nets": [
"DDR_D7"
]
},
{
"component": "U3",
"ball": "H8",
"hints": [
"H8",
"signal_DQL5",
"pin72",
"72"
],
"nets": [
"DDR_D7"
]
}
]
},
{
"net": "DDR_A6",
"terminals": [
{
"component": "U1",
"ball": "D5",
"hints": [
"D5",
"DDR_A6_D5",
"pin76",
"76"
],
"nets": [
"DDR_A6"
]
},
{
"component": "U3",
"ball": "R8",
"hints": [
"R8",
"signal_A6",
"pin79",
"79"
],
"nets": [
"DDR_A6"
]
}
]
},
{
"net": "DDR_1V5",
"terminals": [
{
"component": "U1",
"ball": "E5",
"hints": [
"E5",
"VDDS_DDR_E5",
"pin77",
"77"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U1",
"ball": "F5",
"hints": [
"F5",
"VDDS_DDR_F5",
"pin78",
"78"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U1",
"ball": "G5",
"hints": [
"G5",
"VDDS_DDR_G5",
"pin79",
"79"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U1",
"ball": "H5",
"hints": [
"H5",
"VDDS_DDR_H5",
"pin80",
"80"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U1",
"ball": "J5",
"hints": [
"J5",
"VDDS_DDR_J5",
"pin81",
"81"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U1",
"ball": "K5",
"hints": [
"K5",
"VDDS_DDR_K5",
"pin82",
"82"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U1",
"ball": "L5",
"hints": [
"L5",
"VDDS_DDR_L5",
"pin83",
"83"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "A1",
"hints": [
"A1",
"signal_VDDQ1",
"pin1",
"1"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "C1",
"hints": [
"C1",
"signal_VDDQ2",
"pin3",
"3"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "F1",
"hints": [
"F1",
"signal_VDDQ3",
"pin6",
"6"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "N1",
"hints": [
"N1",
"signal_VDD1",
"pin13",
"13"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "R1",
"hints": [
"R1",
"signal_VDD2",
"pin15",
"15"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "B2",
"hints": [
"B2",
"signal_VDD3",
"pin18",
"18"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "D2",
"hints": [
"D2",
"signal_VDDQ4",
"pin20",
"20"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "H2",
"hints": [
"H2",
"signal_VDDQ5",
"pin24",
"24"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "K2",
"hints": [
"K2",
"signal_VDD4",
"pin26",
"26"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "G7",
"hints": [
"G7",
"signal_VDD5",
"pin55",
"55"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "A8",
"hints": [
"A8",
"signal_VDDQ6",
"pin65",
"65"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "K8",
"hints": [
"K8",
"signal_VDD6",
"pin74",
"74"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "C9",
"hints": [
"C9",
"signal_VDDQ7",
"pin83",
"83"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "D9",
"hints": [
"D9",
"signal_VDD7",
"pin84",
"84"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "E9",
"hints": [
"E9",
"signal_VDDQ8",
"pin85",
"85"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "H9",
"hints": [
"H9",
"signal_VDDQ9",
"pin88",
"88"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "N9",
"hints": [
"N9",
"signal_VDD8",
"pin93",
"93"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U3",
"ball": "R9",
"hints": [
"R9",
"signal_VDD9",
"pin95",
"95"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "U_PMIC",
"ball": "39",
"hints": [
"39",
"FB3_39",
"pin39"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "L_PWR3",
"ball": "pin2",
"hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_PWR9_B",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"1"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_PWR9",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"1"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "R_VREF_TOP",
"ball": "pin1",
"hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_VREF_TOP",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "R_DDR_RESET",
"ball": "pin2",
"hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_0",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_1",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_2",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_3",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_4",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_5",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_6",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_7",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_8",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_9",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_10",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_11",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_B",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_0",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_1",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_2",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_3",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_4",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_5",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_6",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_7",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_8",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_9",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_10",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_11",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_12",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_13",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_14",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_15",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_16",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_17",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_18",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_19",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_B0",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_SOC_DDR_B1",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
},
{
"component": "C_RAM_B1",
"ball": "pin1",
"hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"nets": [
"DDR_1V5"
]
}
]
},
{
"net": "DDR_ZQ",
"terminals": [
{
"component": "U3",
"ball": "L8",
"hints": [
"L8",
"signal_ZQ",
"pin75",
"75"
],
"nets": [
"DDR_ZQ"
]
},
{
"component": "R_DDR_ZQ",
"ball": "pin1",
"hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"nets": [
"DDR_ZQ"
]
}
]
}
],
"ddr_pin_mapping_checks": [
{
"component": "U1",
"ball": "B1",
"signal": "DDR_A5",
"expected": [
"DDR_A5"
],
"observed": [
"DDR_A5"
],
"pass": true
},
{
"component": "U1",
"ball": "C1",
"signal": "DDR_A9",
"expected": [
"DDR_A9"
],
"observed": [
"DDR_A9"
],
"pass": true
},
{
"component": "U1",
"ball": "D1",
"signal": "DDR_CKn",
"expected": [
"DDR_CKn"
],
"observed": [
"DDR_CKn"
],
"pass": true
},
{
"component": "U1",
"ball": "E1",
"signal": "DDR_BA1",
"expected": [
"DDR_BA1"
],
"observed": [
"DDR_BA1"
],
"pass": true
},
{
"component": "U1",
"ball": "F1",
"signal": "DDR_CASn",
"expected": [
"DDR_CASn"
],
"observed": [
"DDR_CASn"
],
"pass": true
},
{
"component": "U1",
"ball": "G1",
"signal": "DDR_ODT",
"expected": [
"DDR_ODT"
],
"observed": [
"DDR_ODT"
],
"pass": true
},
{
"component": "U1",
"ball": "H1",
"signal": "DDR_A1",
"expected": [
"DDR_A1"
],
"observed": [
"DDR_A1"
],
"pass": true
},
{
"component": "U1",
"ball": "J1",
"signal": "DDR_D8",
"expected": [
"DDR_D8"
],
"observed": [
"DDR_D8"
],
"pass": true
},
{
"component": "U1",
"ball": "K1",
"signal": "DDR_D9",
"expected": [
"DDR_D9"
],
"observed": [
"DDR_D9"
],
"pass": true
},
{
"component": "U1",
"ball": "L1",
"signal": "DDR_DQS1",
"expected": [
"DDR_DQS1"
],
"observed": [
"DDR_DQS1"
],
"pass": true
},
{
"component": "U1",
"ball": "M1",
"signal": "DDR_D15",
"expected": [
"DDR_D15"
],
"observed": [
"DDR_D15"
],
"pass": true
},
{
"component": "U1",
"ball": "N1",
"signal": "DDR_D2",
"expected": [
"DDR_D2"
],
"observed": [
"DDR_D2"
],
"pass": true
},
{
"component": "U1",
"ball": "P1",
"signal": "DDR_DQS0",
"expected": [
"DDR_DQS0"
],
"observed": [
"DDR_DQS0"
],
"pass": true
},
{
"component": "U1",
"ball": "B2",
"signal": "DDR_WEn",
"expected": [
"DDR_WEn"
],
"observed": [
"DDR_WEn"
],
"pass": true
},
{
"component": "U1",
"ball": "C2",
"signal": "DDR_A4",
"expected": [
"DDR_A4"
],
"observed": [
"DDR_A4"
],
"pass": true
},
{
"component": "U1",
"ball": "D2",
"signal": "DDR_CK",
"expected": [
"DDR_CK"
],
"observed": [
"DDR_CK"
],
"pass": true
},
{
"component": "U1",
"ball": "E2",
"signal": "DDR_A7",
"expected": [
"DDR_A7"
],
"observed": [
"DDR_A7"
],
"pass": true
},
{
"component": "U1",
"ball": "F2",
"signal": "DDR_A11",
"expected": [
"DDR_A11"
],
"observed": [
"DDR_A11"
],
"pass": true
},
{
"component": "U1",
"ball": "G2",
"signal": "DDR_RESETn",
"expected": [
"DDR_RESETn"
],
"observed": [
"DDR_RESETn"
],
"pass": true
},
{
"component": "U1",
"ball": "H2",
"signal": "DDR_CSn0",
"expected": [
"DDR_CSn0"
],
"observed": [
"DDR_CSn0"
],
"pass": true
},
{
"component": "U1",
"ball": "J2",
"signal": "DDR_DQM1",
"expected": [
"DDR_DQM1"
],
"observed": [
"DDR_DQM1"
],
"pass": true
},
{
"component": "U1",
"ball": "K2",
"signal": "DDR_D10",
"expected": [
"DDR_D10"
],
"observed": [
"DDR_D10"
],
"pass": true
},
{
"component": "U1",
"ball": "L2",
"signal": "DDR_DQSn1",
"expected": [
"DDR_DQSn1"
],
"observed": [
"DDR_DQSn1"
],
"pass": true
},
{
"component": "U1",
"ball": "M2",
"signal": "DDR_DQM0",
"expected": [
"DDR_DQM0"
],
"observed": [
"DDR_DQM0"
],
"pass": true
},
{
"component": "U1",
"ball": "N2",
"signal": "DDR_D3",
"expected": [
"DDR_D3"
],
"observed": [
"DDR_D3"
],
"pass": true
},
{
"component": "U1",
"ball": "P2",
"signal": "DDR_DQSn0",
"expected": [
"DDR_DQSn0"
],
"observed": [
"DDR_DQSn0"
],
"pass": true
},
{
"component": "U1",
"ball": "B3",
"signal": "DDR_BA2",
"expected": [
"DDR_BA2"
],
"observed": [
"DDR_BA2"
],
"pass": true
},
{
"component": "U1",
"ball": "C3",
"signal": "DDR_A3",
"expected": [
"DDR_A3"
],
"observed": [
"DDR_A3"
],
"pass": true
},
{
"component": "U1",
"ball": "D3",
"signal": "DDR_A15",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U1",
"ball": "E3",
"signal": "DDR_A12",
"expected": [
"DDR_A12"
],
"observed": [
"DDR_A12"
],
"pass": true
},
{
"component": "U1",
"ball": "F3",
"signal": "DDR_A0",
"expected": [
"DDR_A0"
],
"observed": [
"DDR_A0"
],
"pass": true
},
{
"component": "U1",
"ball": "G3",
"signal": "DDR_CKE",
"expected": [
"DDR_CKE"
],
"observed": [
"DDR_CKE"
],
"pass": true
},
{
"component": "U1",
"ball": "H3",
"signal": "DDR_A13",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U1",
"ball": "J3",
"signal": "DDR_VTP",
"expected": [
"DDR_VTP"
],
"observed": [
"DDR_VTP"
],
"pass": true
},
{
"component": "U1",
"ball": "K3",
"signal": "DDR_D11",
"expected": [
"DDR_D11"
],
"observed": [
"DDR_D11"
],
"pass": true
},
{
"component": "U1",
"ball": "L3",
"signal": "DDR_D13",
"expected": [
"DDR_D13"
],
"observed": [
"DDR_D13"
],
"pass": true
},
{
"component": "U1",
"ball": "M3",
"signal": "DDR_D0",
"expected": [
"DDR_D0"
],
"observed": [
"DDR_D0"
],
"pass": true
},
{
"component": "U1",
"ball": "N3",
"signal": "DDR_D4",
"expected": [
"DDR_D4"
],
"observed": [
"DDR_D4"
],
"pass": true
},
{
"component": "U1",
"ball": "P3",
"signal": "DDR_D6",
"expected": [
"DDR_D6"
],
"observed": [
"DDR_D6"
],
"pass": true
},
{
"component": "U1",
"ball": "C4",
"signal": "DDR_BA0",
"expected": [
"DDR_BA0"
],
"observed": [
"DDR_BA0"
],
"pass": true
},
{
"component": "U1",
"ball": "D4",
"signal": "DDR_A8",
"expected": [
"DDR_A8"
],
"observed": [
"DDR_A8"
],
"pass": true
},
{
"component": "U1",
"ball": "E4",
"signal": "DDR_A2",
"expected": [
"DDR_A2"
],
"observed": [
"DDR_A2"
],
"pass": true
},
{
"component": "U1",
"ball": "F4",
"signal": "DDR_A10",
"expected": [
"DDR_A10"
],
"observed": [
"DDR_A10"
],
"pass": true
},
{
"component": "U1",
"ball": "G4",
"signal": "DDR_RASn",
"expected": [
"DDR_RASn"
],
"observed": [
"DDR_RASn"
],
"pass": true
},
{
"component": "U1",
"ball": "H4",
"signal": "DDR_A14",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U1",
"ball": "J4",
"signal": "DDR_VREF",
"expected": [
"DDR_VREF"
],
"observed": [
"DDR_VREF"
],
"pass": true
},
{
"component": "U1",
"ball": "K4",
"signal": "DDR_D12",
"expected": [
"DDR_D12"
],
"observed": [
"DDR_D12"
],
"pass": true
},
{
"component": "U1",
"ball": "L4",
"signal": "DDR_D14",
"expected": [
"DDR_D14"
],
"observed": [
"DDR_D14"
],
"pass": true
},
{
"component": "U1",
"ball": "M4",
"signal": "DDR_D1",
"expected": [
"DDR_D1"
],
"observed": [
"DDR_D1"
],
"pass": true
},
{
"component": "U1",
"ball": "N4",
"signal": "DDR_D5",
"expected": [
"DDR_D5"
],
"observed": [
"DDR_D5"
],
"pass": true
},
{
"component": "U1",
"ball": "P4",
"signal": "DDR_D7",
"expected": [
"DDR_D7"
],
"observed": [
"DDR_D7"
],
"pass": true
},
{
"component": "U1",
"ball": "D5",
"signal": "DDR_A6",
"expected": [
"DDR_A6"
],
"observed": [
"DDR_A6"
],
"pass": true
},
{
"component": "U3",
"ball": "A1",
"signal": "VDDQ1",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "B1",
"signal": "VSSQ1",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "C1",
"signal": "VDDQ2",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "D1",
"signal": "VSSQ2",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "E1",
"signal": "VSS1",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "F1",
"signal": "VDDQ3",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "G1",
"signal": "VSSQ3",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "H1",
"signal": "VREFDQ",
"expected": [
"DDR_VREF"
],
"observed": [
"DDR_VREF"
],
"pass": true
},
{
"component": "U3",
"ball": "J1",
"signal": "NC1",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "K1",
"signal": "ODT",
"expected": [
"DDR_ODT"
],
"observed": [
"DDR_ODT"
],
"pass": true
},
{
"component": "U3",
"ball": "L1",
"signal": "NC2",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "M1",
"signal": "VSS2",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "N1",
"signal": "VDD1",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "P1",
"signal": "VSS3",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "R1",
"signal": "VDD2",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "T1",
"signal": "VSS4",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "A2",
"signal": "DQU5",
"expected": [
"DDR_D13"
],
"observed": [
"DDR_D12"
],
"pass": false
},
{
"component": "U3",
"ball": "B2",
"signal": "VDD3",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "C2",
"signal": "DQU3",
"expected": [
"DDR_D11"
],
"observed": [
"DDR_D11"
],
"pass": true
},
{
"component": "U3",
"ball": "D2",
"signal": "VDDQ4",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "E2",
"signal": "VSSQ4",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "F2",
"signal": "DQL2",
"expected": [
"DDR_D2"
],
"observed": [
"DDR_D0"
],
"pass": false
},
{
"component": "U3",
"ball": "G2",
"signal": "DQL6",
"expected": [
"DDR_D6"
],
"observed": [
"DDR_D1"
],
"pass": false
},
{
"component": "U3",
"ball": "H2",
"signal": "VDDQ5",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "J2",
"signal": "VSS5",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "K2",
"signal": "VDD4",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "L2",
"signal": "N_CS",
"expected": [
"DDR_CSn0"
],
"observed": [
"DDR_CSn0"
],
"pass": true
},
{
"component": "U3",
"ball": "M2",
"signal": "BA0",
"expected": [
"DDR_BA0"
],
"observed": [
"DDR_BA0"
],
"pass": true
},
{
"component": "U3",
"ball": "N2",
"signal": "A3",
"expected": [
"DDR_A3"
],
"observed": [
"DDR_A3"
],
"pass": true
},
{
"component": "U3",
"ball": "P2",
"signal": "A5",
"expected": [
"DDR_A5"
],
"observed": [
"DDR_A5"
],
"pass": true
},
{
"component": "U3",
"ball": "R2",
"signal": "A7",
"expected": [
"DDR_A7"
],
"observed": [
"DDR_A7"
],
"pass": true
},
{
"component": "U3",
"ball": "T2",
"signal": "N_RESET",
"expected": [
"DDR_RESETn"
],
"observed": [
"DDR_RESETn"
],
"pass": true
},
{
"component": "U3",
"ball": "A3",
"signal": "DQU7",
"expected": [
"DDR_D15"
],
"observed": [
"DDR_D10"
],
"pass": false
},
{
"component": "U3",
"ball": "B3",
"signal": "VSS6",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "C3",
"signal": "DQU1",
"expected": [
"DDR_D9"
],
"observed": [
"DDR_D8"
],
"pass": false
},
{
"component": "U3",
"ball": "D3",
"signal": "DMU",
"expected": [
"DDR_DQM1"
],
"observed": [
"DDR_DQM1"
],
"pass": true
},
{
"component": "U3",
"ball": "E3",
"signal": "DQL0",
"expected": [
"DDR_D0"
],
"observed": [
"DDR_D2"
],
"pass": false
},
{
"component": "U3",
"ball": "F3",
"signal": "DQSL",
"expected": [
"DDR_DQS0"
],
"observed": [
"DDR_DQS0"
],
"pass": true
},
{
"component": "U3",
"ball": "G3",
"signal": "N_DQSl",
"expected": [
"DDR_DQSn0"
],
"observed": [
"DDR_DQSn0"
],
"pass": true
},
{
"component": "U3",
"ball": "H3",
"signal": "DQL4",
"expected": [
"DDR_D4"
],
"observed": [
"DDR_D3"
],
"pass": false
},
{
"component": "U3",
"ball": "J3",
"signal": "N_RAS",
"expected": [
"DDR_RASn"
],
"observed": [
"DDR_RASn"
],
"pass": true
},
{
"component": "U3",
"ball": "K3",
"signal": "N_CAS",
"expected": [
"DDR_CASn"
],
"observed": [
"DDR_CASn"
],
"pass": true
},
{
"component": "U3",
"ball": "L3",
"signal": "N_WE",
"expected": [
"DDR_WEn"
],
"observed": [
"DDR_WEn"
],
"pass": true
},
{
"component": "U3",
"ball": "M3",
"signal": "BA2",
"expected": [
"DDR_BA2"
],
"observed": [
"DDR_BA2"
],
"pass": true
},
{
"component": "U3",
"ball": "N3",
"signal": "A0",
"expected": [
"DDR_A0"
],
"observed": [
"DDR_A0"
],
"pass": true
},
{
"component": "U3",
"ball": "P3",
"signal": "A2",
"expected": [
"DDR_A2"
],
"observed": [
"DDR_A2"
],
"pass": true
},
{
"component": "U3",
"ball": "R3",
"signal": "A9",
"expected": [
"DDR_A9"
],
"observed": [
"DDR_A9"
],
"pass": true
},
{
"component": "U3",
"ball": "T3",
"signal": "NC3",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "A7",
"signal": "DQU4",
"expected": [
"DDR_D12"
],
"observed": [
"DDR_D13"
],
"pass": false
},
{
"component": "U3",
"ball": "B7",
"signal": "N_DQSU",
"expected": [
"DDR_DQSn1"
],
"observed": [
"DDR_DQSn1"
],
"pass": true
},
{
"component": "U3",
"ball": "C7",
"signal": "DQSU",
"expected": [
"DDR_DQS1"
],
"observed": [
"DDR_DQS1"
],
"pass": true
},
{
"component": "U3",
"ball": "D7",
"signal": "DQU0",
"expected": [
"DDR_D8"
],
"observed": [
"DDR_D9"
],
"pass": false
},
{
"component": "U3",
"ball": "E7",
"signal": "DML",
"expected": [
"DDR_DQM0"
],
"observed": [
"DDR_DQM0"
],
"pass": true
},
{
"component": "U3",
"ball": "F7",
"signal": "DQL1",
"expected": [
"DDR_D1"
],
"observed": [
"DDR_D6"
],
"pass": false
},
{
"component": "U3",
"ball": "G7",
"signal": "VDD5",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "H7",
"signal": "DQL7",
"expected": [
"DDR_D7"
],
"observed": [
"DDR_D5"
],
"pass": false
},
{
"component": "U3",
"ball": "J7",
"signal": "CK",
"expected": [
"DDR_CK"
],
"observed": [
"DDR_CK"
],
"pass": true
},
{
"component": "U3",
"ball": "K7",
"signal": "N_CK",
"expected": [
"DDR_CKn"
],
"observed": [
"DDR_CKn"
],
"pass": true
},
{
"component": "U3",
"ball": "L7",
"signal": "A10",
"expected": [
"DDR_A10"
],
"observed": [
"DDR_A10"
],
"pass": true
},
{
"component": "U3",
"ball": "M7",
"signal": "NC4",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "N7",
"signal": "A12",
"expected": [
"DDR_A12"
],
"observed": [
"DDR_A12"
],
"pass": true
},
{
"component": "U3",
"ball": "P7",
"signal": "A1",
"expected": [
"DDR_A1"
],
"observed": [
"DDR_A1"
],
"pass": true
},
{
"component": "U3",
"ball": "R7",
"signal": "A11",
"expected": [
"DDR_A11"
],
"observed": [
"DDR_A11"
],
"pass": true
},
{
"component": "U3",
"ball": "T7",
"signal": "NC5",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "A8",
"signal": "VDDQ6",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "B8",
"signal": "DQU6",
"expected": [
"DDR_D14"
],
"observed": [
"DDR_D15"
],
"pass": false
},
{
"component": "U3",
"ball": "C8",
"signal": "DQU2",
"expected": [
"DDR_D10"
],
"observed": [
"DDR_D14"
],
"pass": false
},
{
"component": "U3",
"ball": "D8",
"signal": "VSSQ5",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "E8",
"signal": "VSSQ6",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "F8",
"signal": "DQL3",
"expected": [
"DDR_D3"
],
"observed": [
"DDR_D4"
],
"pass": false
},
{
"component": "U3",
"ball": "G8",
"signal": "VSS7",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "H8",
"signal": "DQL5",
"expected": [
"DDR_D5"
],
"observed": [
"DDR_D7"
],
"pass": false
},
{
"component": "U3",
"ball": "J8",
"signal": "VSS8",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "K8",
"signal": "VDD6",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "L8",
"signal": "ZQ",
"expected": [
"DDR_ZQ"
],
"observed": [
"DDR_ZQ"
],
"pass": true
},
{
"component": "U3",
"ball": "M8",
"signal": "VREFCA",
"expected": [
"DDR_VREF"
],
"observed": [
"DDR_VREF"
],
"pass": true
},
{
"component": "U3",
"ball": "N8",
"signal": "BA1",
"expected": [
"DDR_BA1"
],
"observed": [
"DDR_BA1"
],
"pass": true
},
{
"component": "U3",
"ball": "P8",
"signal": "A4",
"expected": [
"DDR_A4"
],
"observed": [
"DDR_A4"
],
"pass": true
},
{
"component": "U3",
"ball": "R8",
"signal": "A6",
"expected": [
"DDR_A6"
],
"observed": [
"DDR_A6"
],
"pass": true
},
{
"component": "U3",
"ball": "T8",
"signal": "A8",
"expected": [
"DDR_A8"
],
"observed": [
"DDR_A8"
],
"pass": true
},
{
"component": "U3",
"ball": "A9",
"signal": "VSS9",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "B9",
"signal": "VSSQ7",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "C9",
"signal": "VDDQ7",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "D9",
"signal": "VDD7",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "E9",
"signal": "VDDQ8",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "F9",
"signal": "VSSQ8",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "G9",
"signal": "VSSQ9",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "H9",
"signal": "VDDQ9",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "J9",
"signal": "NC6",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "K9",
"signal": "CKE",
"expected": [
"DDR_CKE"
],
"observed": [
"DDR_CKE"
],
"pass": true
},
{
"component": "U3",
"ball": "L9",
"signal": "NC7",
"expected": [],
"observed": [],
"pass": true
},
{
"component": "U3",
"ball": "M9",
"signal": "VSS10",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "N9",
"signal": "VDD8",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "P9",
"signal": "VSS11",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
},
{
"component": "U3",
"ball": "R9",
"signal": "VDD9",
"expected": [
"DDR_1V5"
],
"observed": [
"DDR_1V5"
],
"pass": true
},
{
"component": "U3",
"ball": "T9",
"signal": "VSS12",
"expected": [
"GND"
],
"observed": [
"GND"
],
"pass": true
}
],
"ddr_resistors": [
{
"are_pins_interchangeable": true,
"display_resistance": "240\u03a9",
"ftype": "simple_resistor",
"name": "R_DDR_ZQ",
"resistance": 240,
"source_component_id": "source_component_95",
"source_group_id": "source_group_0",
"type": "source_component"
},
{
"are_pins_interchangeable": true,
"display_resistance": "49.9\u03a9",
"ftype": "simple_resistor",
"name": "R_DDR_VTP",
"resistance": 49.9,
"source_component_id": "source_component_96",
"source_group_id": "source_group_0",
"type": "source_component"
},
{
"are_pins_interchangeable": true,
"display_resistance": "1k\u03a9",
"ftype": "simple_resistor",
"name": "R_VREF_TOP",
"resistance": 1000,
"source_component_id": "source_component_97",
"source_group_id": "source_group_0",
"type": "source_component"
},
{
"are_pins_interchangeable": true,
"display_resistance": "1k\u03a9",
"ftype": "simple_resistor",
"name": "R_VREF_BOT",
"resistance": 1000,
"source_component_id": "source_component_98",
"source_group_id": "source_group_0",
"type": "source_component"
},
{
"are_pins_interchangeable": true,
"display_resistance": "10k\u03a9",
"ftype": "simple_resistor",
"name": "R_DDR_RESET",
"resistance": 10000,
"source_component_id": "source_component_104",
"source_group_id": "source_group_0",
"type": "source_component"
}
],
"unconnected_cpu_ddr_pins": [
{
"component": "U1",
"ball": "D3",
"hints": [
"D3",
"DDR_A15_D3",
"pin40",
"40"
],
"nets": []
},
{
"component": "U1",
"ball": "H3",
"hints": [
"H3",
"DDR_A13_H3",
"pin44",
"44"
],
"nets": []
},
{
"component": "U1",
"ball": "H4",
"hints": [
"H4",
"DDR_A14_H4",
"pin62",
"62"
],
"nets": []
}
],
"physical_groups": [
{
"root": "806",
"nets": [
"GND"
],
"objects": [
"baseline_bulk_ground_cf688492_C_PWR1",
"baseline_bulk_ground_cf688492_C_PWR12_B",
"baseline_bulk_ground_cf688492_C_PWR5",
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan",
"baseline_closure_0352998a_U_CLOCK_GATE_3_clock_ground_coplan_via_0",
"baseline_closure_170d9ee6_C_VDDS_RTC_repositioned_return",
"baseline_closure_2019bfbf_R_BOOT10_ground_surface",
"baseline_closure_5a412b81_C_PWR6_pin2_rotated_local",
"baseline_closure_601df44b_C_VDDS_RTC_pin2_existing",
"baseline_closure_601df44b_C_VREF_2_pin2_existing",
"baseline_closure_baf2699b_C_CAP_VBB_MPU_local_return",
"baseline_closure_bf77cf69_C_EFUSE_OUT_pin2_existing",
"baseline_closure_bf77cf69_C_INPUT_DVDT_pin2_existing",
"baseline_closure_bf77cf69_C_IO1_0_pin2_existing",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0",
"baseline_closure_bf77cf69_C_IO1_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0",
"baseline_closure_bf77cf69_C_IO2_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0",
"baseline_closure_bf77cf69_C_IO3_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO4_0_pin2_existing",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0",
"baseline_closure_bf77cf69_C_IO4_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0",
"baseline_closure_bf77cf69_C_IO6_B_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDA1P8V_USB0_pin2_existing",
"baseline_closure_bf77cf69_C_VDDA3P3V_USB0_pin2_existing",
"baseline_closure_bf77cf69_C_VDDS_1_pin2_existing",
"baseline_closure_bf77cf69_C_VDDS_2_pin2_existing",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0",
"baseline_closure_bf77cf69_C_VDDS_OSC_pin2_tap0_via_0",
"baseline_closure_bf77cf69_C_VDD_CORE_0_pin2_existing",
"baseline_closure_bf77cf69_C_VDD_CORE_5_pin2_existing",
"baseline_closure_bf77cf69_C_VDD_MPU_0_pin2_existing",
"baseline_closure_bf77cf69_C_VDD_MPU_1_pin2_existing",
"baseline_closure_bf77cf69_C_VDD_MPU_2_pin2_existing",
"baseline_closure_bf77cf69_C_VDD_MPU_4_pin2_existing",
"baseline_closure_bf77cf69_J_POWER_A12_tap0",
"baseline_closure_bf77cf69_J_POWER_A12_tap0_via_0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0",
"baseline_closure_bf77cf69_J_POWER_A1_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT11_pin2_existing",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0",
"baseline_closure_bf77cf69_R_BOOT5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT6_pin2_existing",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0",
"baseline_closure_bf77cf69_R_CLOCK_OE_PD_pin2_tap0_via_0",
"baseline_closure_bf77cf69_U_INPUT_EFUSE_9_existing",
"baseline_closure_c0cec685_C_PWR11_pin2_existing",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0",
"baseline_closure_cd4b9ff3_C_IO5_B_pin2_tap0_via_0",
"baseline_closure_e3a22c67_C_RTC_LDO_local_return",
"baseline_closure_eac3f412_Y_SOC_ground_coplan",
"baseline_closure_f3643d14_C_CAP_VDD_SRAM_CORE_return",
"baseline_closure_f3643d14_C_CAP_VDD_SRAM_MPU_return",
"baseline_closure_f3643d14_MPU_bulk_relocation_return",
"baseline_closure_f3643d14_MPU_bulk_relocation_return_via_0",
"baseline_closure_f87fbb58_C_VDDS_3_repositioned_return",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0",
"baseline_closure_fcadd8db_C_PWR10_B_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0",
"baseline_closure_fcadd8db_C_PWR10_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0",
"baseline_closure_fcadd8db_C_PWR12_pin2_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR13_pin2_tap0",
"baseline_closure_fcadd8db_C_PWR13_pin2_tap0_via_0",
"baseline_closure_fcadd8db_R_PWR1_pin2_tap0",
"baseline_closure_fcadd8db_R_PWR1_pin2_tap0_via_0",
"baseline_closure_feceddc7_R_BOOT6_return_contact_coplan",
"baseline_ddr_cap_222cd283_pcb_port_920",
"baseline_ddr_cap_222cd283_pcb_port_920_via",
"baseline_ddr_cap_4c88c897_pcb_port_702",
"baseline_ddr_cap_4c88c897_pcb_port_702_via",
"baseline_ddr_cap_4c88c897_pcb_port_704",
"baseline_ddr_cap_4c88c897_pcb_port_704_via",
"baseline_ddr_cap_4c88c897_pcb_port_914",
"baseline_ddr_cap_4c88c897_pcb_port_914_via",
"baseline_ddr_cap_4c88c897_pcb_port_918",
"baseline_ddr_cap_4c88c897_pcb_port_918_via",
"baseline_ddr_cap_4c88c897_pcb_port_926",
"baseline_ddr_cap_4c88c897_pcb_port_926_via",
"baseline_ddr_cap_4c88c897_pcb_port_930",
"baseline_ddr_cap_4c88c897_pcb_port_930_via",
"baseline_ddr_cap_4c88c897_pcb_port_932",
"baseline_ddr_cap_4c88c897_pcb_port_932_via",
"baseline_ddr_cap_4c88c897_pcb_port_936",
"baseline_ddr_cap_4c88c897_pcb_port_936_via",
"baseline_ddr_cap_4c88c897_pcb_port_938",
"baseline_ddr_cap_4c88c897_pcb_port_938_via",
"baseline_ddr_cap_711ac343_pcb_port_910",
"baseline_ddr_cap_711ac343_pcb_port_910_via",
"baseline_ddr_cap_d36217b1_pcb_port_708",
"baseline_ddr_cap_d36217b1_pcb_port_708_via",
"baseline_ddr_cap_d36217b1_pcb_port_906",
"baseline_ddr_cap_d36217b1_pcb_port_906_via",
"baseline_ddr_cap_d36217b1_pcb_port_908",
"baseline_ddr_cap_d36217b1_pcb_port_908_via",
"baseline_ddr_cap_d36217b1_pcb_port_912",
"baseline_ddr_cap_d36217b1_pcb_port_912_via",
"baseline_ddr_cap_d36217b1_pcb_port_924",
"baseline_ddr_cap_d36217b1_pcb_port_924_via",
"baseline_ground_group_0",
"baseline_ground_group_0_via",
"baseline_ground_group_14",
"baseline_ground_group_14_via",
"baseline_ground_group_18",
"baseline_ground_group_18_via",
"baseline_ground_group_20_via",
"baseline_ground_group_22",
"baseline_ground_group_22_via",
"baseline_ground_group_26",
"baseline_ground_group_26_via",
"baseline_ground_group_32",
"baseline_ground_group_32_via",
"baseline_ground_group_38",
"baseline_ground_group_38_via",
"baseline_ground_group_42",
"baseline_ground_group_42_via",
"baseline_ground_group_44",
"baseline_ground_group_44_via",
"baseline_ground_group_46",
"baseline_ground_group_46_via",
"baseline_ground_group_48",
"baseline_ground_group_48_via",
"baseline_ground_group_50",
"baseline_ground_group_50_via",
"baseline_ground_group_54",
"baseline_ground_group_54_via",
"baseline_ground_group_56",
"baseline_ground_group_56_via",
"baseline_ground_group_58",
"baseline_ground_group_58_via",
"baseline_ground_group_76",
"baseline_ground_group_76_via",
"baseline_ground_group_80",
"baseline_ground_group_80_via",
"baseline_ground_group_82",
"baseline_ground_group_82_via",
"baseline_ground_group_84",
"baseline_ground_group_84_via",
"baseline_ground_group_86",
"baseline_ground_group_86_via",
"baseline_ground_group_88",
"baseline_ground_group_88_via",
"baseline_ground_group_90",
"baseline_ground_group_90_via",
"baseline_ground_tie_46c7916b_0",
"baseline_ground_tie_46c7916b_0_via",
"baseline_ground_tie_46c7916b_2",
"baseline_ground_tie_46c7916b_2_via",
"baseline_ground_tie_4ec28b62_0",
"baseline_ground_tie_4ec28b62_0_via",
"baseline_ground_tie_50b997d1_0",
"baseline_ground_tie_50b997d1_0_via",
"baseline_ground_tie_50b997d1_2",
"baseline_ground_tie_50b997d1_2_via",
"baseline_ground_tie_50b997d1_4",
"baseline_ground_tie_50b997d1_4_via",
"baseline_ground_tie_50b997d1_6",
"baseline_ground_tie_50b997d1_6_via",
"baseline_ground_tie_50b997d1_8",
"baseline_ground_tie_50b997d1_8_via",
"baseline_ground_tie_aaf8fa10_0",
"baseline_ground_tie_aaf8fa10_0_via",
"baseline_ground_tie_aaf8fa10_12",
"baseline_ground_tie_aaf8fa10_12_via",
"baseline_ground_tie_aaf8fa10_14",
"baseline_ground_tie_aaf8fa10_14_via",
"baseline_ground_tie_aaf8fa10_16",
"baseline_ground_tie_aaf8fa10_16_via",
"baseline_ground_tie_aaf8fa10_18",
"baseline_ground_tie_aaf8fa10_18_via",
"baseline_ground_tie_aaf8fa10_20",
"baseline_ground_tie_aaf8fa10_20_via",
"baseline_ground_tie_aaf8fa10_22",
"baseline_ground_tie_aaf8fa10_22_via",
"baseline_ground_tie_aaf8fa10_24",
"baseline_ground_tie_aaf8fa10_24_via",
"baseline_ground_tie_aaf8fa10_26",
"baseline_ground_tie_aaf8fa10_26_via",
"baseline_ground_tie_aaf8fa10_28",
"baseline_ground_tie_aaf8fa10_28_via",
"baseline_ground_tie_aaf8fa10_30",
"baseline_ground_tie_aaf8fa10_30_via",
"baseline_ground_tie_aaf8fa10_32",
"baseline_ground_tie_aaf8fa10_32_via",
"baseline_ground_tie_aaf8fa10_36",
"baseline_ground_tie_aaf8fa10_36_via",
"baseline_ground_tie_aaf8fa10_38",
"baseline_ground_tie_aaf8fa10_38_via",
"baseline_ground_tie_aaf8fa10_48",
"baseline_ground_tie_aaf8fa10_48_via",
"baseline_ground_tie_aaf8fa10_4_via",
"baseline_ground_tie_aaf8fa10_52",
"baseline_ground_tie_aaf8fa10_52_via",
"baseline_ground_tie_aaf8fa10_54",
"baseline_ground_tie_aaf8fa10_54_via",
"baseline_ground_tie_aaf8fa10_56",
"baseline_ground_tie_aaf8fa10_56_via",
"baseline_ground_tie_aaf8fa10_58",
"baseline_ground_tie_aaf8fa10_58_via",
"baseline_ground_tie_aaf8fa10_6",
"baseline_ground_tie_aaf8fa10_6_via",
"baseline_ground_tie_aaf8fa10_8",
"baseline_ground_tie_aaf8fa10_8_via",
"baseline_ground_tie_f558468f_12",
"baseline_ground_tie_f558468f_12_via",
"baseline_local_support_0",
"baseline_local_support_1",
"baseline_local_support_10",
"baseline_local_support_12",
"baseline_local_support_13",
"baseline_local_support_2",
"baseline_local_support_22",
"baseline_local_support_29",
"baseline_local_support_32",
"baseline_local_support_37",
"baseline_local_support_4",
"baseline_local_support_56",
"baseline_local_support_6",
"baseline_local_support_7",
"baseline_local_support_79",
"baseline_local_support_8",
"baseline_local_support_82",
"baseline_local_support_84",
"baseline_local_support_98",
"baseline_pcb_copper_pour_0_0",
"baseline_pcb_copper_pour_1_0",
"baseline_pcb_copper_pour_1_2",
"baseline_pcb_via_6",
"baseline_pcb_via_7",
"baseline_pcb_via_8",
"baseline_pcb_via_9",
"baseline_pmic_ep_0b9ad337_21",
"baseline_pmic_ep_0b9ad337_22",
"baseline_pmic_ep_0b9ad337_23",
"baseline_pmic_ep_0b9ad337_24",
"baseline_pmic_ep_0b9ad337_27",
"baseline_pmic_ep_0b9ad337_30",
"baseline_pmic_ep_0b9ad337_31",
"baseline_pmic_ep_0b9ad337_32",
"baseline_pmic_ep_0b9ad337_33",
"baseline_pmic_ep_0b9ad337_9",
"baseline_pmic_ep_2f1fae58_20",
"baseline_pmic_ep_2f1fae58_25",
"baseline_pmic_thermal_0_0",
"baseline_pmic_thermal_0_1",
"baseline_pmic_thermal_0_2",
"baseline_pmic_thermal_0_3",
"baseline_pmic_thermal_0_4",
"baseline_pmic_thermal_1_0",
"baseline_pmic_thermal_1_1",
"baseline_pmic_thermal_1_2",
"baseline_pmic_thermal_1_3",
"baseline_pmic_thermal_1_4",
"baseline_pmic_thermal_2_0",
"baseline_pmic_thermal_2_1",
"baseline_pmic_thermal_2_2",
"baseline_pmic_thermal_2_3",
"baseline_pmic_thermal_2_4",
"baseline_pmic_thermal_3_0",
"baseline_pmic_thermal_3_1",
"baseline_pmic_thermal_3_2",
"baseline_pmic_thermal_3_3",
"baseline_pmic_thermal_3_4",
"baseline_pmic_thermal_4_0",
"baseline_pmic_thermal_4_1",
"baseline_pmic_thermal_4_2",
"baseline_pmic_thermal_4_3",
"baseline_pmic_thermal_4_4",
"baseline_processor_feed_118153d7_0_bulk_C_PWR7_B_load_GND",
"baseline_processor_feed_118153d7_0_bulk_C_PWR7_B_load_GND_via",
"baseline_processor_feed_118153d7_1_bulk_C_PWR7_B_load_GND",
"baseline_processor_feed_118153d7_1_bulk_C_PWR7_B_load_GND_via",
"baseline_processor_feed_19935a11_0_bulk_C_PWR4_load_GND",
"baseline_processor_feed_19935a11_0_bulk_C_PWR4_load_GND_via",
"baseline_processor_feed_19935a11_1_bulk_C_PWR4_load_GND",
"baseline_processor_feed_19935a11_1_bulk_C_PWR4_load_GND_via",
"baseline_processor_feed_4e1f9589_0_bulk_C_PWR9_load_GND",
"baseline_processor_feed_4e1f9589_0_bulk_C_PWR9_load_GND_via",
"baseline_processor_feed_4e1f9589_1_bulk_C_PWR9_load_GND",
"baseline_processor_feed_4e1f9589_1_bulk_C_PWR9_load_GND_via",
"baseline_processor_feed_574b0915_0_bulk_C_PWR8_load_GND",
"baseline_processor_feed_574b0915_0_bulk_C_PWR8_load_GND_via",
"baseline_processor_feed_574b0915_1_bulk_C_PWR8_load_GND",
"baseline_processor_feed_574b0915_1_bulk_C_PWR8_load_GND_via",
"baseline_processor_feed_6fb36306_0_bulk_C_PWR2_load_GND",
"baseline_processor_feed_6fb36306_0_bulk_C_PWR2_load_GND_via",
"baseline_processor_feed_6fb36306_1_bulk_C_PWR2_load_GND",
"baseline_processor_feed_6fb36306_1_bulk_C_PWR2_load_GND_via",
"baseline_processor_feed_735dfb9c_0_bulk_C_PWR3_load_GND",
"baseline_processor_feed_735dfb9c_0_bulk_C_PWR3_load_GND_via",
"baseline_processor_feed_735dfb9c_1_bulk_C_PWR3_load_GND",
"baseline_processor_feed_735dfb9c_1_bulk_C_PWR3_load_GND_via",
"baseline_processor_feed_8e30f9d1_0_bulk_C_PWR7_load_GND",
"baseline_processor_feed_8e30f9d1_0_bulk_C_PWR7_load_GND_via",
"baseline_processor_feed_8e30f9d1_1_bulk_C_PWR7_load_GND",
"baseline_processor_feed_8e30f9d1_1_bulk_C_PWR7_load_GND_via",
"baseline_processor_feed_cdc2f4e2_0_bulk_U_PMIC_load_GND_via",
"baseline_processor_feed_cdc2f4e2_1_bulk_U_PMIC_load_GND_via",
"baseline_processor_feed_e8df21d9_0_bulk_C_PWR9_B_load_GND",
"baseline_processor_feed_e8df21d9_0_bulk_C_PWR9_B_load_GND_via",
"baseline_processor_feed_e8df21d9_1_bulk_C_PWR9_B_load_GND",
"baseline_processor_feed_e8df21d9_1_bulk_C_PWR9_B_load_GND_via",
"baseline_processor_feed_fc20a2e1_0_bulk_C_PWR8_B_load_GND",
"baseline_processor_feed_fc20a2e1_0_bulk_C_PWR8_B_load_GND_via",
"baseline_processor_feed_fc20a2e1_1_bulk_C_PWR8_B_load_GND",
"baseline_processor_feed_fc20a2e1_1_bulk_C_PWR8_B_load_GND_via",
"baseline_ram_decap_C_RAM_0_2",
"baseline_ram_decap_C_RAM_0_2_via",
"baseline_ram_decap_C_RAM_10_2",
"baseline_ram_decap_C_RAM_10_2_via",
"baseline_ram_decap_C_RAM_11_2",
"baseline_ram_decap_C_RAM_11_2_via",
"baseline_ram_decap_C_RAM_1_2",
"baseline_ram_decap_C_RAM_1_2_via",
"baseline_ram_decap_C_RAM_2_2",
"baseline_ram_decap_C_RAM_2_2_via",
"baseline_ram_decap_C_RAM_3_2",
"baseline_ram_decap_C_RAM_3_2_via",
"baseline_ram_decap_C_RAM_4_2",
"baseline_ram_decap_C_RAM_4_2_via",
"baseline_ram_decap_C_RAM_5_2",
"baseline_ram_decap_C_RAM_5_2_via",
"baseline_ram_decap_C_RAM_6_2",
"baseline_ram_decap_C_RAM_6_2_via",
"baseline_ram_decap_C_RAM_7_2",
"baseline_ram_decap_C_RAM_7_2_via",
"baseline_ram_decap_C_RAM_8_2",
"baseline_ram_decap_C_RAM_8_2_via",
"baseline_ram_decap_C_RAM_9_2",
"baseline_ram_decap_C_RAM_9_2_via",
"baseline_signal_ground_tie_c9b29687_0",
"baseline_signal_ground_tie_c9b29687_0_via",
"baseline_signal_ground_tie_c9b29687_10",
"baseline_signal_ground_tie_c9b29687_10_via",
"baseline_signal_ground_tie_c9b29687_12",
"baseline_signal_ground_tie_c9b29687_12_via",
"baseline_signal_ground_tie_c9b29687_14",
"baseline_signal_ground_tie_c9b29687_14_via",
"baseline_signal_ground_tie_c9b29687_16",
"baseline_signal_ground_tie_c9b29687_16_via",
"baseline_signal_ground_tie_c9b29687_18",
"baseline_signal_ground_tie_c9b29687_18_via",
"baseline_signal_ground_tie_c9b29687_2",
"baseline_signal_ground_tie_c9b29687_20",
"baseline_signal_ground_tie_c9b29687_20_via",
"baseline_signal_ground_tie_c9b29687_22",
"baseline_signal_ground_tie_c9b29687_22_via",
"baseline_signal_ground_tie_c9b29687_24",
"baseline_signal_ground_tie_c9b29687_24_via",
"baseline_signal_ground_tie_c9b29687_26",
"baseline_signal_ground_tie_c9b29687_26_via",
"baseline_signal_ground_tie_c9b29687_28",
"baseline_signal_ground_tie_c9b29687_28_via",
"baseline_signal_ground_tie_c9b29687_2_via",
"baseline_signal_ground_tie_c9b29687_30",
"baseline_signal_ground_tie_c9b29687_30_via",
"baseline_signal_ground_tie_c9b29687_32",
"baseline_signal_ground_tie_c9b29687_32_via",
"baseline_signal_ground_tie_c9b29687_34",
"baseline_signal_ground_tie_c9b29687_34_via",
"baseline_signal_ground_tie_c9b29687_36",
"baseline_signal_ground_tie_c9b29687_36_via",
"baseline_signal_ground_tie_c9b29687_38",
"baseline_signal_ground_tie_c9b29687_38_via",
"baseline_signal_ground_tie_c9b29687_4",
"baseline_signal_ground_tie_c9b29687_40",
"baseline_signal_ground_tie_c9b29687_40_via",
"baseline_signal_ground_tie_c9b29687_42",
"baseline_signal_ground_tie_c9b29687_42_via",
"baseline_signal_ground_tie_c9b29687_44",
"baseline_signal_ground_tie_c9b29687_44_via",
"baseline_signal_ground_tie_c9b29687_46",
"baseline_signal_ground_tie_c9b29687_46_via",
"baseline_signal_ground_tie_c9b29687_48",
"baseline_signal_ground_tie_c9b29687_48_via",
"baseline_signal_ground_tie_c9b29687_4_via",
"baseline_signal_ground_tie_c9b29687_50",
"baseline_signal_ground_tie_c9b29687_50_via",
"baseline_signal_ground_tie_c9b29687_52",
"baseline_signal_ground_tie_c9b29687_52_via",
"baseline_signal_ground_tie_c9b29687_54",
"baseline_signal_ground_tie_c9b29687_54_via",
"baseline_signal_ground_tie_c9b29687_56",
"baseline_signal_ground_tie_c9b29687_56_via",
"baseline_signal_ground_tie_c9b29687_6",
"baseline_signal_ground_tie_c9b29687_6_via",
"baseline_signal_ground_tie_c9b29687_8",
"baseline_signal_ground_tie_c9b29687_8_via",
"baseline_support_escape_U1_A1",
"baseline_support_escape_U1_A18",
"baseline_support_escape_U1_A5",
"baseline_support_escape_U1_A7",
"baseline_support_escape_U1_A8",
"baseline_support_escape_U1_A9",
"baseline_support_escape_U1_B6",
"baseline_support_escape_U1_B7",
"baseline_support_escape_U1_B8",
"baseline_support_escape_U1_B9",
"baseline_support_escape_U1_C7",
"baseline_support_escape_U1_C8",
"baseline_support_escape_U1_C9",
"baseline_support_escape_U1_D8",
"baseline_support_escape_U1_E8",
"baseline_support_escape_U1_F8",
"baseline_support_escape_U1_G11",
"baseline_support_escape_U1_G12",
"baseline_support_escape_U1_G8",
"baseline_support_escape_U1_G9",
"baseline_support_escape_U1_H10",
"baseline_support_escape_U1_H12",
"baseline_support_escape_U1_H6",
"baseline_support_escape_U1_H7",
"baseline_support_escape_U1_H8",
"baseline_support_escape_U1_H9",
"baseline_support_escape_U1_J10",
"baseline_support_escape_U1_J11",
"baseline_support_escape_U1_J6",
"baseline_support_escape_U1_J7",
"baseline_support_escape_U1_J8",
"baseline_support_escape_U1_J9",
"baseline_support_escape_U1_K10",
"baseline_support_escape_U1_K11",
"baseline_support_escape_U1_K7",
"baseline_support_escape_U1_K9",
"baseline_support_escape_U1_L10",
"baseline_support_escape_U1_L11",
"baseline_support_escape_U1_L12",
"baseline_support_escape_U1_L13",
"baseline_support_escape_U1_M10",
"baseline_support_escape_U1_M12",
"baseline_support_escape_U1_M14",
"baseline_support_escape_U1_M6",
"baseline_support_escape_U1_M7",
"baseline_support_escape_U1_M8",
"baseline_support_escape_U1_M9",
"baseline_support_escape_U1_N10",
"baseline_support_escape_U1_N11",
"baseline_support_escape_U1_N14",
"baseline_support_escape_U1_N7",
"baseline_support_escape_U1_V1",
"baseline_support_escape_U1_V11",
"baseline_support_escape_U1_V18",
"baseline_support_escape_U3_A9",
"baseline_support_escape_U3_B1",
"baseline_support_escape_U3_B3",
"baseline_support_escape_U3_B9",
"baseline_support_escape_U3_D1",
"baseline_support_escape_U3_D8",
"baseline_support_escape_U3_E1",
"baseline_support_escape_U3_E2",
"baseline_support_escape_U3_E8",
"baseline_support_escape_U3_F9",
"baseline_support_escape_U3_G1",
"baseline_support_escape_U3_G8",
"baseline_support_escape_U3_G9",
"baseline_support_escape_U3_J2",
"baseline_support_escape_U3_J8",
"baseline_support_escape_U3_M1",
"baseline_support_escape_U3_M9",
"baseline_support_escape_U3_P1",
"baseline_support_escape_U3_P9",
"baseline_support_escape_U3_T1",
"baseline_support_escape_U3_T9",
"baseline_support_via_U1_A1",
"baseline_support_via_U1_A18",
"baseline_support_via_U1_A5",
"baseline_support_via_U1_A7",
"baseline_support_via_U1_A9",
"baseline_support_via_U1_B6",
"baseline_support_via_U1_B7",
"baseline_support_via_U1_B8",
"baseline_support_via_U1_B9",
"baseline_support_via_U1_C7",
"baseline_support_via_U1_C8",
"baseline_support_via_U1_C9",
"baseline_support_via_U1_D8",
"baseline_support_via_U1_E8",
"baseline_support_via_U1_F8",
"baseline_support_via_U1_G11",
"baseline_support_via_U1_G12",
"baseline_support_via_U1_G8",
"baseline_support_via_U1_G9",
"baseline_support_via_U1_H10",
"baseline_support_via_U1_H6",
"baseline_support_via_U1_H8",
"baseline_support_via_U1_H9",
"baseline_support_via_U1_J10",
"baseline_support_via_U1_J11",
"baseline_support_via_U1_J6",
"baseline_support_via_U1_J8",
"baseline_support_via_U1_J9",
"baseline_support_via_U1_K11",
"baseline_support_via_U1_K7",
"baseline_support_via_U1_K9",
"baseline_support_via_U1_L10",
"baseline_support_via_U1_L12",
"baseline_support_via_U1_L13",
"baseline_support_via_U1_M10",
"baseline_support_via_U1_M12",
"baseline_support_via_U1_M14",
"baseline_support_via_U1_M6",
"baseline_support_via_U1_M7",
"baseline_support_via_U1_M8",
"baseline_support_via_U1_M9",
"baseline_support_via_U1_N10",
"baseline_support_via_U1_N11",
"baseline_support_via_U1_N14",
"baseline_support_via_U1_N7",
"baseline_support_via_U1_V1",
"baseline_support_via_U1_V11",
"baseline_support_via_U1_V18",
"baseline_support_via_U3_A9",
"baseline_support_via_U3_B1",
"baseline_support_via_U3_B3",
"baseline_support_via_U3_B9",
"baseline_support_via_U3_D1",
"baseline_support_via_U3_D8",
"baseline_support_via_U3_E1",
"baseline_support_via_U3_E2",
"baseline_support_via_U3_G1",
"baseline_support_via_U3_G8",
"baseline_support_via_U3_G9",
"baseline_support_via_U3_J2",
"baseline_support_via_U3_J8",
"baseline_support_via_U3_M1",
"baseline_support_via_U3_M9",
"baseline_support_via_U3_P1",
"baseline_support_via_U3_P9",
"baseline_support_via_U3_T1",
"baseline_support_via_U3_T9",
"clock_replan_clock_cap_ground",
"clock_replan_clock_cap_ground_via",
"clock_replan_clock_ground",
"clock_replan_clock_ground_via",
"clock_replan_old_clock_input_ground_north",
"closure_0d2751e3_C_ETH_A0_pin2_tap0",
"closure_0d2751e3_C_ETH_A0_pin2_tap0_via_0",
"closure_0d2751e3_C_ETH_A1_pin2_tap0",
"closure_0d2751e3_C_ETH_A1_pin2_tap0_via_0",
"closure_0d2751e3_C_ETH_A2_pin2_existing",
"closure_0d2751e3_C_ETH_IO0_pin2_tap0",
"closure_0d2751e3_C_ETH_IO0_pin2_tap0_via_0",
"closure_0d2751e3_C_ETH_IO1_pin2_existing",
"closure_0d2751e3_ESD_short_GND",
"closure_0d2751e3_ESD_short_GND_via_0",
"closure_0d2751e3_R_ETH_BIAS_pin2_existing",
"closure_0d2751e3_R_ETH_STRAP3_pin2_existing",
"closure_0d2751e3_U_ETH_ESD_3_U_ETH_ESD_8",
"closure_0d2751e3_U_ETH_PHY_21_U_ETH_PHY_25",
"closure_0d2751e3_U_ETH_PHY_9_U_ETH_PHY_25",
"closure_35a9e84a_U_LCD_BUF2_17_tap0",
"closure_35a9e84a_U_LCD_BUF2_17_tap0_via_0",
"closure_48c4415c_C_ETH_CHASSIS_pin2_tap0",
"closure_48c4415c_C_ETH_CHASSIS_pin2_tap0_via_0",
"closure_48c4415c_C_ETH_CT_RX_100N_pin2_existing",
"closure_48c4415c_C_ETH_CT_RX_1U_pin2_tap0",
"closure_48c4415c_C_ETH_CT_RX_1U_pin2_tap0_via_0",
"closure_48c4415c_C_ETH_CT_TX_100N_pin2_existing",
"closure_48c4415c_C_ETH_CT_TX_1U_pin2_existing",
"closure_48c4415c_C_ETH_ISO0_pin2_existing",
"closure_48c4415c_C_ETH_ISO1_pin2_existing",
"closure_48c4415c_R_ETH_STRAP2_pin2_existing",
"closure_51daa79a_jack_green_GND_PTH_to_plane",
"closure_5746f2c4_J_ETH_11_existing",
"closure_5746f2c4_R_ETH_STRAP4_pin2_tap0",
"closure_5746f2c4_R_ETH_STRAP4_pin2_tap0_via_0",
"closure_66d3108f_U_LCD_BUF2_13_static_ground",
"closure_66d3108f_U_LCD_BUF2_15_static_ground",
"closure_adeb6f65_C_ETH_A3_pin2_tap0",
"closure_adeb6f65_C_ETH_A3_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_CHASSIS_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_CT_RX_1U_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_IO2_pin2_tap0",
"closure_adeb6f65_C_ETH_IO2_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_IO3_pin2_tap0",
"closure_adeb6f65_C_ETH_IO3_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_ISO_OE_pin2_existing",
"closure_adeb6f65_C_ETH_LDO_IN_pin2_tap0",
"closure_adeb6f65_C_ETH_LDO_IN_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_OSC_pin2_existing",
"closure_adeb6f65_C_ETH_RAMP_CT_pin2_tap0",
"closure_adeb6f65_C_ETH_RAMP_CT_pin2_tap0_via_0",
"closure_adeb6f65_C_ETH_RESET_pin2_tap0",
"closure_adeb6f65_C_ETH_RESET_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_BL_IN_pin2_existing",
"closure_adeb6f65_C_LCD_BL_OUT_pin2_tap0",
"closure_adeb6f65_C_LCD_BL_OUT_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_BUF0_pin2_tap0",
"closure_adeb6f65_C_LCD_BUF0_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_BUF1_pin2_tap0",
"closure_adeb6f65_C_LCD_BUF1_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_BUF2_pin2_tap0",
"closure_adeb6f65_C_LCD_BUF2_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_LDO_IN_pin2_tap0",
"closure_adeb6f65_C_LCD_LDO_IN_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_LDO_OUT_pin2_tap0",
"closure_adeb6f65_C_LCD_LDO_OUT_pin2_tap0_via_0",
"closure_adeb6f65_C_LCD_OE_pin2_tap0",
"closure_adeb6f65_C_LCD_OE_pin2_tap0_via_0",
"closure_adeb6f65_C_PANEL_100N_pin2_tap0",
"closure_adeb6f65_C_PANEL_100N_pin2_tap0_via_0",
"closure_adeb6f65_C_PANEL_1U_pin2_existing",
"closure_adeb6f65_J_LCD_13_tap0",
"closure_adeb6f65_J_LCD_13_tap0_via_0",
"closure_adeb6f65_J_LCD_14_tap0",
"closure_adeb6f65_J_LCD_14_tap0_via_0",
"closure_adeb6f65_J_LCD_21_tap0",
"closure_adeb6f65_J_LCD_21_tap0_via_0",
"closure_adeb6f65_J_LCD_22_existing",
"closure_adeb6f65_J_LCD_23_existing",
"closure_adeb6f65_J_LCD_29_tap0",
"closure_adeb6f65_J_LCD_29_tap0_via_0",
"closure_adeb6f65_J_LCD_32_tap0",
"closure_adeb6f65_J_LCD_32_tap0_via_0",
"closure_adeb6f65_J_LCD_33_existing",
"closure_adeb6f65_J_LCD_36_tap0",
"closure_adeb6f65_J_LCD_36_tap0_via_0",
"closure_adeb6f65_J_LCD_3_tap0",
"closure_adeb6f65_J_LCD_3_tap0_via_0",
"closure_adeb6f65_J_LCD_5_tap0",
"closure_adeb6f65_J_LCD_5_tap0_via_0",
"closure_adeb6f65_J_LCD_6_existing",
"closure_adeb6f65_J_LCD_7_existing",
"closure_adeb6f65_R_ETH_CHASSIS_pin2_tap0",
"closure_adeb6f65_R_ETH_CHASSIS_pin2_tap0_via_0",
"closure_adeb6f65_R_ETH_STRAP0_pin2_existing",
"closure_adeb6f65_R_ETH_STRAP1_pin2_existing",
"closure_adeb6f65_R_LCD_ISET_pin2_tap0",
"closure_adeb6f65_R_LCD_ISET_pin2_tap0_via_0",
"closure_adeb6f65_U_LCD_BL_2_tap0",
"closure_adeb6f65_U_LCD_BL_2_tap0_via_0",
"closure_ff49e202_C_ETH_LDO_OUT_pin2_tap0",
"closure_ff49e202_C_ETH_LDO_OUT_pin2_tap0_via_0",
"closure_ff49e202_R_ETH_STRAP5_pin2_tap0",
"closure_ff49e202_R_ETH_STRAP5_pin2_tap0_via_0",
"closure_ff49e202_R_LCD_BL_PD_pin2_tap0",
"closure_ff49e202_R_LCD_BL_PD_pin2_tap0_via_0",
"closure_ff49e202_R_LCD_CTRL_PD_pin2_tap0",
"closure_ff49e202_R_LCD_CTRL_PD_pin2_tap0_via_0",
"closure_ff49e202_R_LCD_ENABLE_PD_pin2_existing",
"closure_ff49e202_R_LCD_STBY_PD_pin2_tap0",
"closure_ff49e202_R_LCD_STBY_PD_pin2_tap0_via_0",
"closure_ff49e202_U_ETH_ISO0_10_tap0",
"closure_ff49e202_U_ETH_ISO0_10_tap0_via_0",
"closure_ff49e202_U_ETH_ISO1_10_tap0",
"closure_ff49e202_U_ETH_ISO1_10_tap0_via_0",
"closure_ff49e202_U_ETH_ISO1_11_tap0",
"closure_ff49e202_U_ETH_ISO1_11_tap0_via_0",
"closure_ff49e202_U_ETH_ISO1_12_existing",
"closure_ff49e202_U_ETH_ISO1_13_existing",
"closure_ff49e202_U_ETH_ISO1_14_existing",
"closure_ff49e202_U_ETH_ISO1_15_existing",
"closure_ff49e202_U_ETH_ISO1_16_tap0",
"closure_ff49e202_U_ETH_ISO1_16_tap0_via_0",
"closure_ff49e202_U_ETH_ISO1_4_tap0",
"closure_ff49e202_U_ETH_ISO1_4_tap0_via_0",
"closure_ff49e202_U_ETH_ISO1_5_existing",
"closure_ff49e202_U_ETH_ISO1_6_existing",
"closure_ff49e202_U_ETH_ISO1_7_existing",
"closure_ff49e202_U_ETH_ISO1_8_existing",
"closure_ff49e202_U_ETH_ISO1_9_existing",
"closure_ff49e202_U_ETH_ISO_OE_3_existing",
"closure_ff49e202_U_ETH_LDO_2_tap0",
"closure_ff49e202_U_ETH_LDO_2_tap0_via_0",
"closure_ff49e202_U_ETH_RAMP_2_tap0",
"closure_ff49e202_U_ETH_RAMP_2_tap0_via_0",
"closure_ff49e202_U_ETH_RESET_2_tap0",
"closure_ff49e202_U_ETH_RESET_2_tap0_via_0",
"closure_ff49e202_U_LCD_BUF0_10_tap0",
"closure_ff49e202_U_LCD_BUF0_10_tap0_via_0",
"closure_ff49e202_U_LCD_BUF1_10_tap0",
"closure_ff49e202_U_LCD_BUF1_10_tap0_via_0",
"closure_ff49e202_U_LCD_BUF2_10_tap0",
"closure_ff49e202_U_LCD_BUF2_10_tap0_via_0",
"closure_ff49e202_U_LCD_BUF2_11_tap0",
"closure_ff49e202_U_LCD_BUF2_11_tap0_via_0",
"closure_ff49e202_U_LCD_LDO_2_tap0",
"closure_ff49e202_U_LCD_LDO_2_tap0_via_0",
"closure_ff49e202_U_LCD_OE_3_tap0",
"closure_ff49e202_U_LCD_OE_3_tap0_via_0",
"closure_ff49e202_Y_ETH_2_tap0",
"closure_ff49e202_Y_ETH_2_tap0_via_0",
"core_replan_DDR18_GND_via",
"core_replan_R6_USB0_return_via",
"dbg_pcb_smtpad_4",
"dbg_pcb_trace_4",
"ddr_return_stitch_inner6_island2",
"ground_reference_stitch_CRS_far_transfer",
"ground_reference_stitch_D0_damped_transfer",
"ground_reference_stitch_EN_baseline_transfer",
"ground_reference_stitch_EN_extension_transfer",
"hdmi_boot15_native_short_ground",
"hdmi_power_trace_1004_ground_R177_original_top",
"hdmi_power_trace_1018_C178_selected_EP_ground",
"hdmi_power_trace_1019_C179_to_clock_ground",
"hdmi_power_trace_1021_C182_ground_reconciled",
"hdmi_power_trace_1028_utility_75R_ground_local",
"hdmi_power_trace_1030_J8_left_ground_handover",
"hdmi_power_trace_final_015_ground_U_HDMI_2",
"hdmi_power_trace_final_021_ground_R_HDMI_5V_BOTTOM_pin2",
"hdmi_power_trace_final_024_LDO_Cin_ground_top",
"hdmi_power_trace_final_025_ground_C_HDMI_1V2_IN_pin2",
"hdmi_power_trace_final_030_ground_U_HDMI_3",
"hdmi_power_trace_final_031_ground_U_HDMI_4",
"hdmi_power_trace_final_032_ground_U_HDMI_5",
"hdmi_power_trace_final_033_ground_C_HDMI_REF_C144_pin2",
"hdmi_power_trace_final_034_ground_C_HDMI_REF_C145_pin2",
"hdmi_power_trace_final_035_ground_C_HDMI_REF_C146_pin2",
"hdmi_power_trace_final_036_ground_C_HDMI_REF_C147_pin2",
"hdmi_power_trace_final_037_ground_C_HDMI_REF_C148_pin2",
"hdmi_power_trace_final_038_ground_C_HDMI_REF_C149_pin2",
"hdmi_power_trace_final_039_ground_C_HDMI_REF_C150_pin2",
"hdmi_power_trace_final_040_ground_C_HDMI_REF_C151_pin2",
"hdmi_power_trace_final_041_ground_C_HDMI_REF_C176_pin1",
"hdmi_power_trace_final_042_ground_C_HDMI_REF_C177_pin2",
"hdmi_power_trace_final_045_ground_C_HDMI_REF_C180_pin2",
"hdmi_power_trace_final_046_ground_C_HDMI_REF_C181_pin2",
"hdmi_power_trace_final_048_ground_C_HDMI_REF_C184_pin2",
"hdmi_power_trace_final_049_ground_C_HDMI_REF_C185_pin2",
"hdmi_power_trace_final_050_ground_C_HDMI_REF_C186_pin2",
"hdmi_power_trace_final_051_ground_C_HDMI_REF_C187_pin2",
"hdmi_power_trace_final_052_ground_C_HDMI_REF_C188_pin2",
"hdmi_power_trace_final_053_ground_C_HDMI_REF_C193_pin2",
"hdmi_power_trace_final_054_ground_R_HDMI_REF_R176_pin2",
"hdmi_power_trace_final_055_ground_R_HDMI_REF_R181_pin2",
"hdmi_power_trace_final_056_ground_R_HDMI_REF_R188_pin1",
"hdmi_power_trace_final_057_ground_U_HDMI_1V2_2",
"hdmi_power_trace_final_058_ground_U_HDMI_1V2_2",
"hdmi_power_trace_final_059_ground_C_HDMI_1V2_EN_pin2",
"hdmi_power_trace_final_060_ground_C_HDMI_RESET_DECOUPLE_pin2",
"hdmi_power_trace_final_062_ground_J_HDMI_2",
"hdmi_power_trace_final_063_ground_J_HDMI_5",
"hdmi_power_trace_final_065_ground_J_HDMI_11",
"hdmi_power_trace_final_066_ground_J_HDMI_20",
"hdmi_power_trace_final_067_ground_J_HDMI_21",
"hdmi_power_trace_final_068_ground_J_HDMI_22",
"hdmi_power_trace_final_069_ground_J_HDMI_23",
"hdmi_power_trace_final_070_ground_U_HDMI_5V_BOOST_6",
"hdmi_power_trace_final_071_ground_U_HDMI_5V_BOOST_6",
"hdmi_power_trace_final_072_ground_C_HDMI_5V_IN_pin2",
"hdmi_power_trace_final_073_ground_C_HDMI_5V_IN_pin2",
"hdmi_power_trace_final_075_ground_U_HDMI_6",
"hdmi_power_trace_final_076_ground_U_HDMI_7",
"hdmi_power_trace_final_077_ground_U_HDMI_RESET_3",
"hdmi_power_trace_final_078_ground_C_HDMI_ESD_SUPPLY_pin2",
"hdmi_power_trace_final_079_ground_C_HDMI_ESD_OUT_pin2",
"hdmi_power_trace_final_080_ground_J_HDMI_17",
"hdmi_power_trace_final_081_ground_C_HDMI_5V_OUT1_pin2",
"hdmi_power_trace_final_082_ground_C_HDMI_5V_OUT1_pin2",
"hdmi_power_trace_final_083_ground_C_HDMI_5V_OUT2_pin2",
"hdmi_power_trace_final_084_ground_C_HDMI_5V_OUT2_pin2",
"hdmi_power_trace_final_134_ground_C_HDMI_REF_C183_pin2",
"hdmi_power_trace_final_136_ground_U_HDMI_ESD_6",
"hdmi_power_via_1010",
"hdmi_power_via_1017",
"hdmi_power_via_1020",
"hdmi_power_via_1029",
"hdmi_power_via_1031",
"hdmi_power_via_1032",
"hdmi_power_via_1033",
"hdmi_power_via_final_003",
"hdmi_power_via_final_006",
"hdmi_power_via_final_008",
"hdmi_power_via_final_011",
"hdmi_power_via_final_012",
"hdmi_power_via_final_013",
"hdmi_power_via_final_014",
"hdmi_power_via_final_015",
"hdmi_power_via_final_016",
"hdmi_power_via_final_017",
"hdmi_power_via_final_018",
"hdmi_power_via_final_019",
"hdmi_power_via_final_020",
"hdmi_power_via_final_021",
"hdmi_power_via_final_022",
"hdmi_power_via_final_023",
"hdmi_power_via_final_024",
"hdmi_power_via_final_025",
"hdmi_power_via_final_026",
"hdmi_power_via_final_027",
"hdmi_power_via_final_030",
"hdmi_power_via_final_031",
"hdmi_power_via_final_033",
"hdmi_power_via_final_034",
"hdmi_power_via_final_035",
"hdmi_power_via_final_036",
"hdmi_power_via_final_037",
"hdmi_power_via_final_038",
"hdmi_power_via_final_039",
"hdmi_power_via_final_040",
"hdmi_power_via_final_041",
"hdmi_power_via_final_042",
"hdmi_power_via_final_043",
"hdmi_power_via_final_044",
"hdmi_power_via_final_045",
"hdmi_power_via_final_047",
"hdmi_power_via_final_048",
"hdmi_power_via_final_050",
"hdmi_power_via_final_051",
"hdmi_power_via_final_052",
"hdmi_power_via_final_053",
"hdmi_power_via_final_054",
"hdmi_power_via_final_055",
"hdmi_power_via_final_056",
"hdmi_power_via_final_057",
"hdmi_power_via_final_058",
"hdmi_power_via_final_061",
"hdmi_power_via_final_062",
"hdmi_power_via_final_063",
"hdmi_power_via_final_064",
"hdmi_power_via_final_065",
"hdmi_power_via_final_066",
"hdmi_power_via_final_067",
"hdmi_power_via_final_068",
"hdmi_power_via_final_069",
"hdmi_power_via_final_070",
"hdmi_power_via_final_132",
"hdmi_power_via_final_134",
"interface_PHY_EP_thermal_0",
"interface_PHY_EP_thermal_3",
"interface_plan_GND_EXT_inner1_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0",
"interface_plan_GND_EXT_inner2_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0",
"interface_plan_GND_EXT_inner6_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0",
"pcb_plated_hole_0",
"pcb_plated_hole_1",
"pcb_plated_hole_12",
"pcb_plated_hole_14",
"pcb_plated_hole_2",
"pcb_plated_hole_3",
"pcb_plated_hole_hdmi_pcb_plated_hole_0",
"pcb_plated_hole_hdmi_pcb_plated_hole_1",
"pcb_plated_hole_hdmi_pcb_plated_hole_2",
"pcb_plated_hole_hdmi_pcb_plated_hole_3",
"pcb_smtpad_0",
"pcb_smtpad_1009",
"pcb_smtpad_101",
"pcb_smtpad_1011",
"pcb_smtpad_1013",
"pcb_smtpad_1015",
"pcb_smtpad_1017",
"pcb_smtpad_1019",
"pcb_smtpad_1021",
"pcb_smtpad_1027",
"pcb_smtpad_1033",
"pcb_smtpad_1035",
"pcb_smtpad_1043",
"pcb_smtpad_1045",
"pcb_smtpad_1047",
"pcb_smtpad_1049",
"pcb_smtpad_1051",
"pcb_smtpad_1053",
"pcb_smtpad_1055",
"pcb_smtpad_1057",
"pcb_smtpad_1059",
"pcb_smtpad_1065",
"pcb_smtpad_1067",
"pcb_smtpad_1069",
"pcb_smtpad_1071",
"pcb_smtpad_1074",
"pcb_smtpad_1079",
"pcb_smtpad_108",
"pcb_smtpad_1083",
"pcb_smtpad_1085",
"pcb_smtpad_109",
"pcb_smtpad_110",
"pcb_smtpad_115",
"pcb_smtpad_116",
"pcb_smtpad_117",
"pcb_smtpad_119",
"pcb_smtpad_120",
"pcb_smtpad_126",
"pcb_smtpad_1269",
"pcb_smtpad_127",
"pcb_smtpad_1275",
"pcb_smtpad_128",
"pcb_smtpad_1285",
"pcb_smtpad_129",
"pcb_smtpad_1297",
"pcb_smtpad_130",
"pcb_smtpad_1301",
"pcb_smtpad_1302",
"pcb_smtpad_1303",
"pcb_smtpad_1304",
"pcb_smtpad_1305",
"pcb_smtpad_1306",
"pcb_smtpad_1307",
"pcb_smtpad_1308",
"pcb_smtpad_1309",
"pcb_smtpad_131",
"pcb_smtpad_1310",
"pcb_smtpad_1311",
"pcb_smtpad_1312",
"pcb_smtpad_1313",
"pcb_smtpad_1319",
"pcb_smtpad_132",
"pcb_smtpad_1322",
"pcb_smtpad_1328",
"pcb_smtpad_133",
"pcb_smtpad_134",
"pcb_smtpad_137",
"pcb_smtpad_144",
"pcb_smtpad_145",
"pcb_smtpad_146",
"pcb_smtpad_150",
"pcb_smtpad_151",
"pcb_smtpad_152",
"pcb_smtpad_153",
"pcb_smtpad_155",
"pcb_smtpad_169",
"pcb_smtpad_17",
"pcb_smtpad_170",
"pcb_smtpad_171",
"pcb_smtpad_172",
"pcb_smtpad_173",
"pcb_smtpad_174",
"pcb_smtpad_186",
"pcb_smtpad_188",
"pcb_smtpad_189",
"pcb_smtpad_190",
"pcb_smtpad_192",
"pcb_smtpad_197",
"pcb_smtpad_204",
"pcb_smtpad_205",
"pcb_smtpad_208",
"pcb_smtpad_209",
"pcb_smtpad_226",
"pcb_smtpad_245",
"pcb_smtpad_246",
"pcb_smtpad_306",
"pcb_smtpad_323",
"pcb_smtpad_325",
"pcb_smtpad_327",
"pcb_smtpad_328",
"pcb_smtpad_330",
"pcb_smtpad_335",
"pcb_smtpad_337",
"pcb_smtpad_339",
"pcb_smtpad_344",
"pcb_smtpad_348",
"pcb_smtpad_357",
"pcb_smtpad_391",
"pcb_smtpad_392",
"pcb_smtpad_394",
"pcb_smtpad_396",
"pcb_smtpad_404",
"pcb_smtpad_405",
"pcb_smtpad_409",
"pcb_smtpad_410",
"pcb_smtpad_415",
"pcb_smtpad_417",
"pcb_smtpad_419",
"pcb_smtpad_428",
"pcb_smtpad_439",
"pcb_smtpad_440",
"pcb_smtpad_441",
"pcb_smtpad_442",
"pcb_smtpad_443",
"pcb_smtpad_444",
"pcb_smtpad_446",
"pcb_smtpad_449",
"pcb_smtpad_450",
"pcb_smtpad_451",
"pcb_smtpad_452",
"pcb_smtpad_468",
"pcb_smtpad_478",
"pcb_smtpad_480",
"pcb_smtpad_482",
"pcb_smtpad_484",
"pcb_smtpad_486",
"pcb_smtpad_488",
"pcb_smtpad_490",
"pcb_smtpad_492",
"pcb_smtpad_494",
"pcb_smtpad_496",
"pcb_smtpad_498",
"pcb_smtpad_500",
"pcb_smtpad_502",
"pcb_smtpad_504",
"pcb_smtpad_506",
"pcb_smtpad_508",
"pcb_smtpad_510",
"pcb_smtpad_512",
"pcb_smtpad_527",
"pcb_smtpad_528",
"pcb_smtpad_532",
"pcb_smtpad_534",
"pcb_smtpad_536",
"pcb_smtpad_538",
"pcb_smtpad_540",
"pcb_smtpad_542",
"pcb_smtpad_544",
"pcb_smtpad_546",
"pcb_smtpad_548",
"pcb_smtpad_550",
"pcb_smtpad_552",
"pcb_smtpad_554",
"pcb_smtpad_556",
"pcb_smtpad_558",
"pcb_smtpad_560",
"pcb_smtpad_562",
"pcb_smtpad_564",
"pcb_smtpad_566",
"pcb_smtpad_568",
"pcb_smtpad_570",
"pcb_smtpad_572",
"pcb_smtpad_574",
"pcb_smtpad_576",
"pcb_smtpad_578",
"pcb_smtpad_580",
"pcb_smtpad_582",
"pcb_smtpad_584",
"pcb_smtpad_586",
"pcb_smtpad_588",
"pcb_smtpad_590",
"pcb_smtpad_592",
"pcb_smtpad_594",
"pcb_smtpad_596",
"pcb_smtpad_598",
"pcb_smtpad_600",
"pcb_smtpad_602",
"pcb_smtpad_604",
"pcb_smtpad_606",
"pcb_smtpad_608",
"pcb_smtpad_610",
"pcb_smtpad_612",
"pcb_smtpad_614",
"pcb_smtpad_616",
"pcb_smtpad_618",
"pcb_smtpad_620",
"pcb_smtpad_622",
"pcb_smtpad_624",
"pcb_smtpad_626",
"pcb_smtpad_628",
"pcb_smtpad_630",
"pcb_smtpad_632",
"pcb_smtpad_634",
"pcb_smtpad_636",
"pcb_smtpad_638",
"pcb_smtpad_640",
"pcb_smtpad_642",
"pcb_smtpad_644",
"pcb_smtpad_646",
"pcb_smtpad_648",
"pcb_smtpad_650",
"pcb_smtpad_652",
"pcb_smtpad_654",
"pcb_smtpad_656",
"pcb_smtpad_658",
"pcb_smtpad_662",
"pcb_smtpad_666",
"pcb_smtpad_668",
"pcb_smtpad_670",
"pcb_smtpad_672",
"pcb_smtpad_676",
"pcb_smtpad_678",
"pcb_smtpad_680",
"pcb_smtpad_682",
"pcb_smtpad_684",
"pcb_smtpad_686",
"pcb_smtpad_688",
"pcb_smtpad_690",
"pcb_smtpad_692",
"pcb_smtpad_694",
"pcb_smtpad_696",
"pcb_smtpad_698",
"pcb_smtpad_700",
"pcb_smtpad_702",
"pcb_smtpad_704",
"pcb_smtpad_706",
"pcb_smtpad_708",
"pcb_smtpad_716",
"pcb_smtpad_72",
"pcb_smtpad_720",
"pcb_smtpad_722",
"pcb_smtpad_724",
"pcb_smtpad_726",
"pcb_smtpad_728",
"pcb_smtpad_730",
"pcb_smtpad_732",
"pcb_smtpad_734",
"pcb_smtpad_736",
"pcb_smtpad_740",
"pcb_smtpad_742",
"pcb_smtpad_746",
"pcb_smtpad_752",
"pcb_smtpad_756",
"pcb_smtpad_757",
"pcb_smtpad_758",
"pcb_smtpad_759",
"pcb_smtpad_760",
"pcb_smtpad_774",
"pcb_smtpad_776",
"pcb_smtpad_777",
"pcb_smtpad_784",
"pcb_smtpad_785",
"pcb_smtpad_792",
"pcb_smtpad_794",
"pcb_smtpad_805",
"pcb_smtpad_806",
"pcb_smtpad_809",
"pcb_smtpad_816",
"pcb_smtpad_817",
"pcb_smtpad_820",
"pcb_smtpad_832",
"pcb_smtpad_833",
"pcb_smtpad_841",
"pcb_smtpad_843",
"pcb_smtpad_847",
"pcb_smtpad_849",
"pcb_smtpad_851",
"pcb_smtpad_853",
"pcb_smtpad_855",
"pcb_smtpad_857",
"pcb_smtpad_860",
"pcb_smtpad_864",
"pcb_smtpad_870",
"pcb_smtpad_872",
"pcb_smtpad_876",
"pcb_smtpad_882",
"pcb_smtpad_883",
"pcb_smtpad_884",
"pcb_smtpad_887",
"pcb_smtpad_888",
"pcb_smtpad_889",
"pcb_smtpad_890",
"pcb_smtpad_891",
"pcb_smtpad_894",
"pcb_smtpad_898",
"pcb_smtpad_900",
"pcb_smtpad_901",
"pcb_smtpad_906",
"pcb_smtpad_908",
"pcb_smtpad_91",
"pcb_smtpad_910",
"pcb_smtpad_912",
"pcb_smtpad_914",
"pcb_smtpad_916",
"pcb_smtpad_918",
"pcb_smtpad_920",
"pcb_smtpad_922",
"pcb_smtpad_924",
"pcb_smtpad_926",
"pcb_smtpad_928",
"pcb_smtpad_930",
"pcb_smtpad_932",
"pcb_smtpad_934",
"pcb_smtpad_936",
"pcb_smtpad_938",
"pcb_smtpad_940",
"pcb_smtpad_942",
"pcb_smtpad_944",
"pcb_smtpad_946",
"pcb_smtpad_948",
"pcb_smtpad_953",
"pcb_smtpad_955",
"pcb_smtpad_97",
"pcb_smtpad_973",
"pcb_smtpad_98",
"pcb_smtpad_985",
"pcb_smtpad_989",
"pcb_smtpad_hdmi_pcb_smtpad_1",
"pcb_smtpad_hdmi_pcb_smtpad_100",
"pcb_smtpad_hdmi_pcb_smtpad_102",
"pcb_smtpad_hdmi_pcb_smtpad_104",
"pcb_smtpad_hdmi_pcb_smtpad_106",
"pcb_smtpad_hdmi_pcb_smtpad_108",
"pcb_smtpad_hdmi_pcb_smtpad_132",
"pcb_smtpad_hdmi_pcb_smtpad_134",
"pcb_smtpad_hdmi_pcb_smtpad_136",
"pcb_smtpad_hdmi_pcb_smtpad_139",
"pcb_smtpad_hdmi_pcb_smtpad_142",
"pcb_smtpad_hdmi_pcb_smtpad_148",
"pcb_smtpad_hdmi_pcb_smtpad_156",
"pcb_smtpad_hdmi_pcb_smtpad_158",
"pcb_smtpad_hdmi_pcb_smtpad_160",
"pcb_smtpad_hdmi_pcb_smtpad_166",
"pcb_smtpad_hdmi_pcb_smtpad_178",
"pcb_smtpad_hdmi_pcb_smtpad_180",
"pcb_smtpad_hdmi_pcb_smtpad_182",
"pcb_smtpad_hdmi_pcb_smtpad_184",
"pcb_smtpad_hdmi_pcb_smtpad_187",
"pcb_smtpad_hdmi_pcb_smtpad_190",
"pcb_smtpad_hdmi_pcb_smtpad_193",
"pcb_smtpad_hdmi_pcb_smtpad_199",
"pcb_smtpad_hdmi_pcb_smtpad_2",
"pcb_smtpad_hdmi_pcb_smtpad_263",
"pcb_smtpad_hdmi_pcb_smtpad_271",
"pcb_smtpad_hdmi_pcb_smtpad_273",
"pcb_smtpad_hdmi_pcb_smtpad_275",
"pcb_smtpad_hdmi_pcb_smtpad_277",
"pcb_smtpad_hdmi_pcb_smtpad_3",
"pcb_smtpad_hdmi_pcb_smtpad_4",
"pcb_smtpad_hdmi_pcb_smtpad_5",
"pcb_smtpad_hdmi_pcb_smtpad_6",
"pcb_smtpad_hdmi_pcb_smtpad_64",
"pcb_smtpad_hdmi_pcb_smtpad_66",
"pcb_smtpad_hdmi_pcb_smtpad_68",
"pcb_smtpad_hdmi_pcb_smtpad_70",
"pcb_smtpad_hdmi_pcb_smtpad_72",
"pcb_smtpad_hdmi_pcb_smtpad_74",
"pcb_smtpad_hdmi_pcb_smtpad_76",
"pcb_smtpad_hdmi_pcb_smtpad_78",
"pcb_smtpad_hdmi_pcb_smtpad_80",
"pcb_smtpad_hdmi_pcb_smtpad_81",
"pcb_smtpad_hdmi_pcb_smtpad_84",
"pcb_smtpad_hdmi_pcb_smtpad_86",
"pcb_smtpad_hdmi_pcb_smtpad_88",
"pcb_smtpad_hdmi_pcb_smtpad_90",
"pcb_smtpad_hdmi_pcb_smtpad_92",
"pcb_smtpad_hdmi_pcb_smtpad_94",
"pcb_smtpad_hdmi_pcb_smtpad_96",
"pcb_smtpad_hdmi_pcb_smtpad_98",
"pg7_pcb_smtpad_12",
"pg7_pcb_smtpad_16",
"pg7_pcb_smtpad_2",
"pg7_route_divider_ground",
"pg7_route_ground_feed",
"pg7_route_ic_ground",
"proposed_joint_D0_D1_inner4_GND_reference",
"reference_repair_GND_ETH_MDC_0",
"reference_repair_GND_ETH_MDC_1",
"reference_repair_GND_SYSBOOT15_0",
"reference_repair_GND_SYSBOOT15_1",
"reference_repair_GND_SYSBOOT15_2",
"short_tx_return_C_RMII_RETURN_A_GND",
"short_tx_return_C_RMII_RETURN_A_GND_via",
"short_tx_return_C_RMII_RETURN_B_GND",
"short_tx_return_C_RMII_RETURN_B_GND_via",
"short_tx_return_C_RMII_RETURN_C_GND",
"short_tx_return_C_RMII_RETURN_C_GND_via",
"short_tx_return_C_RMII_RETURN_D_GND",
"short_tx_return_C_RMII_RETURN_D_GND_via",
"short_tx_return_pcb_smtpad_1346",
"short_tx_return_pcb_smtpad_1348",
"short_tx_return_pcb_smtpad_1350",
"short_tx_return_pcb_smtpad_1352"
],
"required_terminals": [
"dbg_pcb_port_4",
"pcb_port_0",
"pcb_port_1009",
"pcb_port_101",
"pcb_port_1011",
"pcb_port_1013",
"pcb_port_1015",
"pcb_port_1017",
"pcb_port_1019",
"pcb_port_1021",
"pcb_port_1027",
"pcb_port_1033",
"pcb_port_1035",
"pcb_port_1043",
"pcb_port_1045",
"pcb_port_1047",
"pcb_port_1049",
"pcb_port_1051",
"pcb_port_1053",
"pcb_port_1055",
"pcb_port_1057",
"pcb_port_1059",
"pcb_port_1068",
"pcb_port_1070",
"pcb_port_1079",
"pcb_port_108",
"pcb_port_1081",
"pcb_port_1083",
"pcb_port_1085",
"pcb_port_1088",
"pcb_port_109",
"pcb_port_1093",
"pcb_port_1097",
"pcb_port_1099",
"pcb_port_110",
"pcb_port_115",
"pcb_port_116",
"pcb_port_117",
"pcb_port_119",
"pcb_port_120",
"pcb_port_126",
"pcb_port_127",
"pcb_port_128",
"pcb_port_1281",
"pcb_port_1287",
"pcb_port_129",
"pcb_port_1297",
"pcb_port_130",
"pcb_port_1309",
"pcb_port_131",
"pcb_port_1313",
"pcb_port_1314",
"pcb_port_1315",
"pcb_port_1316",
"pcb_port_1317",
"pcb_port_1318",
"pcb_port_1319",
"pcb_port_132",
"pcb_port_1320",
"pcb_port_1321",
"pcb_port_1322",
"pcb_port_1323",
"pcb_port_1324",
"pcb_port_1325",
"pcb_port_133",
"pcb_port_1331",
"pcb_port_1334",
"pcb_port_134",
"pcb_port_1340",
"pcb_port_137",
"pcb_port_144",
"pcb_port_145",
"pcb_port_146",
"pcb_port_150",
"pcb_port_151",
"pcb_port_152",
"pcb_port_153",
"pcb_port_155",
"pcb_port_169",
"pcb_port_17",
"pcb_port_170",
"pcb_port_171",
"pcb_port_172",
"pcb_port_173",
"pcb_port_174",
"pcb_port_186",
"pcb_port_188",
"pcb_port_189",
"pcb_port_190",
"pcb_port_192",
"pcb_port_197",
"pcb_port_204",
"pcb_port_205",
"pcb_port_208",
"pcb_port_209",
"pcb_port_226",
"pcb_port_245",
"pcb_port_246",
"pcb_port_306",
"pcb_port_323",
"pcb_port_325",
"pcb_port_327",
"pcb_port_328",
"pcb_port_330",
"pcb_port_335",
"pcb_port_337",
"pcb_port_339",
"pcb_port_344",
"pcb_port_348",
"pcb_port_357",
"pcb_port_391",
"pcb_port_392",
"pcb_port_394",
"pcb_port_396",
"pcb_port_404",
"pcb_port_405",
"pcb_port_409",
"pcb_port_410",
"pcb_port_415",
"pcb_port_417",
"pcb_port_419",
"pcb_port_428",
"pcb_port_439",
"pcb_port_440",
"pcb_port_441",
"pcb_port_442",
"pcb_port_443",
"pcb_port_444",
"pcb_port_446",
"pcb_port_449",
"pcb_port_450",
"pcb_port_451",
"pcb_port_452",
"pcb_port_468",
"pcb_port_478",
"pcb_port_480",
"pcb_port_482",
"pcb_port_484",
"pcb_port_486",
"pcb_port_488",
"pcb_port_490",
"pcb_port_492",
"pcb_port_494",
"pcb_port_496",
"pcb_port_498",
"pcb_port_500",
"pcb_port_502",
"pcb_port_504",
"pcb_port_506",
"pcb_port_508",
"pcb_port_510",
"pcb_port_512",
"pcb_port_526",
"pcb_port_532",
"pcb_port_534",
"pcb_port_536",
"pcb_port_538",
"pcb_port_540",
"pcb_port_542",
"pcb_port_544",
"pcb_port_546",
"pcb_port_548",
"pcb_port_550",
"pcb_port_552",
"pcb_port_554",
"pcb_port_556",
"pcb_port_558",
"pcb_port_560",
"pcb_port_562",
"pcb_port_564",
"pcb_port_566",
"pcb_port_568",
"pcb_port_570",
"pcb_port_572",
"pcb_port_574",
"pcb_port_576",
"pcb_port_578",
"pcb_port_580",
"pcb_port_582",
"pcb_port_584",
"pcb_port_586",
"pcb_port_588",
"pcb_port_590",
"pcb_port_592",
"pcb_port_594",
"pcb_port_596",
"pcb_port_598",
"pcb_port_600",
"pcb_port_602",
"pcb_port_604",
"pcb_port_606",
"pcb_port_608",
"pcb_port_610",
"pcb_port_612",
"pcb_port_614",
"pcb_port_616",
"pcb_port_618",
"pcb_port_620",
"pcb_port_622",
"pcb_port_624",
"pcb_port_626",
"pcb_port_628",
"pcb_port_630",
"pcb_port_632",
"pcb_port_634",
"pcb_port_636",
"pcb_port_638",
"pcb_port_640",
"pcb_port_642",
"pcb_port_644",
"pcb_port_646",
"pcb_port_648",
"pcb_port_650",
"pcb_port_652",
"pcb_port_654",
"pcb_port_656",
"pcb_port_658",
"pcb_port_662",
"pcb_port_666",
"pcb_port_668",
"pcb_port_670",
"pcb_port_672",
"pcb_port_676",
"pcb_port_678",
"pcb_port_680",
"pcb_port_682",
"pcb_port_684",
"pcb_port_686",
"pcb_port_688",
"pcb_port_690",
"pcb_port_692",
"pcb_port_694",
"pcb_port_696",
"pcb_port_698",
"pcb_port_700",
"pcb_port_702",
"pcb_port_704",
"pcb_port_706",
"pcb_port_708",
"pcb_port_716",
"pcb_port_72",
"pcb_port_720",
"pcb_port_722",
"pcb_port_724",
"pcb_port_726",
"pcb_port_728",
"pcb_port_730",
"pcb_port_732",
"pcb_port_734",
"pcb_port_736",
"pcb_port_740",
"pcb_port_742",
"pcb_port_746",
"pcb_port_752",
"pcb_port_756",
"pcb_port_757",
"pcb_port_774",
"pcb_port_776",
"pcb_port_777",
"pcb_port_784",
"pcb_port_785",
"pcb_port_792",
"pcb_port_793",
"pcb_port_798",
"pcb_port_808",
"pcb_port_813",
"pcb_port_820",
"pcb_port_821",
"pcb_port_824",
"pcb_port_836",
"pcb_port_837",
"pcb_port_845",
"pcb_port_847",
"pcb_port_851",
"pcb_port_853",
"pcb_port_855",
"pcb_port_857",
"pcb_port_859",
"pcb_port_861",
"pcb_port_864",
"pcb_port_868",
"pcb_port_874",
"pcb_port_876",
"pcb_port_880",
"pcb_port_886",
"pcb_port_887",
"pcb_port_888",
"pcb_port_891",
"pcb_port_894",
"pcb_port_898",
"pcb_port_900",
"pcb_port_901",
"pcb_port_906",
"pcb_port_908",
"pcb_port_91",
"pcb_port_910",
"pcb_port_912",
"pcb_port_914",
"pcb_port_916",
"pcb_port_918",
"pcb_port_920",
"pcb_port_922",
"pcb_port_924",
"pcb_port_926",
"pcb_port_928",
"pcb_port_930",
"pcb_port_932",
"pcb_port_934",
"pcb_port_936",
"pcb_port_938",
"pcb_port_940",
"pcb_port_942",
"pcb_port_944",
"pcb_port_946",
"pcb_port_948",
"pcb_port_953",
"pcb_port_955",
"pcb_port_97",
"pcb_port_973",
"pcb_port_98",
"pcb_port_985",
"pcb_port_989",
"pcb_port_hdmi_pcb_port_1",
"pcb_port_hdmi_pcb_port_100",
"pcb_port_hdmi_pcb_port_102",
"pcb_port_hdmi_pcb_port_104",
"pcb_port_hdmi_pcb_port_106",
"pcb_port_hdmi_pcb_port_108",
"pcb_port_hdmi_pcb_port_132",
"pcb_port_hdmi_pcb_port_134",
"pcb_port_hdmi_pcb_port_136",
"pcb_port_hdmi_pcb_port_139",
"pcb_port_hdmi_pcb_port_142",
"pcb_port_hdmi_pcb_port_148",
"pcb_port_hdmi_pcb_port_156",
"pcb_port_hdmi_pcb_port_158",
"pcb_port_hdmi_pcb_port_160",
"pcb_port_hdmi_pcb_port_166",
"pcb_port_hdmi_pcb_port_178",
"pcb_port_hdmi_pcb_port_180",
"pcb_port_hdmi_pcb_port_182",
"pcb_port_hdmi_pcb_port_184",
"pcb_port_hdmi_pcb_port_187",
"pcb_port_hdmi_pcb_port_190",
"pcb_port_hdmi_pcb_port_193",
"pcb_port_hdmi_pcb_port_199",
"pcb_port_hdmi_pcb_port_2",
"pcb_port_hdmi_pcb_port_202",
"pcb_port_hdmi_pcb_port_203",
"pcb_port_hdmi_pcb_port_204",
"pcb_port_hdmi_pcb_port_205",
"pcb_port_hdmi_pcb_port_267",
"pcb_port_hdmi_pcb_port_275",
"pcb_port_hdmi_pcb_port_277",
"pcb_port_hdmi_pcb_port_279",
"pcb_port_hdmi_pcb_port_281",
"pcb_port_hdmi_pcb_port_3",
"pcb_port_hdmi_pcb_port_4",
"pcb_port_hdmi_pcb_port_5",
"pcb_port_hdmi_pcb_port_6",
"pcb_port_hdmi_pcb_port_64",
"pcb_port_hdmi_pcb_port_66",
"pcb_port_hdmi_pcb_port_68",
"pcb_port_hdmi_pcb_port_70",
"pcb_port_hdmi_pcb_port_72",
"pcb_port_hdmi_pcb_port_74",
"pcb_port_hdmi_pcb_port_76",
"pcb_port_hdmi_pcb_port_78",
"pcb_port_hdmi_pcb_port_80",
"pcb_port_hdmi_pcb_port_81",
"pcb_port_hdmi_pcb_port_84",
"pcb_port_hdmi_pcb_port_86",
"pcb_port_hdmi_pcb_port_88",
"pcb_port_hdmi_pcb_port_90",
"pcb_port_hdmi_pcb_port_92",
"pcb_port_hdmi_pcb_port_94",
"pcb_port_hdmi_pcb_port_96",
"pcb_port_hdmi_pcb_port_98",
"pg7_pcb_port_12",
"pg7_pcb_port_16",
"pg7_pcb_port_2",
"short_tx_return_pcb_port_1358",
"short_tx_return_pcb_port_1360",
"short_tx_return_pcb_port_1362",
"short_tx_return_pcb_port_1364"
]
},
{
"root": "10853",
"nets": [
"DDR_A5"
],
"objects": [
"baseline_preserved_pcb_via_14",
"baseline_preserved_pcb_via_15",
"baseline_preserved_signal_source_trace_8",
"baseline_preserved_signal_source_trace_8_via",
"pcb_smtpad_1",
"pcb_smtpad_353"
],
"required_terminals": [
"pcb_port_1",
"pcb_port_353"
]
},
{
"root": "10889",
"nets": [
"DDR_A9"
],
"objects": [
"baseline_preserved_pcb_via_18",
"baseline_preserved_pcb_via_19",
"baseline_preserved_signal_source_trace_24",
"baseline_preserved_signal_source_trace_24_via",
"pcb_smtpad_2",
"pcb_smtpad_370"
],
"required_terminals": [
"pcb_port_2",
"pcb_port_370"
]
},
{
"root": "11450",
"nets": [
"DDR_CKn"
],
"objects": [
"baseline_preserved_pcb_via_88",
"baseline_preserved_pcb_via_89",
"baseline_preserved_signal_source_trace_33",
"baseline_preserved_signal_source_trace_33_via",
"pcb_smtpad_3",
"pcb_smtpad_381"
],
"required_terminals": [
"pcb_port_3",
"pcb_port_381"
]
},
{
"root": "11226",
"nets": [
"DDR_BA1"
],
"objects": [
"baseline_preserved_pcb_via_64",
"baseline_preserved_pcb_via_65",
"baseline_preserved_signal_source_trace_42",
"baseline_preserved_signal_source_trace_42_via",
"pcb_smtpad_4",
"pcb_smtpad_400"
],
"required_terminals": [
"pcb_port_4",
"pcb_port_400"
]
},
{
"root": "11429",
"nets": [
"DDR_CASn"
],
"objects": [
"baseline_preserved_pcb_via_86",
"baseline_preserved_pcb_via_87",
"baseline_preserved_signal_source_trace_19",
"baseline_preserved_signal_source_trace_19_via",
"ca_bridge_DDR_CASn_0",
"ca_bridge_DDR_CASn_1",
"pcb_smtpad_365",
"pcb_smtpad_5"
],
"required_terminals": [
"pcb_port_365",
"pcb_port_5"
]
},
{
"root": "11411",
"nets": [
"DDR_ODT"
],
"objects": [
"baseline_preserved_pcb_via_84",
"baseline_preserved_pcb_via_85",
"baseline_preserved_signal_source_trace_0",
"baseline_preserved_signal_source_trace_0_via",
"ca_bridge_DDR_ODT_0",
"pcb_smtpad_333",
"pcb_smtpad_6"
],
"required_terminals": [
"pcb_port_333",
"pcb_port_6"
]
},
{
"root": "10974",
"nets": [
"DDR_A1"
],
"objects": [
"baseline_preserved_pcb_via_32",
"baseline_preserved_pcb_via_33",
"baseline_preserved_signal_source_trace_36",
"baseline_preserved_signal_source_trace_36_via",
"pcb_smtpad_385",
"pcb_smtpad_7"
],
"required_terminals": [
"pcb_port_385",
"pcb_port_7"
]
},
{
"root": "11068",
"nets": [
"DDR_D8"
],
"objects": [
"baseline_preserved_pcb_via_44",
"baseline_preserved_pcb_via_49",
"baseline_preserved_signal_source_trace_28",
"baseline_preserved_signal_source_trace_28_via",
"pcb_smtpad_358",
"pcb_smtpad_8"
],
"required_terminals": [
"pcb_port_358",
"pcb_port_8"
]
},
{
"root": "11098",
"nets": [
"DDR_D9"
],
"objects": [
"baseline_preserved_pcb_via_45",
"baseline_preserved_pcb_via_48",
"baseline_preserved_signal_source_trace_12",
"baseline_preserved_signal_source_trace_12_via",
"pcb_smtpad_375",
"pcb_smtpad_9"
],
"required_terminals": [
"pcb_port_375",
"pcb_port_9"
]
},
{
"root": "11053",
"nets": [
"DDR_DQS1"
],
"objects": [
"baseline_preserved_pcb_via_42",
"baseline_preserved_pcb_via_43",
"baseline_preserved_signal_source_trace_27",
"baseline_preserved_signal_source_trace_27_via",
"pcb_smtpad_10",
"pcb_smtpad_374"
],
"required_terminals": [
"pcb_port_10",
"pcb_port_374"
]
},
{
"root": "10993",
"nets": [
"DDR_D15"
],
"objects": [
"baseline_preserved_pcb_via_34",
"baseline_preserved_pcb_via_39",
"baseline_preserved_signal_source_trace_11",
"baseline_preserved_signal_source_trace_11_via",
"pcb_smtpad_11",
"pcb_smtpad_389"
],
"required_terminals": [
"pcb_port_11",
"pcb_port_389"
]
},
{
"root": "10831",
"nets": [
"DDR_D2"
],
"objects": [
"baseline_preserved_pcb_via_1",
"baseline_preserved_pcb_via_10",
"baseline_preserved_signal_source_trace_3",
"baseline_preserved_signal_source_trace_3_via",
"pcb_smtpad_12",
"pcb_smtpad_360"
],
"required_terminals": [
"pcb_port_12",
"pcb_port_360"
]
},
{
"root": "10798",
"nets": [
"DDR_DQS0"
],
"objects": [
"baseline_preserved_pcb_via_4",
"baseline_preserved_pcb_via_5",
"baseline_preserved_signal_source_trace_15",
"baseline_preserved_signal_source_trace_15_via",
"pcb_smtpad_13",
"pcb_smtpad_361"
],
"required_terminals": [
"pcb_port_13",
"pcb_port_361"
]
},
{
"root": "13512",
"nets": [
"SYSBOOT0"
],
"objects": [
"baseline_closure_bc1b2a98_SYSBOOT0_reassigned_CPU_root_via_0",
"baseline_reset_ijump_6a4e354b_21_via_26",
"baseline_reset_ijump_6a4e354b_21_via_28",
"baseline_reset_ijump_6a4e354b_21_via_33",
"baseline_reset_ijump_6a4e354b_21_via_35",
"hdmi_retained_boot_SYSBOOT0_0",
"hdmi_retained_boot_SYSBOOT0_1",
"hdmi_retained_boot_SYSBOOT0_2",
"hdmi_retained_boot_SYSBOOT0_3",
"hdmi_retained_boot_SYSBOOT0_4",
"hdmi_retained_boot_SYSBOOT0_5",
"pcb_smtpad_14",
"pcb_smtpad_709"
],
"required_terminals": [
"pcb_port_14",
"pcb_port_709"
]
},
{
"root": "13541",
"nets": [
"SYSBOOT4"
],
"objects": [
"baseline_closure_6536c0d8_SYSBOOT4_CPU_surface_root_via_0",
"baseline_closure_6536c0d8_SYSBOOT4_resistor_surface_root_via_0",
"hdmi_retained_boot_SYSBOOT4_0",
"hdmi_retained_boot_SYSBOOT4_1",
"hdmi_retained_boot_SYSBOOT4_2",
"pcb_smtpad_15",
"pcb_smtpad_717"
],
"required_terminals": [
"pcb_port_15",
"pcb_port_717"
]
},
{
"root": "13552",
"nets": [
"SYSBOOT8"
],
"objects": [
"baseline_closure_657047d2_U1_U1_adapted_boot_root_via_0",
"baseline_closure_ed628361_SYSBOOT8_escape_0_1_via_0",
"hdmi_retained_boot_SYSBOOT8_0",
"hdmi_retained_boot_SYSBOOT8_1",
"hdmi_retained_boot_SYSBOOT8_2",
"pcb_smtpad_16",
"pcb_smtpad_725"
],
"required_terminals": [
"pcb_port_16",
"pcb_port_725"
]
},
{
"root": "12755",
"nets": [
"VDD_MPU"
],
"objects": [
"baseline_bulk_branch_f8da9606_C_PWR8",
"baseline_bulk_branch_f8da9606_C_PWR8_B",
"baseline_closure_4bf9f1fb_VDD_MPU_CPU_power_group_2_1",
"baseline_closure_a3d5dbf8_C_VDD_MPU_1_pin1_actual_rail_feed",
"baseline_closure_a3d5dbf8_C_VDD_MPU_1_pin1_actual_rail_feed_via",
"baseline_closure_a3d5dbf8_C_VDD_MPU_1_pin1_actual_rail_feed_via_0",
"baseline_closure_a3d5dbf8_C_VDD_MPU_2_pin1_actual_rail_feed",
"baseline_closure_a3d5dbf8_C_VDD_MPU_2_pin1_actual_rail_feed_via",
"baseline_closure_a3d5dbf8_C_VDD_MPU_2_pin1_actual_rail_feed_via_0",
"baseline_closure_a3d5dbf8_C_VDD_MPU_3_pin1_actual_rail_feed",
"baseline_closure_a3d5dbf8_C_VDD_MPU_3_pin1_actual_rail_feed_via",
"baseline_closure_a3d5dbf8_C_VDD_MPU_3_pin1_actual_rail_feed_via_0",
"baseline_closure_a3d5dbf8_C_VDD_MPU_4_pin1_actual_rail_feed",
"baseline_closure_a3d5dbf8_C_VDD_MPU_4_pin1_actual_rail_feed_via",
"baseline_closure_a3d5dbf8_C_VDD_MPU_4_pin1_actual_rail_feed_via_0",
"baseline_closure_bf77cf69_C_VDD_MPU_0_pin1_existing",
"baseline_closure_f3643d14_MPU_bulk_relocation_supply",
"baseline_closure_f3643d14_MPU_bulk_relocation_supply_via",
"baseline_closure_f3643d14_MPU_bulk_relocation_supply_via_0",
"baseline_north_feedback_17787539_VDD_MPU",
"baseline_north_feedback_17787539_VDD_MPU_via",
"baseline_pcb_via_1",
"baseline_processor_feed_82463290_2_load_VDD_MPU",
"baseline_processor_feed_82463290_2_load_VDD_MPU_via",
"baseline_processor_feed_d5c8ff87_0_load_VDD_MPU",
"baseline_processor_feed_d5c8ff87_0_load_VDD_MPU_via",
"baseline_processor_feed_d5c8ff87_1_load_VDD_MPU",
"baseline_processor_feed_d5c8ff87_1_load_VDD_MPU_via",
"baseline_rail_region_MPU_distribution_0",
"baseline_rail_region_MPU_distribution_1",
"baseline_support_escape_U1_A2",
"baseline_support_escape_U1_F10",
"baseline_support_escape_U1_F11",
"baseline_support_escape_U1_F12",
"baseline_support_escape_U1_F13",
"baseline_support_escape_U1_G13",
"baseline_support_escape_U1_H13",
"baseline_support_escape_U1_J13",
"baseline_support_via_U1_A2",
"baseline_support_via_U1_F10",
"baseline_support_via_U1_F12",
"baseline_support_via_U1_F13",
"baseline_support_via_U1_G13",
"baseline_support_via_U1_H13",
"baseline_support_via_U1_J13",
"dbg_pcb_smtpad_3",
"dbg_pcb_trace_3",
"pcb_smtpad_167",
"pcb_smtpad_18",
"pcb_smtpad_185",
"pcb_smtpad_203",
"pcb_smtpad_221",
"pcb_smtpad_222",
"pcb_smtpad_223",
"pcb_smtpad_224",
"pcb_smtpad_460",
"pcb_smtpad_472",
"pcb_smtpad_493",
"pcb_smtpad_495",
"pcb_smtpad_557",
"pcb_smtpad_559",
"pcb_smtpad_561",
"pcb_smtpad_563",
"pcb_smtpad_565",
"pcb_smtpad_567"
],
"required_terminals": [
"dbg_pcb_port_3",
"pcb_port_167",
"pcb_port_18",
"pcb_port_185",
"pcb_port_203",
"pcb_port_221",
"pcb_port_222",
"pcb_port_223",
"pcb_port_224",
"pcb_port_460",
"pcb_port_472",
"pcb_port_493",
"pcb_port_495",
"pcb_port_557",
"pcb_port_559",
"pcb_port_561",
"pcb_port_563",
"pcb_port_565",
"pcb_port_567"
]
},
{
"root": "10868",
"nets": [
"DDR_WEn"
],
"objects": [
"baseline_preserved_pcb_via_16",
"baseline_preserved_pcb_via_17",
"baseline_preserved_signal_source_trace_20",
"baseline_preserved_signal_source_trace_20_via",
"ca_bridge_DDR_WEn_0",
"pcb_smtpad_19",
"pcb_smtpad_366"
],
"required_terminals": [
"pcb_port_19",
"pcb_port_366"
]
},
{
"root": "10963",
"nets": [
"DDR_A4"
],
"objects": [
"baseline_preserved_pcb_via_30",
"baseline_preserved_pcb_via_31",
"baseline_preserved_signal_source_trace_43",
"baseline_preserved_signal_source_trace_43_via",
"pcb_smtpad_20",
"pcb_smtpad_401"
],
"required_terminals": [
"pcb_port_20",
"pcb_port_401"
]
},
{
"root": "11488",
"nets": [
"DDR_CK"
],
"objects": [
"baseline_preserved_pcb_via_92",
"baseline_preserved_pcb_via_93",
"baseline_preserved_signal_source_trace_32",
"baseline_preserved_signal_source_trace_32_via",
"pcb_smtpad_21",
"pcb_smtpad_380"
],
"required_terminals": [
"pcb_port_21",
"pcb_port_380"
]
},
{
"root": "11387",
"nets": [
"DDR_A7"
],
"objects": [
"baseline_preserved_pcb_via_82",
"baseline_preserved_pcb_via_83",
"baseline_preserved_signal_source_trace_9",
"baseline_preserved_signal_source_trace_9_via",
"ca_bridge_DDR_A7_0",
"ca_bridge_DDR_A7_1",
"pcb_smtpad_22",
"pcb_smtpad_354"
],
"required_terminals": [
"pcb_port_22",
"pcb_port_354"
]
},
{
"root": "11343",
"nets": [
"DDR_A11"
],
"objects": [
"baseline_preserved_pcb_via_78",
"baseline_preserved_pcb_via_79",
"baseline_preserved_signal_source_trace_37",
"baseline_preserved_signal_source_trace_37_via",
"ca_bridge_DDR_A11_0",
"ca_bridge_DDR_A11_1",
"pcb_smtpad_23",
"pcb_smtpad_386"
],
"required_terminals": [
"pcb_port_23",
"pcb_port_386"
]
},
{
"root": "11899",
"nets": [
"DDR_RESETn"
],
"objects": [
"baseline_preserved_pcb_via_76",
"baseline_preserved_pcb_via_77",
"baseline_preserved_signal_source_trace_10",
"baseline_preserved_signal_source_trace_10_via",
"baseline_reset_ijump_a3c6bd23_13",
"baseline_reset_ijump_a3c6bd23_13_via",
"baseline_reset_ijump_a3c6bd23_13_via_7",
"pcb_smtpad_24",
"pcb_smtpad_355",
"pcb_smtpad_673"
],
"required_terminals": [
"pcb_port_24",
"pcb_port_355",
"pcb_port_673"
]
},
{
"root": "11469",
"nets": [
"DDR_CSn0"
],
"objects": [
"baseline_preserved_pcb_via_90",
"baseline_preserved_pcb_via_91",
"baseline_preserved_signal_source_trace_5",
"baseline_preserved_signal_source_trace_5_via",
"pcb_smtpad_25",
"pcb_smtpad_350"
],
"required_terminals": [
"pcb_port_25",
"pcb_port_350"
]
},
{
"root": "11113",
"nets": [
"DDR_DQM1"
],
"objects": [
"baseline_preserved_pcb_via_50",
"baseline_preserved_pcb_via_51",
"baseline_preserved_signal_source_trace_13",
"baseline_preserved_signal_source_trace_13_via",
"pcb_smtpad_26",
"pcb_smtpad_359"
],
"required_terminals": [
"pcb_port_26",
"pcb_port_359"
]
},
{
"root": "11083",
"nets": [
"DDR_D10"
],
"objects": [
"baseline_preserved_pcb_via_35",
"baseline_preserved_pcb_via_46",
"baseline_preserved_signal_source_trace_39",
"baseline_preserved_signal_source_trace_39_via",
"pcb_smtpad_27",
"pcb_smtpad_356"
],
"required_terminals": [
"pcb_port_27",
"pcb_port_356"
]
},
{
"root": "11008",
"nets": [
"DDR_DQSn1"
],
"objects": [
"baseline_preserved_pcb_via_36",
"baseline_preserved_pcb_via_37",
"baseline_preserved_signal_source_trace_26",
"baseline_preserved_signal_source_trace_26_via",
"pcb_smtpad_28",
"pcb_smtpad_373"
],
"required_terminals": [
"pcb_port_28",
"pcb_port_373"
]
},
{
"root": "10787",
"nets": [
"DDR_DQM0"
],
"objects": [
"baseline_preserved_pcb_via_2",
"baseline_preserved_pcb_via_3",
"baseline_preserved_signal_source_trace_29",
"baseline_preserved_signal_source_trace_29_via",
"pcb_smtpad_29",
"pcb_smtpad_376"
],
"required_terminals": [
"pcb_port_29",
"pcb_port_376"
]
},
{
"root": "10842",
"nets": [
"DDR_D3"
],
"objects": [
"baseline_preserved_pcb_via_12",
"baseline_preserved_pcb_via_25",
"baseline_preserved_signal_source_trace_40",
"baseline_preserved_signal_source_trace_40_via",
"pcb_smtpad_30",
"pcb_smtpad_363"
],
"required_terminals": [
"pcb_port_30",
"pcb_port_363"
]
},
{
"root": "10809",
"nets": [
"DDR_DQSn0"
],
"objects": [
"baseline_preserved_pcb_via_6",
"baseline_preserved_pcb_via_7",
"baseline_preserved_signal_source_trace_16",
"baseline_preserved_signal_source_trace_16_via",
"pcb_smtpad_31",
"pcb_smtpad_362"
],
"required_terminals": [
"pcb_port_31",
"pcb_port_362"
]
},
{
"root": "13518",
"nets": [
"SYSBOOT1"
],
"objects": [
"baseline_reset_ijump_0799c6f5_0_via_11",
"baseline_reset_ijump_0799c6f5_0_via_14",
"hdmi_boot_fence_SYSBOOT1_source_via",
"hdmi_boot_fence_SYSBOOT1_via_0",
"hdmi_boot_fence_SYSBOOT1_via_1",
"hdmi_boot_fence_SYSBOOT1_via_2",
"hdmi_retained_boot_SYSBOOT1_0",
"hdmi_retained_boot_SYSBOOT1_0_via",
"hdmi_retained_boot_SYSBOOT1_1",
"hdmi_retained_boot_SYSBOOT1_2",
"pcb_smtpad_32",
"pcb_smtpad_711"
],
"required_terminals": [
"pcb_port_32",
"pcb_port_711"
]
},
{
"root": "13544",
"nets": [
"SYSBOOT5"
],
"objects": [
"baseline_closure_850b6820_R_BOOT5_pin1_surface_contact_via_0",
"baseline_support_via_U1_T2",
"hdmi_retained_boot_SYSBOOT5_0",
"hdmi_retained_boot_SYSBOOT5_1",
"hdmi_retained_boot_SYSBOOT5_2",
"pcb_smtpad_33",
"pcb_smtpad_719"
],
"required_terminals": [
"pcb_port_33",
"pcb_port_719"
]
},
{
"root": "13556",
"nets": [
"SYSBOOT9"
],
"objects": [
"baseline_reset_ijump_c9eda02b_6_via_16",
"baseline_support_via_U1_U2",
"hdmi_retained_boot_SYSBOOT9_0",
"hdmi_retained_boot_SYSBOOT9_1",
"hdmi_retained_boot_SYSBOOT9_2",
"hdmi_retained_boot_SYSBOOT9_3",
"pcb_smtpad_34",
"pcb_smtpad_727"
],
"required_terminals": [
"pcb_port_34",
"pcb_port_727"
]
},
{
"root": "13565",
"nets": [
"SYSBOOT12"
],
"objects": [
"baseline_closure_925266cf_SYSBOOT12_group_0_1_via_0",
"baseline_support_via_U1_V2",
"hdmi_retained_boot_SYSBOOT12_0",
"hdmi_retained_boot_SYSBOOT12_1",
"hdmi_retained_boot_SYSBOOT12_2",
"pcb_smtpad_35",
"pcb_smtpad_733"
],
"required_terminals": [
"pcb_port_35",
"pcb_port_733"
]
},
{
"root": "36",
"nets": [],
"objects": [
"pcb_smtpad_36"
],
"required_terminals": []
},
{
"root": "10904",
"nets": [
"DDR_BA2"
],
"objects": [
"baseline_preserved_pcb_via_20",
"baseline_preserved_pcb_via_21",
"baseline_preserved_signal_source_trace_21",
"baseline_preserved_signal_source_trace_21_via",
"pcb_smtpad_367",
"pcb_smtpad_37"
],
"required_terminals": [
"pcb_port_367",
"pcb_port_37"
]
},
{
"root": "11173",
"nets": [
"DDR_A3"
],
"objects": [
"baseline_preserved_pcb_via_58",
"baseline_preserved_pcb_via_59",
"baseline_preserved_signal_source_trace_7",
"baseline_preserved_signal_source_trace_7_via",
"ca_bridge_DDR_A3_0",
"pcb_smtpad_352",
"pcb_smtpad_38"
],
"required_terminals": [
"pcb_port_352",
"pcb_port_38"
]
},
{
"root": "39",
"nets": [],
"objects": [
"pcb_smtpad_39"
],
"required_terminals": []
},
{
"root": "11313",
"nets": [
"DDR_A12"
],
"objects": [
"baseline_preserved_pcb_via_74",
"baseline_preserved_pcb_via_75",
"baseline_preserved_signal_source_trace_35",
"baseline_preserved_signal_source_trace_35_via",
"pcb_smtpad_384",
"pcb_smtpad_40"
],
"required_terminals": [
"pcb_port_384",
"pcb_port_40"
]
},
{
"root": "11272",
"nets": [
"DDR_A0"
],
"objects": [
"baseline_preserved_pcb_via_70",
"baseline_preserved_pcb_via_71",
"baseline_preserved_signal_source_trace_22",
"baseline_preserved_signal_source_trace_22_via",
"ca_bridge_DDR_A0_0",
"pcb_smtpad_368",
"pcb_smtpad_41"
],
"required_terminals": [
"pcb_port_368",
"pcb_port_41"
]
},
{
"root": "11241",
"nets": [
"DDR_CKE"
],
"objects": [
"baseline_preserved_pcb_via_66",
"baseline_preserved_pcb_via_67",
"baseline_preserved_signal_source_trace_46",
"baseline_preserved_signal_source_trace_46_via",
"pcb_smtpad_413",
"pcb_smtpad_42"
],
"required_terminals": [
"pcb_port_413",
"pcb_port_42"
]
},
{
"root": "43",
"nets": [],
"objects": [
"pcb_smtpad_43"
],
"required_terminals": []
},
{
"root": "12033",
"nets": [
"DDR_VTP"
],
"objects": [
"baseline_support_escape_U1_J3",
"baseline_support_via_U1_J3",
"baseline_vtp_l3_2f2819c3",
"baseline_vtp_l3_2f2819c3_via",
"pcb_smtpad_44",
"pcb_smtpad_657"
],
"required_terminals": [
"pcb_port_44",
"pcb_port_657"
]
},
{
"root": "11143",
"nets": [
"DDR_D11"
],
"objects": [
"baseline_preserved_pcb_via_54",
"baseline_preserved_pcb_via_55",
"baseline_preserved_signal_source_trace_2",
"baseline_preserved_signal_source_trace_2_via",
"pcb_smtpad_342",
"pcb_smtpad_45"
],
"required_terminals": [
"pcb_port_342",
"pcb_port_45"
]
},
{
"root": "11038",
"nets": [
"DDR_D13"
],
"objects": [
"baseline_preserved_pcb_via_40",
"baseline_preserved_pcb_via_53",
"baseline_preserved_signal_source_trace_1",
"baseline_preserved_signal_source_trace_1_via",
"pcb_smtpad_372",
"pcb_smtpad_46"
],
"required_terminals": [
"pcb_port_372",
"pcb_port_46"
]
},
{
"root": "10776",
"nets": [
"DDR_D0"
],
"objects": [
"baseline_preserved_pcb_via_0",
"baseline_preserved_pcb_via_11",
"baseline_preserved_signal_source_trace_14",
"baseline_preserved_signal_source_trace_14_via",
"pcb_smtpad_345",
"pcb_smtpad_47"
],
"required_terminals": [
"pcb_port_345",
"pcb_port_47"
]
},
{
"root": "10926",
"nets": [
"DDR_D4"
],
"objects": [
"baseline_preserved_pcb_via_13",
"baseline_preserved_pcb_via_24",
"baseline_preserved_signal_source_trace_17",
"baseline_preserved_signal_source_trace_17_via",
"pcb_smtpad_393",
"pcb_smtpad_48"
],
"required_terminals": [
"pcb_port_393",
"pcb_port_48"
]
},
{
"root": "10915",
"nets": [
"DDR_D6"
],
"objects": [
"baseline_preserved_pcb_via_22",
"baseline_preserved_pcb_via_9",
"baseline_preserved_signal_source_trace_4",
"baseline_preserved_signal_source_trace_4_via",
"pcb_smtpad_377",
"pcb_smtpad_49"
],
"required_terminals": [
"pcb_port_377",
"pcb_port_49"
]
},
{
"root": "13535",
"nets": [
"SYSBOOT2"
],
"objects": [
"baseline_closure_5bb7a382_SYSBOOT2_final_resistor_root_via_0",
"baseline_closure_7fadfe01_SYSBOOT2_joint_window_root_via_0",
"hdmi_retained_boot_SYSBOOT2_0",
"hdmi_retained_boot_SYSBOOT2_1",
"hdmi_retained_boot_SYSBOOT2_2",
"pcb_smtpad_50",
"pcb_smtpad_713"
],
"required_terminals": [
"pcb_port_50",
"pcb_port_713"
]
},
{
"root": "13547",
"nets": [
"SYSBOOT6"
],
"objects": [
"baseline_support_via_U1_T3",
"hdmi_retained_boot_SYSBOOT6_0",
"hdmi_retained_boot_SYSBOOT6_1",
"pcb_smtpad_51",
"pcb_smtpad_721"
],
"required_terminals": [
"pcb_port_51",
"pcb_port_721"
]
},
{
"root": "13559",
"nets": [
"SYSBOOT10"
],
"objects": [
"baseline_closure_2019bfbf_R_BOOT10_signal_surface_via_0",
"baseline_support_via_U1_U3",
"hdmi_retained_boot_SYSBOOT10_0",
"hdmi_retained_boot_SYSBOOT10_1",
"hdmi_retained_boot_SYSBOOT10_2",
"pcb_smtpad_52",
"pcb_smtpad_729"
],
"required_terminals": [
"pcb_port_52",
"pcb_port_729"
]
},
{
"root": "13568",
"nets": [
"SYSBOOT13"
],
"objects": [
"baseline_closure_50a6dd03_R_BOOT13_pin1_clock_crossing_surface_via_0",
"baseline_reset_ijump_c9eda02b_10_via_14",
"baseline_reset_ijump_c9eda02b_10_via_9",
"baseline_support_via_U1_V3",
"hdmi_retained_boot_SYSBOOT13_0",
"hdmi_retained_boot_SYSBOOT13_1",
"hdmi_retained_boot_SYSBOOT13_2",
"hdmi_retained_boot_SYSBOOT13_3",
"hdmi_retained_boot_SYSBOOT13_4",
"pcb_smtpad_53",
"pcb_smtpad_735"
],
"required_terminals": [
"pcb_port_53",
"pcb_port_735"
]
},
{
"root": "54",
"nets": [],
"objects": [
"pcb_smtpad_54"
],
"required_terminals": []
},
{
"root": "12660",
"nets": [
"RTC_KALDO_EN_N"
],
"objects": [
"baseline_closure_9ea03c89_RTC_KALDO_EN_N_escape_0_1",
"baseline_closure_9ea03c89_RTC_KALDO_EN_N_escape_0_1_via",
"baseline_closure_9ea03c89_RTC_KALDO_EN_N_escape_0_1_via_0",
"baseline_support_escape_U1_B4",
"baseline_support_via_U1_B4",
"pcb_smtpad_531",
"pcb_smtpad_55"
],
"required_terminals": [
"pcb_port_531",
"pcb_port_55"
]
},
{
"root": "11158",
"nets": [
"DDR_BA0"
],
"objects": [
"baseline_preserved_pcb_via_56",
"baseline_preserved_pcb_via_57",
"baseline_preserved_signal_source_trace_6",
"baseline_preserved_signal_source_trace_6_via",
"pcb_smtpad_351",
"pcb_smtpad_56"
],
"required_terminals": [
"pcb_port_351",
"pcb_port_56"
]
},
{
"root": "11215",
"nets": [
"DDR_A8"
],
"objects": [
"baseline_preserved_pcb_via_62",
"baseline_preserved_pcb_via_63",
"baseline_preserved_signal_source_trace_45",
"baseline_preserved_signal_source_trace_45_via",
"pcb_smtpad_403",
"pcb_smtpad_57"
],
"required_terminals": [
"pcb_port_403",
"pcb_port_57"
]
},
{
"root": "11252",
"nets": [
"DDR_A2"
],
"objects": [
"baseline_preserved_pcb_via_68",
"baseline_preserved_pcb_via_69",
"baseline_preserved_signal_source_trace_23",
"baseline_preserved_signal_source_trace_23_via",
"pcb_smtpad_369",
"pcb_smtpad_58"
],
"required_terminals": [
"pcb_port_369",
"pcb_port_58"
]
},
{
"root": "11293",
"nets": [
"DDR_A10"
],
"objects": [
"baseline_preserved_pcb_via_72",
"baseline_preserved_pcb_via_73",
"baseline_preserved_signal_source_trace_34",
"baseline_preserved_signal_source_trace_34_via",
"ca_bridge_DDR_A10_0",
"pcb_smtpad_382",
"pcb_smtpad_59"
],
"required_terminals": [
"pcb_port_382",
"pcb_port_59"
]
},
{
"root": "11366",
"nets": [
"DDR_RASn"
],
"objects": [
"baseline_preserved_pcb_via_80",
"baseline_preserved_pcb_via_81",
"baseline_preserved_signal_source_trace_18",
"baseline_preserved_signal_source_trace_18_via",
"ca_bridge_DDR_RASn_0",
"pcb_smtpad_364",
"pcb_smtpad_60"
],
"required_terminals": [
"pcb_port_364",
"pcb_port_60"
]
},
{
"root": "61",
"nets": [],
"objects": [
"pcb_smtpad_61"
],
"required_terminals": []
},
{
"root": "12717",
"nets": [
"DDR_VREF"
],
"objects": [
"baseline_reset_ijump_d886ba68_2",
"baseline_reset_ijump_d886ba68_2_via",
"baseline_reset_ijump_d886ba68_2_via_20",
"baseline_reset_ijump_d886ba68_2_via_5",
"baseline_reset_ijump_ee87e890_0",
"baseline_reset_ijump_ee87e890_2",
"baseline_reset_ijump_ee87e890_3",
"baseline_reset_ijump_ee87e890_4",
"baseline_reset_ijump_ee87e890_6",
"baseline_reset_ijump_f9f37ff3_0",
"baseline_reset_ijump_f9f37ff3_0_via",
"baseline_reset_ijump_f9f37ff3_0_via_47",
"baseline_reset_ijump_f9f37ff3_0_via_9",
"baseline_support_escape_U1_J4",
"baseline_support_escape_U3_H1",
"baseline_support_escape_U3_M8",
"baseline_support_via_U1_J4",
"baseline_support_via_U3_H1",
"baseline_support_via_U3_M8",
"baseline_vref_l3_5690d202_support_via_U3_H1",
"baseline_vref_l3_c4c96cfa_support_via_U3_M8",
"pcb_smtpad_331",
"pcb_smtpad_399",
"pcb_smtpad_62",
"pcb_smtpad_660",
"pcb_smtpad_661",
"pcb_smtpad_664",
"pcb_smtpad_665",
"pcb_smtpad_667",
"pcb_smtpad_669",
"pcb_smtpad_671"
],
"required_terminals": [
"pcb_port_331",
"pcb_port_399",
"pcb_port_62",
"pcb_port_660",
"pcb_port_661",
"pcb_port_664",
"pcb_port_665",
"pcb_port_667",
"pcb_port_669",
"pcb_port_671"
]
},
{
"root": "11128",
"nets": [
"DDR_D12"
],
"objects": [
"baseline_preserved_pcb_via_41",
"baseline_preserved_pcb_via_52",
"baseline_preserved_signal_source_trace_25",
"baseline_preserved_signal_source_trace_25_via",
"pcb_smtpad_340",
"pcb_smtpad_63"
],
"required_terminals": [
"pcb_port_340",
"pcb_port_63"
]
},
{
"root": "11023",
"nets": [
"DDR_D14"
],
"objects": [
"baseline_preserved_pcb_via_38",
"baseline_preserved_pcb_via_47",
"baseline_preserved_signal_source_trace_38",
"baseline_preserved_signal_source_trace_38_via",
"pcb_smtpad_390",
"pcb_smtpad_64"
],
"required_terminals": [
"pcb_port_390",
"pcb_port_64"
]
},
{
"root": "10820",
"nets": [
"DDR_D1"
],
"objects": [
"baseline_preserved_pcb_via_23",
"baseline_preserved_pcb_via_8",
"baseline_preserved_signal_source_trace_30",
"baseline_preserved_signal_source_trace_30_via",
"pcb_smtpad_346",
"pcb_smtpad_65"
],
"required_terminals": [
"pcb_port_346",
"pcb_port_65"
]
},
{
"root": "10948",
"nets": [
"DDR_D5"
],
"objects": [
"baseline_preserved_pcb_via_27",
"baseline_preserved_pcb_via_28",
"baseline_preserved_signal_source_trace_41",
"baseline_preserved_signal_source_trace_41_via",
"pcb_smtpad_379",
"pcb_smtpad_66"
],
"required_terminals": [
"pcb_port_379",
"pcb_port_66"
]
},
{
"root": "10937",
"nets": [
"DDR_D7"
],
"objects": [
"baseline_preserved_pcb_via_26",
"baseline_preserved_pcb_via_29",
"baseline_preserved_signal_source_trace_31",
"baseline_preserved_signal_source_trace_31_via",
"pcb_smtpad_395",
"pcb_smtpad_67"
],
"required_terminals": [
"pcb_port_395",
"pcb_port_67"
]
},
{
"root": "13538",
"nets": [
"SYSBOOT3"
],
"objects": [
"baseline_closure_10ee3c19_SYSBOOT3_partition_repair_via_0",
"baseline_support_via_U1_R4",
"hdmi_retained_boot_SYSBOOT3_0",
"hdmi_retained_boot_SYSBOOT3_1",
"hdmi_retained_boot_SYSBOOT3_2",
"pcb_smtpad_68",
"pcb_smtpad_715"
],
"required_terminals": [
"pcb_port_68",
"pcb_port_715"
]
},
{
"root": "13549",
"nets": [
"SYSBOOT7"
],
"objects": [
"baseline_closure_38c02ca0_SYSBOOT7_final_resistor_root_via_0",
"baseline_support_via_U1_R2",
"hdmi_retained_boot_SYSBOOT7_0",
"hdmi_retained_boot_SYSBOOT7_1",
"hdmi_retained_boot_SYSBOOT7_2",
"pcb_smtpad_69",
"pcb_smtpad_723"
],
"required_terminals": [
"pcb_port_69",
"pcb_port_723"
]
},
{
"root": "13562",
"nets": [
"SYSBOOT11"
],
"objects": [
"baseline_closure_265b8675_R_BOOT11_pin1_surface_contact_via_0",
"baseline_support_via_U1_U4",
"hdmi_retained_boot_SYSBOOT11_0",
"hdmi_retained_boot_SYSBOOT11_1",
"hdmi_retained_boot_SYSBOOT11_2",
"pcb_smtpad_70",
"pcb_smtpad_731"
],
"required_terminals": [
"pcb_port_70",
"pcb_port_731"
]
},
{
"root": "13573",
"nets": [
"SYSBOOT14"
],
"objects": [
"baseline_closure_33a3116a_SYSBOOT14_group_0_1_via_0",
"baseline_support_via_U1_V4",
"hdmi_retained_boot_SYSBOOT14_0",
"hdmi_retained_boot_SYSBOOT14_1",
"hdmi_retained_boot_SYSBOOT14_2",
"pcb_smtpad_71",
"pcb_smtpad_737"
],
"required_terminals": [
"pcb_port_71",
"pcb_port_737"
]
},
{
"root": "11797",
"nets": [
"RTC_RESET_N"
],
"objects": [
"baseline_reset_ijump_3",
"baseline_reset_ijump_3_via",
"baseline_reset_ijump_3_via_11",
"baseline_reset_ijump_3_via_14",
"baseline_reset_ijump_4",
"baseline_reset_ijump_4_via",
"baseline_reset_ijump_4_via_14",
"baseline_reset_ijump_4_via_16",
"baseline_reset_ijump_f8b6f07c_5",
"baseline_support_escape_U1_B5",
"baseline_support_via_U1_B5",
"pcb_smtpad_530",
"pcb_smtpad_73",
"pcb_smtpad_886",
"pcb_smtpad_895"
],
"required_terminals": [
"pcb_port_530",
"pcb_port_73",
"pcb_port_890",
"pcb_port_895"
]
},
{
"root": "12496",
"nets": [
"EXT_WAKEUP"
],
"objects": [
"baseline_closure_847f7e5f_EXT_WAKEUP_group_0_1",
"baseline_closure_847f7e5f_EXT_WAKEUP_group_0_1_via",
"baseline_closure_847f7e5f_EXT_WAKEUP_group_0_1_via_0",
"baseline_support_escape_U1_C5",
"baseline_support_via_U1_C5",
"pcb_smtpad_535",
"pcb_smtpad_74"
],
"required_terminals": [
"pcb_port_535",
"pcb_port_74"
]
},
{
"root": "11195",
"nets": [
"DDR_A6"
],
"objects": [
"baseline_preserved_pcb_via_60",
"baseline_preserved_pcb_via_61",
"baseline_preserved_signal_source_trace_44",
"baseline_preserved_signal_source_trace_44_via",
"ca_bridge_DDR_A6_0",
"pcb_smtpad_402",
"pcb_smtpad_75"
],
"required_terminals": [
"pcb_port_402",
"pcb_port_75"
]
},
{
"root": "12184",
"nets": [
"DDR_1V5"
],
"objects": [
"baseline_bulk_branch_f8da9606_C_PWR9",
"baseline_bulk_branch_f8da9606_C_PWR9_B",
"baseline_closure_98afff44_U3_C9_actual_supply",
"baseline_closure_bf77cf69_R_DDR_RESET_pin2_tap0",
"baseline_closure_bf77cf69_R_DDR_RESET_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_VREF_TOP_pin1_existing",
"baseline_ddr_cap_222cd283_pcb_port_919",
"baseline_ddr_cap_222cd283_pcb_port_919_via",
"baseline_ddr_cap_4c88c897_pcb_port_699",
"baseline_ddr_cap_4c88c897_pcb_port_699_via",
"baseline_ddr_cap_4c88c897_pcb_port_701",
"baseline_ddr_cap_4c88c897_pcb_port_701_via",
"baseline_ddr_cap_4c88c897_pcb_port_703",
"baseline_ddr_cap_4c88c897_pcb_port_703_via",
"baseline_ddr_cap_4c88c897_pcb_port_705",
"baseline_ddr_cap_4c88c897_pcb_port_705_via",
"baseline_ddr_cap_4c88c897_pcb_port_913",
"baseline_ddr_cap_4c88c897_pcb_port_913_via",
"baseline_ddr_cap_4c88c897_pcb_port_915",
"baseline_ddr_cap_4c88c897_pcb_port_915_via",
"baseline_ddr_cap_4c88c897_pcb_port_917",
"baseline_ddr_cap_4c88c897_pcb_port_917_via",
"baseline_ddr_cap_4c88c897_pcb_port_921",
"baseline_ddr_cap_4c88c897_pcb_port_921_via",
"baseline_ddr_cap_4c88c897_pcb_port_925",
"baseline_ddr_cap_4c88c897_pcb_port_925_via",
"baseline_ddr_cap_4c88c897_pcb_port_927",
"baseline_ddr_cap_4c88c897_pcb_port_927_via",
"baseline_ddr_cap_4c88c897_pcb_port_929",
"baseline_ddr_cap_4c88c897_pcb_port_929_via",
"baseline_ddr_cap_4c88c897_pcb_port_931",
"baseline_ddr_cap_4c88c897_pcb_port_931_via",
"baseline_ddr_cap_4c88c897_pcb_port_933",
"baseline_ddr_cap_4c88c897_pcb_port_933_via",
"baseline_ddr_cap_711ac343_pcb_port_909",
"baseline_ddr_cap_711ac343_pcb_port_909_via",
"baseline_ddr_cap_d36217b1_pcb_port_707",
"baseline_ddr_cap_d36217b1_pcb_port_707_via",
"baseline_ddr_cap_d36217b1_pcb_port_905",
"baseline_ddr_cap_d36217b1_pcb_port_905_via",
"baseline_ddr_cap_d36217b1_pcb_port_907",
"baseline_ddr_cap_d36217b1_pcb_port_907_via",
"baseline_ddr_cap_d36217b1_pcb_port_911",
"baseline_ddr_cap_d36217b1_pcb_port_911_via",
"baseline_ddr_cap_d36217b1_pcb_port_923",
"baseline_ddr_cap_d36217b1_pcb_port_923_via",
"baseline_north_feedback_17787539_DDR_1V5",
"baseline_north_feedback_17787539_DDR_1V5_via",
"baseline_pcb_copper_pour_2_0",
"baseline_pcb_via_4",
"baseline_pcb_via_5",
"baseline_plane_tie_DDR_1V5_0dee7f1d_0",
"baseline_plane_tie_DDR_1V5_0dee7f1d_0_via",
"baseline_plane_tie_DDR_1V5_0dee7f1d_2",
"baseline_plane_tie_DDR_1V5_0dee7f1d_2_via",
"baseline_plane_tie_DDR_1V5_0dee7f1d_4",
"baseline_plane_tie_DDR_1V5_0dee7f1d_4_via",
"baseline_plane_tie_DDR_1V5_0dee7f1d_6",
"baseline_plane_tie_DDR_1V5_0dee7f1d_6_via",
"baseline_plane_tie_DDR_1V5_0dee7f1d_8",
"baseline_plane_tie_DDR_1V5_0dee7f1d_8_via",
"baseline_processor_feed_0b682182_0_load_DDR_1V5",
"baseline_processor_feed_0b682182_0_load_DDR_1V5_via",
"baseline_processor_feed_0b682182_1_load_DDR_1V5",
"baseline_processor_feed_0b682182_1_load_DDR_1V5_via",
"baseline_processor_feed_0b682182_2_load_DDR_1V5",
"baseline_processor_feed_0b682182_2_load_DDR_1V5_via",
"baseline_ram_decap_C_RAM_0_1",
"baseline_ram_decap_C_RAM_0_1_via",
"baseline_ram_decap_C_RAM_10_1",
"baseline_ram_decap_C_RAM_10_1_via",
"baseline_ram_decap_C_RAM_11_1",
"baseline_ram_decap_C_RAM_11_1_via",
"baseline_ram_decap_C_RAM_1_1",
"baseline_ram_decap_C_RAM_1_1_via",
"baseline_ram_decap_C_RAM_2_1",
"baseline_ram_decap_C_RAM_2_1_via",
"baseline_ram_decap_C_RAM_3_1",
"baseline_ram_decap_C_RAM_3_1_via",
"baseline_ram_decap_C_RAM_4_1",
"baseline_ram_decap_C_RAM_4_1_via",
"baseline_ram_decap_C_RAM_5_1",
"baseline_ram_decap_C_RAM_5_1_via",
"baseline_ram_decap_C_RAM_6_1",
"baseline_ram_decap_C_RAM_6_1_via",
"baseline_ram_decap_C_RAM_7_1",
"baseline_ram_decap_C_RAM_7_1_via",
"baseline_ram_decap_C_RAM_8_1",
"baseline_ram_decap_C_RAM_8_1_via",
"baseline_ram_decap_C_RAM_9_1",
"baseline_ram_decap_C_RAM_9_1_via",
"baseline_support_escape_U1_E5",
"baseline_support_escape_U1_F5",
"baseline_support_escape_U1_G5",
"baseline_support_escape_U1_H5",
"baseline_support_escape_U1_J5",
"baseline_support_escape_U1_K5",
"baseline_support_escape_U1_L5",
"baseline_support_escape_U3_A1",
"baseline_support_escape_U3_A8",
"baseline_support_escape_U3_B2",
"baseline_support_escape_U3_C1",
"baseline_support_escape_U3_D2",
"baseline_support_escape_U3_D9",
"baseline_support_escape_U3_E9",
"baseline_support_escape_U3_F1",
"baseline_support_escape_U3_G7",
"baseline_support_escape_U3_H2",
"baseline_support_escape_U3_H9",
"baseline_support_escape_U3_K2",
"baseline_support_escape_U3_K8",
"baseline_support_escape_U3_N1",
"baseline_support_escape_U3_N9",
"baseline_support_escape_U3_R1",
"baseline_support_escape_U3_R9",
"baseline_support_via_U1_E5",
"baseline_support_via_U1_F5",
"baseline_support_via_U1_G5",
"baseline_support_via_U1_H5",
"baseline_support_via_U1_J5",
"baseline_support_via_U1_K5",
"baseline_support_via_U1_L5",
"baseline_support_via_U3_A1",
"baseline_support_via_U3_A8",
"baseline_support_via_U3_B2",
"baseline_support_via_U3_C1",
"baseline_support_via_U3_D9",
"baseline_support_via_U3_E9",
"baseline_support_via_U3_F1",
"baseline_support_via_U3_G7",
"baseline_support_via_U3_H2",
"baseline_support_via_U3_H9",
"baseline_support_via_U3_K8",
"baseline_support_via_U3_N1",
"baseline_support_via_U3_N9",
"baseline_support_via_U3_R1",
"baseline_support_via_U3_R9",
"pcb_smtpad_324",
"pcb_smtpad_326",
"pcb_smtpad_329",
"pcb_smtpad_336",
"pcb_smtpad_338",
"pcb_smtpad_341",
"pcb_smtpad_343",
"pcb_smtpad_347",
"pcb_smtpad_349",
"pcb_smtpad_378",
"pcb_smtpad_388",
"pcb_smtpad_397",
"pcb_smtpad_406",
"pcb_smtpad_407",
"pcb_smtpad_408",
"pcb_smtpad_411",
"pcb_smtpad_416",
"pcb_smtpad_418",
"pcb_smtpad_458",
"pcb_smtpad_474",
"pcb_smtpad_497",
"pcb_smtpad_499",
"pcb_smtpad_659",
"pcb_smtpad_663",
"pcb_smtpad_674",
"pcb_smtpad_675",
"pcb_smtpad_677",
"pcb_smtpad_679",
"pcb_smtpad_681",
"pcb_smtpad_683",
"pcb_smtpad_685",
"pcb_smtpad_687",
"pcb_smtpad_689",
"pcb_smtpad_691",
"pcb_smtpad_693",
"pcb_smtpad_695",
"pcb_smtpad_697",
"pcb_smtpad_699",
"pcb_smtpad_701",
"pcb_smtpad_703",
"pcb_smtpad_705",
"pcb_smtpad_707",
"pcb_smtpad_76",
"pcb_smtpad_77",
"pcb_smtpad_78",
"pcb_smtpad_79",
"pcb_smtpad_80",
"pcb_smtpad_81",
"pcb_smtpad_82",
"pcb_smtpad_905",
"pcb_smtpad_907",
"pcb_smtpad_909",
"pcb_smtpad_911",
"pcb_smtpad_913",
"pcb_smtpad_915",
"pcb_smtpad_917",
"pcb_smtpad_919",
"pcb_smtpad_921",
"pcb_smtpad_923",
"pcb_smtpad_925",
"pcb_smtpad_927",
"pcb_smtpad_929",
"pcb_smtpad_931",
"pcb_smtpad_933",
"pcb_smtpad_935",
"pcb_smtpad_937",
"pcb_smtpad_939",
"pcb_smtpad_941"
],
"required_terminals": [
"pcb_port_324",
"pcb_port_326",
"pcb_port_329",
"pcb_port_336",
"pcb_port_338",
"pcb_port_341",
"pcb_port_343",
"pcb_port_347",
"pcb_port_349",
"pcb_port_378",
"pcb_port_388",
"pcb_port_397",
"pcb_port_406",
"pcb_port_407",
"pcb_port_408",
"pcb_port_411",
"pcb_port_416",
"pcb_port_418",
"pcb_port_458",
"pcb_port_474",
"pcb_port_497",
"pcb_port_499",
"pcb_port_659",
"pcb_port_663",
"pcb_port_674",
"pcb_port_675",
"pcb_port_677",
"pcb_port_679",
"pcb_port_681",
"pcb_port_683",
"pcb_port_685",
"pcb_port_687",
"pcb_port_689",
"pcb_port_691",
"pcb_port_693",
"pcb_port_695",
"pcb_port_697",
"pcb_port_699",
"pcb_port_701",
"pcb_port_703",
"pcb_port_705",
"pcb_port_707",
"pcb_port_76",
"pcb_port_77",
"pcb_port_78",
"pcb_port_79",
"pcb_port_80",
"pcb_port_81",
"pcb_port_82",
"pcb_port_905",
"pcb_port_907",
"pcb_port_909",
"pcb_port_911",
"pcb_port_913",
"pcb_port_915",
"pcb_port_917",
"pcb_port_919",
"pcb_port_921",
"pcb_port_923",
"pcb_port_925",
"pcb_port_927",
"pcb_port_929",
"pcb_port_931",
"pcb_port_933",
"pcb_port_935",
"pcb_port_937",
"pcb_port_939",
"pcb_port_941"
]
},
{
"root": "83",
"nets": [],
"objects": [
"pcb_smtpad_83"
],
"required_terminals": []
},
{
"root": "13492",
"nets": [
"V3V3"
],
"objects": [
"baseline_closure_601df44b_C_IO1_0_pin1_existing",
"baseline_closure_bf77cf69_C_IO3_B_pin1_existing",
"baseline_closure_bf77cf69_J_MICROSD_4_tap0",
"baseline_closure_bf77cf69_J_MICROSD_4_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT0_pin2_tap0",
"baseline_closure_bf77cf69_R_BOOT0_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_BOOT14_pin2_tap0",
"baseline_closure_bf77cf69_R_BOOT14_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_EMU0_pin2_tap0",
"baseline_closure_bf77cf69_R_EMU0_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_PGOOD_RAW_pin2_tap0",
"baseline_closure_bf77cf69_R_PGOOD_RAW_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_PWR2_pin2_tap0",
"baseline_closure_bf77cf69_R_PWR2_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_PWR3_pin2_tap0",
"baseline_closure_bf77cf69_R_PWR3_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_PWR4_pin2_tap0",
"baseline_closure_bf77cf69_R_PWR4_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_PWR5_pin2_tap0",
"baseline_closure_bf77cf69_R_PWR5_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_PWR6_pin2_tap0",
"baseline_closure_bf77cf69_R_PWR6_pin2_tap0_via_0",
"baseline_closure_bf77cf69_R_TDI_pin2_tap0",
"baseline_closure_bf77cf69_R_TDI_pin2_tap0_via_0",
"baseline_closure_bf77cf69_TP_UART_4_1_existing",
"baseline_closure_bf77cf69_U_RESET_DELAY_5_tap0",
"baseline_closure_bf77cf69_U_RESET_DELAY_5_tap0_via_0",
"baseline_closure_cd4b9ff3_DCDC4_load_via_reposition",
"baseline_closure_cd4b9ff3_DCDC4_load_via_reposition_via_0",
"baseline_closure_cd4b9ff3_DCDC4_primary_PFI_corridor",
"baseline_closure_e5158c8d_R_SD_DAT2_pin1_tap0",
"baseline_closure_e5158c8d_R_SD_DAT2_pin1_tap0_via_0",
"baseline_closure_fcadd8db_C_PWR10_pin1_tap0",
"baseline_closure_fcadd8db_C_PWR10_pin1_tap0_via_0",
"baseline_closure_fcadd8db_DCDC4_HF",
"baseline_local_support_15",
"baseline_local_support_21",
"baseline_local_support_24",
"baseline_local_support_25",
"baseline_local_support_27",
"baseline_local_support_47",
"baseline_local_support_48",
"baseline_local_support_57",
"baseline_local_support_58",
"baseline_local_support_86",
"baseline_local_support_93",
"baseline_local_support_96",
"baseline_pcb_via_3",
"baseline_plane_tie_V3V3_9591af83_0",
"baseline_plane_tie_V3V3_9591af83_0_via",
"baseline_plane_tie_V3V3_9591af83_2",
"baseline_plane_tie_V3V3_9591af83_2_via",
"baseline_plane_tie_V3V3_9591af83_4",
"baseline_plane_tie_V3V3_9591af83_4_via",
"baseline_rail_region_V3V3_CPU_IO_bridge_2",
"baseline_rail_region_V3V3_bottom_distribution_0",
"baseline_rail_region_V3V3_bottom_distribution_53",
"baseline_rail_region_V3V3_bottom_distribution_60",
"baseline_rail_region_V3V3_bottom_distribution_61",
"baseline_rail_region_V3V3_bottom_distribution_65",
"baseline_reset_ijump_430571dc_10",
"baseline_support_escape_U1_E10",
"baseline_support_escape_U1_E11",
"baseline_support_escape_U1_E12",
"baseline_support_escape_U1_E13",
"baseline_support_escape_U1_F14",
"baseline_support_escape_U1_G14",
"baseline_support_escape_U1_H14",
"baseline_support_escape_U1_J14",
"baseline_support_escape_U1_K14",
"baseline_support_escape_U1_L14",
"baseline_support_escape_U1_N15",
"baseline_support_escape_U1_N5",
"baseline_support_escape_U1_P10",
"baseline_support_escape_U1_P11",
"baseline_support_escape_U1_P12",
"baseline_support_escape_U1_P13",
"baseline_support_escape_U1_P5",
"baseline_support_escape_U1_P6",
"baseline_support_escape_U1_P7",
"baseline_support_escape_U1_P8",
"baseline_support_escape_U1_R15",
"baseline_support_via_U1_E10",
"baseline_support_via_U1_E12",
"baseline_support_via_U1_E13",
"baseline_support_via_U1_F14",
"baseline_support_via_U1_G14",
"baseline_support_via_U1_H14",
"baseline_support_via_U1_J14",
"baseline_support_via_U1_K14",
"baseline_support_via_U1_L14",
"baseline_support_via_U1_N15",
"baseline_support_via_U1_P10",
"baseline_support_via_U1_P11",
"baseline_support_via_U1_P12",
"baseline_support_via_U1_P13",
"baseline_support_via_U1_P5",
"baseline_support_via_U1_P6",
"baseline_support_via_U1_P7",
"baseline_support_via_U1_R15",
"closure_ce831868_V3V3_carrier_0",
"closure_ce831868_V3V3_carrier_0_via",
"closure_ce831868_V3V3_carrier_0_via_0",
"closure_ce831868_V3V3_carrier_0_via_1",
"closure_ce831868_V3V3_carrier_3",
"d1_retained_V3V3_CPU_IO_east",
"dbg_pcb_smtpad_1",
"dbg_pcb_trace_1",
"hdmi_power_trace_final_003_boost_Cin",
"hdmi_power_trace_final_004_boost_EN",
"hdmi_power_trace_final_005_boost_MODE",
"hdmi_power_trace_final_022_LDO_Cin_top",
"hdmi_power_trace_final_023_LDO_Cin_bottom",
"hdmi_power_trace_final_113_V3V3_branch",
"hdmi_power_trace_final_113_V3V3_branch_via",
"hdmi_power_trace_final_114_V3V3_branch",
"hdmi_power_trace_final_114_V3V3_branch_via",
"hdmi_power_trace_final_115_V3V3_branch",
"hdmi_power_trace_final_116_V3V3_branch",
"hdmi_power_trace_final_117_V3V3_branch",
"hdmi_power_trace_final_117_V3V3_branch_via",
"hdmi_power_trace_final_118_V3V3_branch",
"hdmi_power_trace_final_118_V3V3_branch_via",
"hdmi_power_trace_final_119_V3V3_branch",
"hdmi_power_trace_final_120_V3V3_branch",
"hdmi_power_trace_final_121_V3V3_branch",
"hdmi_power_trace_final_122_V3V3_branch",
"hdmi_power_trace_final_122_V3V3_branch_via",
"hdmi_power_trace_final_123_V3V3_branch",
"hdmi_power_trace_final_124_V3V3_branch",
"hdmi_power_trace_final_125_V3V3_branch",
"hdmi_power_trace_final_126_V3V3_branch",
"hdmi_power_trace_final_126_V3V3_branch_via",
"hdmi_power_trace_final_127_V3V3_branch",
"hdmi_power_trace_final_128_V3V3_branch",
"hdmi_power_trace_final_129_V3V3_branch",
"hdmi_power_trace_final_129_V3V3_branch_via",
"hdmi_power_trace_final_130_V3V3_retained_plane",
"hdmi_power_trace_final_130_V3V3_retained_plane_via",
"hdmi_power_via_final_007",
"hdmi_power_via_final_116",
"hdmi_power_via_final_117",
"hdmi_power_via_final_118",
"hdmi_power_via_final_119",
"hdmi_power_via_final_120",
"hdmi_power_via_final_121",
"hdmi_power_via_final_122",
"hdmi_power_via_final_123",
"hdmi_power_via_final_124",
"hdmi_power_via_final_125",
"hdmi_power_via_final_126",
"hdmi_power_via_final_127",
"hdmi_power_via_final_128",
"local_bundle_J14_K14_power_strap",
"local_bundle_J15_K14_retained_fragment_0",
"pcb_smtpad_103",
"pcb_smtpad_121",
"pcb_smtpad_139",
"pcb_smtpad_166",
"pcb_smtpad_175",
"pcb_smtpad_184",
"pcb_smtpad_193",
"pcb_smtpad_202",
"pcb_smtpad_211",
"pcb_smtpad_220",
"pcb_smtpad_229",
"pcb_smtpad_239",
"pcb_smtpad_240",
"pcb_smtpad_241",
"pcb_smtpad_242",
"pcb_smtpad_243",
"pcb_smtpad_244",
"pcb_smtpad_264",
"pcb_smtpad_266",
"pcb_smtpad_434",
"pcb_smtpad_501",
"pcb_smtpad_503",
"pcb_smtpad_514",
"pcb_smtpad_516",
"pcb_smtpad_518",
"pcb_smtpad_520",
"pcb_smtpad_522",
"pcb_smtpad_587",
"pcb_smtpad_589",
"pcb_smtpad_591",
"pcb_smtpad_593",
"pcb_smtpad_595",
"pcb_smtpad_597",
"pcb_smtpad_599",
"pcb_smtpad_601",
"pcb_smtpad_603",
"pcb_smtpad_605",
"pcb_smtpad_607",
"pcb_smtpad_609",
"pcb_smtpad_611",
"pcb_smtpad_613",
"pcb_smtpad_615",
"pcb_smtpad_617",
"pcb_smtpad_619",
"pcb_smtpad_621",
"pcb_smtpad_623",
"pcb_smtpad_625",
"pcb_smtpad_627",
"pcb_smtpad_629",
"pcb_smtpad_645",
"pcb_smtpad_647",
"pcb_smtpad_710",
"pcb_smtpad_712",
"pcb_smtpad_714",
"pcb_smtpad_718",
"pcb_smtpad_738",
"pcb_smtpad_750",
"pcb_smtpad_761",
"pcb_smtpad_763",
"pcb_smtpad_765",
"pcb_smtpad_767",
"pcb_smtpad_769",
"pcb_smtpad_771",
"pcb_smtpad_773",
"pcb_smtpad_775",
"pcb_smtpad_796",
"pcb_smtpad_798",
"pcb_smtpad_800",
"pcb_smtpad_802",
"pcb_smtpad_84",
"pcb_smtpad_85",
"pcb_smtpad_867",
"pcb_smtpad_868",
"pcb_smtpad_871",
"pcb_smtpad_874",
"pcb_smtpad_904",
"pcb_smtpad_943",
"pcb_smtpad_945",
"pcb_smtpad_949",
"pcb_smtpad_hdmi_pcb_smtpad_101",
"pcb_smtpad_hdmi_pcb_smtpad_116",
"pcb_smtpad_hdmi_pcb_smtpad_120",
"pcb_smtpad_hdmi_pcb_smtpad_127",
"pcb_smtpad_hdmi_pcb_smtpad_130",
"pcb_smtpad_hdmi_pcb_smtpad_137",
"pcb_smtpad_hdmi_pcb_smtpad_141",
"pcb_smtpad_hdmi_pcb_smtpad_150",
"pcb_smtpad_hdmi_pcb_smtpad_151",
"pcb_smtpad_hdmi_pcb_smtpad_153",
"pcb_smtpad_hdmi_pcb_smtpad_155",
"pcb_smtpad_hdmi_pcb_smtpad_159",
"pcb_smtpad_hdmi_pcb_smtpad_258",
"pcb_smtpad_hdmi_pcb_smtpad_259",
"pcb_smtpad_hdmi_pcb_smtpad_260",
"pcb_smtpad_hdmi_pcb_smtpad_266",
"pcb_smtpad_hdmi_pcb_smtpad_272",
"pcb_smtpad_hdmi_pcb_smtpad_82",
"pg7_pcb_smtpad_11",
"pg7_pcb_smtpad_4",
"pg7_pcb_smtpad_7",
"proposed_D1_V3V3_P13_R15_feed_021"
],
"required_terminals": [
"dbg_pcb_port_1",
"pcb_port_103",
"pcb_port_121",
"pcb_port_139",
"pcb_port_166",
"pcb_port_175",
"pcb_port_184",
"pcb_port_193",
"pcb_port_202",
"pcb_port_211",
"pcb_port_220",
"pcb_port_229",
"pcb_port_239",
"pcb_port_240",
"pcb_port_241",
"pcb_port_242",
"pcb_port_243",
"pcb_port_244",
"pcb_port_264",
"pcb_port_266",
"pcb_port_434",
"pcb_port_501",
"pcb_port_503",
"pcb_port_514",
"pcb_port_516",
"pcb_port_518",
"pcb_port_520",
"pcb_port_522",
"pcb_port_587",
"pcb_port_589",
"pcb_port_591",
"pcb_port_593",
"pcb_port_595",
"pcb_port_597",
"pcb_port_599",
"pcb_port_601",
"pcb_port_603",
"pcb_port_605",
"pcb_port_607",
"pcb_port_609",
"pcb_port_611",
"pcb_port_613",
"pcb_port_615",
"pcb_port_617",
"pcb_port_619",
"pcb_port_621",
"pcb_port_623",
"pcb_port_625",
"pcb_port_627",
"pcb_port_629",
"pcb_port_645",
"pcb_port_647",
"pcb_port_710",
"pcb_port_712",
"pcb_port_714",
"pcb_port_718",
"pcb_port_738",
"pcb_port_750",
"pcb_port_761",
"pcb_port_763",
"pcb_port_765",
"pcb_port_767",
"pcb_port_769",
"pcb_port_771",
"pcb_port_773",
"pcb_port_775",
"pcb_port_800",
"pcb_port_802",
"pcb_port_804",
"pcb_port_806",
"pcb_port_84",
"pcb_port_85",
"pcb_port_871",
"pcb_port_872",
"pcb_port_875",
"pcb_port_878",
"pcb_port_904",
"pcb_port_943",
"pcb_port_945",
"pcb_port_949",
"pcb_port_hdmi_pcb_port_101",
"pcb_port_hdmi_pcb_port_116",
"pcb_port_hdmi_pcb_port_120",
"pcb_port_hdmi_pcb_port_127",
"pcb_port_hdmi_pcb_port_130",
"pcb_port_hdmi_pcb_port_137",
"pcb_port_hdmi_pcb_port_141",
"pcb_port_hdmi_pcb_port_150",
"pcb_port_hdmi_pcb_port_151",
"pcb_port_hdmi_pcb_port_153",
"pcb_port_hdmi_pcb_port_155",
"pcb_port_hdmi_pcb_port_159",
"pcb_port_hdmi_pcb_port_262",
"pcb_port_hdmi_pcb_port_263",
"pcb_port_hdmi_pcb_port_264",
"pcb_port_hdmi_pcb_port_270",
"pcb_port_hdmi_pcb_port_276",
"pcb_port_hdmi_pcb_port_82",
"pg7_pcb_port_11",
"pg7_pcb_port_4",
"pg7_pcb_port_7"
]
},
{
"root": "86",
"nets": [
"HDMI_HSYNC"
],
"objects": [
"pcb_smtpad_86"
],
"required_terminals": [
"pcb_port_86"
]
},
{
"root": "13575",
"nets": [
"SYSBOOT15"
],
"objects": [
"baseline_support_via_U1_T5",
"hdmi_retained_boot_SYSBOOT15_0",
"hdmi_retained_boot_SYSBOOT15_1",
"pcb_smtpad_739",
"pcb_smtpad_87"
],
"required_terminals": [
"pcb_port_739",
"pcb_port_87"
]
},
{
"root": "88",
"nets": [
"HDMI_VSYNC"
],
"objects": [
"pcb_smtpad_88"
],
"required_terminals": [
"pcb_port_88"
]
},
{
"root": "89",
"nets": [
"LCD_PCLK"
],
"objects": [
"pcb_smtpad_89"
],
"required_terminals": [
"pcb_port_89"
]
},
{
"root": "90",
"nets": [],
"objects": [
"pcb_smtpad_90"
],
"required_terminals": []
},
{
"root": "12773",
"nets": [
"PMIC_POWER_EN"
],
"objects": [
"baseline_closure_24237100_U_PMIC_46_settled_root",
"baseline_closure_24237100_U_PMIC_46_settled_root_via_0",
"baseline_closure_7e11b17a_PMIC_POWER_EN_escape_1_2",
"baseline_closure_7e11b17a_PMIC_POWER_EN_escape_1_2_via",
"baseline_closure_7e11b17a_PMIC_POWER_EN_escape_1_2_via_0",
"baseline_closure_a7fb5d8f_PMIC_POWER_EN_short_spare_layer_trunk",
"baseline_support_escape_U1_C6",
"baseline_support_via_U1_C6",
"pcb_smtpad_465",
"pcb_smtpad_537",
"pcb_smtpad_92"
],
"required_terminals": [
"pcb_port_465",
"pcb_port_537",
"pcb_port_92"
]
},
{
"root": "12685",
"nets": [
"CAP_VDD_RTC"
],
"objects": [
"baseline_closure_e3a22c67_C_RTC_LDO_local_driver",
"baseline_support_escape_U1_D6",
"baseline_support_via_U1_D6",
"pcb_smtpad_533",
"pcb_smtpad_93"
],
"required_terminals": [
"pcb_port_533",
"pcb_port_93"
]
},
{
"root": "12698",
"nets": [
"V1V8"
],
"objects": [
"baseline_closure_170d9ee6_C_VDDS_RTC_repositioned_supply",
"baseline_closure_26176be2_V1V8_CPU_power_group_0_2",
"baseline_closure_26176be2_V1V8_CPU_power_group_0_5",
"baseline_closure_5cd77670_V1V8_short_contact_1",
"baseline_closure_a3d5dbf8_C_VDDS_1_pin1_actual_rail_feed",
"baseline_closure_a3d5dbf8_C_VDDS_1_pin1_actual_rail_feed_via",
"baseline_closure_a3d5dbf8_C_VDDS_1_pin1_actual_rail_feed_via_0",
"baseline_closure_a3d5dbf8_C_VDDS_2_pin1_actual_rail_feed",
"baseline_closure_a3d5dbf8_C_VDDS_2_pin1_actual_rail_feed_via",
"baseline_closure_a3d5dbf8_C_VDDS_2_pin1_actual_rail_feed_via_0",
"baseline_closure_bf77cf69_C_CLOCK_GATE_pin1_existing",
"baseline_closure_bf77cf69_C_SOC_CLOCK_pin1_tap0",
"baseline_closure_bf77cf69_C_SOC_CLOCK_pin1_tap0_via_0",
"baseline_closure_bf77cf69_C_SRAM_CORE_0_pin1_tap0",
"baseline_closure_bf77cf69_C_SRAM_CORE_0_pin1_tap0_via_0",
"baseline_closure_bf77cf69_C_SRAM_CORE_B_pin1_existing",
"baseline_closure_bf77cf69_C_SRAM_MPU_0_pin1_tap0",
"baseline_closure_bf77cf69_C_SRAM_MPU_0_pin1_tap0_via_0",
"baseline_closure_bf77cf69_C_SRAM_MPU_B_pin1_existing",
"baseline_closure_bf77cf69_C_VDDA1P8V_USB0_pin1_tap0",
"baseline_closure_bf77cf69_C_VDDA1P8V_USB0_pin1_tap0_via_0",
"baseline_closure_bf77cf69_C_VDDS_B_pin1_tap0",
"baseline_closure_bf77cf69_C_VDDS_B_pin1_tap0_via_0",
"baseline_closure_bf77cf69_U_CLOCK_GATE_5_existing",
"baseline_closure_bf77cf69_U_RTC_POR_GATE_5_tap0",
"baseline_closure_bf77cf69_U_RTC_POR_GATE_5_tap0_via_0",
"baseline_closure_bf77cf69_Y_SOC_4_tap0",
"baseline_closure_bf77cf69_Y_SOC_4_tap0_via_0",
"baseline_closure_f87fbb58_C_VDDS_3_repositioned_supply",
"baseline_closure_fcadd8db_C_PWR12_B_pin1_tap0",
"baseline_closure_fcadd8db_C_PWR12_B_pin1_tap0_via_0",
"baseline_compact_ldo_685bae96_cap",
"baseline_compact_ldo_685bae96_root",
"baseline_compact_ldo_685bae96_via",
"baseline_local_support_20",
"baseline_local_support_30",
"baseline_local_support_39",
"baseline_pcb_via_2",
"baseline_plane_tie_V1V8_5209b9ca_0",
"baseline_plane_tie_V1V8_5209b9ca_0_via",
"baseline_plane_tie_V1V8_5209b9ca_2",
"baseline_plane_tie_V1V8_5209b9ca_2_via",
"baseline_plane_tie_V1V8_5209b9ca_4",
"baseline_plane_tie_V1V8_5209b9ca_4_via",
"baseline_plane_tie_V1V8_5209b9ca_6",
"baseline_plane_tie_V1V8_5209b9ca_6_via",
"baseline_plane_tie_V1V8_5209b9ca_8",
"baseline_plane_tie_V1V8_5209b9ca_8_via",
"baseline_rail_region_V1V8_distribution_0",
"baseline_rail_region_V1V8_distribution_24",
"baseline_rail_region_V1V8_distribution_7",
"baseline_reset_ijump_430571dc_2",
"baseline_reset_ijump_430571dc_3",
"baseline_reset_ijump_430571dc_5",
"baseline_reset_ijump_430571dc_6",
"baseline_support_escape_U1_D10",
"baseline_support_escape_U1_D7",
"baseline_support_escape_U1_E14",
"baseline_support_escape_U1_E6",
"baseline_support_escape_U1_E7",
"baseline_support_escape_U1_E9",
"baseline_support_escape_U1_F9",
"baseline_support_escape_U1_H15",
"baseline_support_escape_U1_K13",
"baseline_support_escape_U1_N16",
"baseline_support_escape_U1_N6",
"baseline_support_escape_U1_P14",
"baseline_support_escape_U1_P9",
"baseline_support_escape_U1_R10",
"baseline_support_escape_U1_R11",
"baseline_support_escape_U1_R16",
"baseline_support_via_U1_D10",
"baseline_support_via_U1_E14",
"baseline_support_via_U1_E6",
"baseline_support_via_U1_E7",
"baseline_support_via_U1_F9",
"baseline_support_via_U1_H15",
"baseline_support_via_U1_K13",
"baseline_support_via_U1_N16",
"baseline_support_via_U1_N6",
"baseline_support_via_U1_P14",
"baseline_support_via_U1_P9",
"baseline_support_via_U1_R10",
"baseline_support_via_U1_R11",
"baseline_support_via_U1_R16",
"dbg_pcb_smtpad_2",
"dbg_pcb_trace_2",
"pcb_smtpad_102",
"pcb_smtpad_111",
"pcb_smtpad_112",
"pcb_smtpad_148",
"pcb_smtpad_149",
"pcb_smtpad_157",
"pcb_smtpad_165",
"pcb_smtpad_176",
"pcb_smtpad_194",
"pcb_smtpad_225",
"pcb_smtpad_238",
"pcb_smtpad_247",
"pcb_smtpad_259",
"pcb_smtpad_282",
"pcb_smtpad_284",
"pcb_smtpad_423",
"pcb_smtpad_505",
"pcb_smtpad_507",
"pcb_smtpad_529",
"pcb_smtpad_569",
"pcb_smtpad_571",
"pcb_smtpad_573",
"pcb_smtpad_575",
"pcb_smtpad_577",
"pcb_smtpad_579",
"pcb_smtpad_581",
"pcb_smtpad_583",
"pcb_smtpad_585",
"pcb_smtpad_631",
"pcb_smtpad_633",
"pcb_smtpad_635",
"pcb_smtpad_637",
"pcb_smtpad_639",
"pcb_smtpad_641",
"pcb_smtpad_643",
"pcb_smtpad_744",
"pcb_smtpad_745",
"pcb_smtpad_862",
"pcb_smtpad_869",
"pcb_smtpad_879",
"pcb_smtpad_881",
"pcb_smtpad_896",
"pcb_smtpad_897",
"pcb_smtpad_899",
"pcb_smtpad_94",
"short_tx_return_C_RMII_RETURN_A_V1V8",
"short_tx_return_C_RMII_RETURN_A_V1V8_via",
"short_tx_return_C_RMII_RETURN_B_V1V8",
"short_tx_return_C_RMII_RETURN_B_V1V8_via",
"short_tx_return_C_RMII_RETURN_C_V1V8",
"short_tx_return_C_RMII_RETURN_C_V1V8_via",
"short_tx_return_C_RMII_RETURN_D_V1V8",
"short_tx_return_C_RMII_RETURN_D_V1V8_via",
"short_tx_return_pcb_smtpad_1347",
"short_tx_return_pcb_smtpad_1349",
"short_tx_return_pcb_smtpad_1351",
"short_tx_return_pcb_smtpad_1353"
],
"required_terminals": [
"dbg_pcb_port_2",
"pcb_port_102",
"pcb_port_111",
"pcb_port_112",
"pcb_port_148",
"pcb_port_149",
"pcb_port_157",
"pcb_port_165",
"pcb_port_176",
"pcb_port_194",
"pcb_port_225",
"pcb_port_238",
"pcb_port_247",
"pcb_port_259",
"pcb_port_282",
"pcb_port_284",
"pcb_port_423",
"pcb_port_505",
"pcb_port_507",
"pcb_port_529",
"pcb_port_569",
"pcb_port_571",
"pcb_port_573",
"pcb_port_575",
"pcb_port_577",
"pcb_port_579",
"pcb_port_581",
"pcb_port_583",
"pcb_port_585",
"pcb_port_631",
"pcb_port_633",
"pcb_port_635",
"pcb_port_637",
"pcb_port_639",
"pcb_port_641",
"pcb_port_643",
"pcb_port_744",
"pcb_port_745",
"pcb_port_866",
"pcb_port_873",
"pcb_port_883",
"pcb_port_885",
"pcb_port_896",
"pcb_port_897",
"pcb_port_899",
"pcb_port_94",
"short_tx_return_pcb_port_1359",
"short_tx_return_pcb_port_1361",
"short_tx_return_pcb_port_1363",
"short_tx_return_pcb_port_1365"
]
},
{
"root": "13487",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_bulk_branch_f8da9606_C_PWR7",
"baseline_bulk_branch_f8da9606_C_PWR7_B",
"baseline_closure_4bf9f1fb_VDD_CORE_CPU_power_group_1_0",
"baseline_closure_4bf9f1fb_VDD_CORE_CPU_power_group_2_1",
"baseline_north_feedback_17787539_VDD_CORE",
"baseline_north_feedback_17787539_VDD_CORE_via",
"baseline_pcb_via_0",
"baseline_processor_feed_60aa5887_0_load_VDD_CORE",
"baseline_processor_feed_60aa5887_0_load_VDD_CORE_via",
"baseline_processor_feed_60aa5887_1_load_VDD_CORE",
"baseline_processor_feed_60aa5887_1_load_VDD_CORE_via",
"baseline_processor_feed_60aa5887_2_load_VDD_CORE",
"baseline_processor_feed_60aa5887_2_load_VDD_CORE_via",
"baseline_rail_region_CORE_backside_decoupling_bank_1",
"baseline_rail_region_CORE_distribution_0",
"baseline_rail_region_CORE_distribution_2",
"baseline_rail_region_CORE_distribution_3",
"baseline_support_escape_U1_F6",
"baseline_support_escape_U1_F7",
"baseline_support_escape_U1_G10",
"baseline_support_escape_U1_G6",
"baseline_support_escape_U1_G7",
"baseline_support_escape_U1_H11",
"baseline_support_escape_U1_J12",
"baseline_support_escape_U1_K12",
"baseline_support_escape_U1_K6",
"baseline_support_escape_U1_K8",
"baseline_support_escape_U1_L6",
"baseline_support_escape_U1_L7",
"baseline_support_escape_U1_L8",
"baseline_support_escape_U1_L9",
"baseline_support_escape_U1_M11",
"baseline_support_escape_U1_M13",
"baseline_support_escape_U1_N12",
"baseline_support_escape_U1_N13",
"baseline_support_escape_U1_N8",
"baseline_support_escape_U1_N9",
"baseline_support_via_U1_F6",
"baseline_support_via_U1_G10",
"baseline_support_via_U1_G6",
"baseline_support_via_U1_G7",
"baseline_support_via_U1_H11",
"baseline_support_via_U1_J12",
"baseline_support_via_U1_K12",
"baseline_support_via_U1_K6",
"baseline_support_via_U1_K8",
"baseline_support_via_U1_L6",
"baseline_support_via_U1_L7",
"baseline_support_via_U1_L8",
"baseline_support_via_U1_M11",
"baseline_support_via_U1_M13",
"baseline_support_via_U1_N12",
"baseline_support_via_U1_N13",
"baseline_support_via_U1_N8",
"core_replan_CORE2_supply_feed",
"d0_retained_VDD_CORE_east_bank",
"held_CORE4_nearby_bank_feed",
"held_CORE4_nearby_bank_feed_via",
"pcb_smtpad_100",
"pcb_smtpad_113",
"pcb_smtpad_114",
"pcb_smtpad_118",
"pcb_smtpad_135",
"pcb_smtpad_136",
"pcb_smtpad_138",
"pcb_smtpad_154",
"pcb_smtpad_156",
"pcb_smtpad_168",
"pcb_smtpad_187",
"pcb_smtpad_191",
"pcb_smtpad_206",
"pcb_smtpad_207",
"pcb_smtpad_210",
"pcb_smtpad_227",
"pcb_smtpad_228",
"pcb_smtpad_466",
"pcb_smtpad_470",
"pcb_smtpad_489",
"pcb_smtpad_491",
"pcb_smtpad_539",
"pcb_smtpad_541",
"pcb_smtpad_543",
"pcb_smtpad_545",
"pcb_smtpad_547",
"pcb_smtpad_549",
"pcb_smtpad_551",
"pcb_smtpad_553",
"pcb_smtpad_555",
"pcb_smtpad_95",
"pcb_smtpad_96",
"pcb_smtpad_99"
],
"required_terminals": [
"pcb_port_100",
"pcb_port_113",
"pcb_port_114",
"pcb_port_118",
"pcb_port_135",
"pcb_port_136",
"pcb_port_138",
"pcb_port_154",
"pcb_port_156",
"pcb_port_168",
"pcb_port_187",
"pcb_port_191",
"pcb_port_206",
"pcb_port_207",
"pcb_port_210",
"pcb_port_227",
"pcb_port_228",
"pcb_port_466",
"pcb_port_470",
"pcb_port_489",
"pcb_port_491",
"pcb_port_539",
"pcb_port_541",
"pcb_port_543",
"pcb_port_545",
"pcb_port_547",
"pcb_port_549",
"pcb_port_551",
"pcb_port_553",
"pcb_port_555",
"pcb_port_95",
"pcb_port_96",
"pcb_port_99"
]
},
{
"root": "104",
"nets": [
"LCD_DE"
],
"objects": [
"pcb_smtpad_104"
],
"required_terminals": [
"pcb_port_104"
]
},
{
"root": "105",
"nets": [],
"objects": [
"pcb_smtpad_105"
],
"required_terminals": []
},
{
"root": "106",
"nets": [],
"objects": [
"pcb_smtpad_106"
],
"required_terminals": []
},
{
"root": "107",
"nets": [],
"objects": [
"pcb_smtpad_107"
],
"required_terminals": []
},
{
"root": "122",
"nets": [],
"objects": [
"pcb_smtpad_122"
],
"required_terminals": []
},
{
"root": "123",
"nets": [],
"objects": [
"pcb_smtpad_123"
],
"required_terminals": []
},
{
"root": "124",
"nets": [],
"objects": [
"pcb_smtpad_124"
],
"required_terminals": []
},
{
"root": "125",
"nets": [],
"objects": [
"pcb_smtpad_125"
],
"required_terminals": []
},
{
"root": "140",
"nets": [],
"objects": [
"pcb_smtpad_140"
],
"required_terminals": []
},
{
"root": "141",
"nets": [],
"objects": [
"pcb_smtpad_141"
],
"required_terminals": []
},
{
"root": "142",
"nets": [],
"objects": [
"pcb_smtpad_142"
],
"required_terminals": []
},
{
"root": "12257",
"nets": [
"PMIC_INT_N"
],
"objects": [
"baseline_closure_847f7e5f_PMIC_INT_N_group_0_1",
"baseline_reset_ijump_6029a795_4",
"baseline_reset_ijump_6029a795_4_via",
"baseline_reset_ijump_6029a795_4_via_11",
"baseline_reset_ijump_6029a795_4_via_21",
"baseline_reset_ijump_6029a795_4_via_23",
"baseline_reset_ijump_6029a795_4_via_7",
"baseline_support_escape_U1_V8",
"baseline_support_via_U1_V8",
"pcb_smtpad_143",
"pcb_smtpad_464",
"pcb_smtpad_517"
],
"required_terminals": [
"pcb_port_143",
"pcb_port_464",
"pcb_port_517"
]
},
{
"root": "12748",
"nets": [
"CAP_VDD_SRAM_CORE"
],
"objects": [
"baseline_closure_f3643d14_C_CAP_VDD_SRAM_CORE_driver",
"baseline_support_escape_U1_D9",
"baseline_support_via_U1_D9",
"pcb_smtpad_147",
"pcb_smtpad_649"
],
"required_terminals": [
"pcb_port_147",
"pcb_port_649"
]
},
{
"root": "158",
"nets": [],
"objects": [
"pcb_smtpad_158"
],
"required_terminals": []
},
{
"root": "159",
"nets": [],
"objects": [
"pcb_smtpad_159"
],
"required_terminals": []
},
{
"root": "160",
"nets": [],
"objects": [
"pcb_smtpad_160"
],
"required_terminals": []
},
{
"root": "161",
"nets": [],
"objects": [
"pcb_smtpad_161"
],
"required_terminals": []
},
{
"root": "12476",
"nets": [
"WARMRST_N"
],
"objects": [
"baseline_closure_847f7e5f_WARMRST_N_group_0_1",
"baseline_closure_847f7e5f_WARMRST_N_group_0_1_via",
"baseline_closure_847f7e5f_WARMRST_N_group_0_1_via_0",
"baseline_reset_ijump_6029a795_5",
"baseline_support_escape_U1_A10",
"baseline_support_via_U1_A10",
"hdmi_low_speed_WARMRST_N_0",
"pcb_smtpad_162",
"pcb_smtpad_445",
"pcb_smtpad_515",
"pcb_smtpad_hdmi_pcb_smtpad_147"
],
"required_terminals": [
"pcb_port_162",
"pcb_port_445",
"pcb_port_515",
"pcb_port_hdmi_pcb_port_147"
]
},
{
"root": "12008",
"nets": [
"TRST_N"
],
"objects": [
"baseline_reset_ijump_6a4e354b_37",
"baseline_reset_ijump_6a4e354b_37_via",
"baseline_reset_ijump_6a4e354b_37_via_15",
"baseline_reset_ijump_6a4e354b_37_via_21",
"baseline_reset_ijump_6a4e354b_37_via_27",
"baseline_reset_ijump_6a4e354b_37_via_33",
"baseline_reset_ijump_6a4e354b_37_via_35",
"baseline_reset_ijump_6a4e354b_37_via_7",
"baseline_support_escape_U1_B10",
"baseline_support_via_U1_B10",
"pcb_smtpad_163",
"pcb_smtpad_793"
],
"required_terminals": [
"pcb_port_163",
"pcb_port_797"
]
},
{
"root": "12742",
"nets": [
"CAP_VBB_MPU"
],
"objects": [
"baseline_closure_baf2699b_C_CAP_VBB_MPU_local_driver",
"baseline_closure_baf2699b_C_CAP_VBB_MPU_local_driver_via",
"baseline_closure_baf2699b_C_CAP_VBB_MPU_local_driver_via_0",
"baseline_support_escape_U1_C10",
"baseline_support_via_U1_C10",
"pcb_smtpad_164",
"pcb_smtpad_653"
],
"required_terminals": [
"pcb_port_164",
"pcb_port_653"
]
},
{
"root": "177",
"nets": [
"HDMI_RGB_D22"
],
"objects": [
"pcb_smtpad_177"
],
"required_terminals": [
"pcb_port_177"
]
},
{
"root": "178",
"nets": [
"HDMI_RGB_D23"
],
"objects": [
"pcb_smtpad_178"
],
"required_terminals": [
"pcb_port_178"
]
},
{
"root": "12481",
"nets": [
"SOC_CLK24"
],
"objects": [
"baseline_closure_847f7e5f_SOC_CLK24_group_0_1",
"baseline_closure_847f7e5f_SOC_CLK24_group_0_1_via",
"baseline_closure_847f7e5f_SOC_CLK24_group_0_1_via_0",
"baseline_support_escape_U1_V10",
"baseline_support_via_U1_V10",
"pcb_smtpad_179",
"pcb_smtpad_743"
],
"required_terminals": [
"pcb_port_179",
"pcb_port_743"
]
},
{
"root": "3126",
"nets": [
"TDO"
],
"objects": [
"baseline_support_escape_U1_A11",
"baseline_support_via_U1_A11",
"pcb_smtpad_180"
],
"required_terminals": [
"pcb_port_180"
]
},
{
"root": "12222",
"nets": [
"TDI"
],
"objects": [
"baseline_reset_ijump_6029a795_1",
"baseline_reset_ijump_6029a795_1_via",
"baseline_reset_ijump_6029a795_1_via_14",
"baseline_reset_ijump_6029a795_1_via_8",
"baseline_support_escape_U1_B11",
"baseline_support_via_U1_B11",
"pcb_smtpad_181",
"pcb_smtpad_797"
],
"required_terminals": [
"pcb_port_181",
"pcb_port_801"
]
},
{
"root": "12501",
"nets": [
"TMS"
],
"objects": [
"baseline_closure_847f7e5f_TMS_group_0_1",
"baseline_closure_847f7e5f_TMS_group_0_1_via",
"baseline_closure_847f7e5f_TMS_group_0_1_via_0",
"baseline_support_escape_U1_C11",
"baseline_support_via_U1_C11",
"pcb_smtpad_182",
"pcb_smtpad_795"
],
"required_terminals": [
"pcb_port_182",
"pcb_port_799"
]
},
{
"root": "12750",
"nets": [
"CAP_VDD_SRAM_MPU"
],
"objects": [
"baseline_closure_f3643d14_C_CAP_VDD_SRAM_MPU_driver",
"baseline_closure_f3643d14_C_CAP_VDD_SRAM_MPU_driver_via",
"baseline_closure_f3643d14_C_CAP_VDD_SRAM_MPU_driver_via_0",
"baseline_support_escape_U1_D11",
"baseline_support_via_U1_D11",
"pcb_smtpad_183",
"pcb_smtpad_651"
],
"required_terminals": [
"pcb_port_183",
"pcb_port_651"
]
},
{
"root": "195",
"nets": [
"HDMI_RGB_D21"
],
"objects": [
"pcb_smtpad_195"
],
"required_terminals": [
"pcb_port_195"
]
},
{
"root": "196",
"nets": [],
"objects": [
"pcb_smtpad_196"
],
"required_terminals": []
},
{
"root": "3158",
"nets": [
"TCK"
],
"objects": [
"baseline_support_escape_U1_A12",
"baseline_support_via_U1_A12",
"pcb_smtpad_198"
],
"required_terminals": [
"pcb_port_198"
]
},
{
"root": "199",
"nets": [],
"objects": [
"pcb_smtpad_199"
],
"required_terminals": []
},
{
"root": "200",
"nets": [],
"objects": [
"pcb_smtpad_200"
],
"required_terminals": []
},
{
"root": "201",
"nets": [],
"objects": [
"pcb_smtpad_201"
],
"required_terminals": []
},
{
"root": "212",
"nets": [
"HDMI_RGB_D18"
],
"objects": [
"pcb_smtpad_212"
],
"required_terminals": [
"pcb_port_212"
]
},
{
"root": "213",
"nets": [
"HDMI_RGB_D19"
],
"objects": [
"pcb_smtpad_213"
],
"required_terminals": [
"pcb_port_213"
]
},
{
"root": "214",
"nets": [
"HDMI_RGB_D20"
],
"objects": [
"pcb_smtpad_214"
],
"required_terminals": [
"pcb_port_214"
]
},
{
"root": "215",
"nets": [],
"objects": [
"pcb_smtpad_215"
],
"required_terminals": []
},
{
"root": "216",
"nets": [],
"objects": [
"pcb_smtpad_216"
],
"required_terminals": []
},
{
"root": "217",
"nets": [],
"objects": [
"pcb_smtpad_217"
],
"required_terminals": []
},
{
"root": "218",
"nets": [],
"objects": [
"pcb_smtpad_218"
],
"required_terminals": []
},
{
"root": "219",
"nets": [],
"objects": [
"pcb_smtpad_219"
],
"required_terminals": []
},
{
"root": "230",
"nets": [],
"objects": [
"pcb_smtpad_230"
],
"required_terminals": []
},
{
"root": "231",
"nets": [],
"objects": [
"pcb_smtpad_231"
],
"required_terminals": []
},
{
"root": "232",
"nets": [
"HDMI_RGB_D16"
],
"objects": [
"pcb_smtpad_232"
],
"required_terminals": [
"pcb_port_232"
]
},
{
"root": "13849",
"nets": [
"HDMI_RGB_D17"
],
"objects": [
"hdmi_rgb_source_HDMI_RGB_D17",
"pcb_smtpad_233",
"pcb_smtpad_hdmi_pcb_smtpad_203"
],
"required_terminals": [
"pcb_port_233",
"pcb_port_hdmi_pcb_port_207"
]
},
{
"root": "234",
"nets": [],
"objects": [
"pcb_smtpad_234"
],
"required_terminals": []
},
{
"root": "12192",
"nets": [
"EMU1"
],
"objects": [
"baseline_reset_ijump_c9eda02b_5",
"baseline_reset_ijump_c9eda02b_5_via",
"baseline_reset_ijump_c9eda02b_5_via_13",
"baseline_reset_ijump_c9eda02b_5_via_9",
"baseline_support_escape_U1_B14",
"baseline_support_via_U1_B14",
"pcb_smtpad_235",
"pcb_smtpad_801"
],
"required_terminals": [
"pcb_port_235",
"pcb_port_805"
]
},
{
"root": "12238",
"nets": [
"EMU0"
],
"objects": [
"baseline_reset_ijump_6029a795_3",
"baseline_reset_ijump_6029a795_3_via",
"baseline_reset_ijump_6029a795_3_via_3",
"baseline_reset_ijump_6029a795_3_via_7",
"baseline_support_escape_U1_C14",
"baseline_support_via_U1_C14",
"pcb_smtpad_236",
"pcb_smtpad_799"
],
"required_terminals": [
"pcb_port_236",
"pcb_port_803"
]
},
{
"root": "237",
"nets": [],
"objects": [
"pcb_smtpad_237"
],
"required_terminals": []
},
{
"root": "248",
"nets": [],
"objects": [
"pcb_smtpad_248"
],
"required_terminals": []
},
{
"root": "249",
"nets": [],
"objects": [
"pcb_smtpad_249"
],
"required_terminals": []
},
{
"root": "250",
"nets": [],
"objects": [
"pcb_smtpad_250"
],
"required_terminals": []
},
{
"root": "251",
"nets": [],
"objects": [
"pcb_smtpad_251"
],
"required_terminals": []
},
{
"root": "252",
"nets": [],
"objects": [
"pcb_smtpad_252"
],
"required_terminals": []
},
{
"root": "804",
"nets": [
"PWRONRST_N"
],
"objects": [
"baseline_reset_ijump_0",
"baseline_reset_ijump_3d12ab20_0",
"baseline_reset_ijump_f8b6f07c_4",
"baseline_support_escape_U1_B15",
"baseline_support_via_U1_B15",
"closure_0859d6ad_LCD_local_escape_PWRONRST_N",
"closure_0859d6ad_LCD_local_escape_PWRONRST_N_via_0",
"closure_88c738dc_PWRONRST_N_cpu_surface_1",
"closure_be1cfec0_two_layer_PWRONRST_N",
"closure_be1cfec0_two_layer_PWRONRST_N_via",
"closure_be1cfec0_two_layer_PWRONRST_N_via_0",
"pcb_smtpad_1036",
"pcb_smtpad_1270",
"pcb_smtpad_253",
"pcb_smtpad_513",
"pcb_smtpad_803",
"pcb_smtpad_804",
"pcb_smtpad_863"
],
"required_terminals": [
"pcb_port_1036",
"pcb_port_1282",
"pcb_port_253",
"pcb_port_513",
"pcb_port_807",
"pcb_port_867"
]
},
{
"root": "254",
"nets": [],
"objects": [
"pcb_smtpad_254"
],
"required_terminals": []
},
{
"root": "255",
"nets": [],
"objects": [
"pcb_smtpad_255"
],
"required_terminals": []
},
{
"root": "12083",
"nets": [
"UART0_RX"
],
"objects": [
"baseline_reset_ijump_09b69059_4",
"baseline_reset_ijump_09b69059_4_via",
"baseline_reset_ijump_09b69059_4_via_8",
"baseline_support_escape_U1_E15",
"baseline_support_via_U1_E15",
"pcb_smtpad_256",
"pcb_smtpad_903"
],
"required_terminals": [
"pcb_port_256",
"pcb_port_903"
]
},
{
"root": "257",
"nets": [],
"objects": [
"pcb_smtpad_257"
],
"required_terminals": []
},
{
"root": "12115",
"nets": [
"MMC0_DAT1"
],
"objects": [
"baseline_reset_ijump_58fa5da9_3",
"baseline_reset_ijump_58fa5da9_3_via",
"baseline_reset_ijump_58fa5da9_3_via_14",
"baseline_reset_ijump_58fa5da9_3_via_18",
"baseline_reset_ijump_8b723cc1_4",
"baseline_reset_ijump_8b723cc1_4_via",
"baseline_reset_ijump_8b723cc1_4_via_12",
"baseline_reset_ijump_8b723cc1_4_via_5",
"baseline_support_escape_U1_G15",
"baseline_support_via_U1_G15",
"pcb_smtpad_258",
"pcb_smtpad_754",
"pcb_smtpad_766"
],
"required_terminals": [
"pcb_port_258",
"pcb_port_754",
"pcb_port_766"
]
},
{
"root": "13398",
"nets": [
"RMII1_RX_ER"
],
"objects": [
"core_replan_J15_escape",
"core_replan_J15_via",
"held_RX_ER_current_v2_trunk",
"held_RX_ER_current_v2_trunk_via",
"held_RX_ER_current_v2_trunk_via_0",
"held_RX_ER_current_v2_trunk_via_1",
"held_RX_ER_current_v2_trunk_via_2",
"held_RX_ER_current_v2_trunk_via_3",
"held_RX_ER_current_v2_trunk_via_4",
"held_RX_ER_current_v2_trunk_via_5",
"held_RX_ER_current_v2_trunk_via_6",
"local_bundle_J15_continuous_egress",
"local_bundle_J15_west_transition",
"pcb_smtpad_1283",
"pcb_smtpad_260",
"proposal_receiver_RMII1_RX_ER_top",
"proposal_receiver_RMII1_RX_ER_via",
"receiver_joint_RMII1_RX_ER_eastern_bridge",
"receiver_joint_RMII1_RX_ER_eastern_bridge_via",
"receiver_joint_RMII1_RX_ER_eastern_bridge_via_0",
"receiver_joint_RMII1_RX_ER_eastern_bridge_via_1"
],
"required_terminals": [
"pcb_port_1295",
"pcb_port_260"
]
},
{
"root": "261",
"nets": [],
"objects": [
"pcb_smtpad_261"
],
"required_terminals": []
},
{
"root": "13416",
"nets": [
"RMII1_RXD1"
],
"objects": [
"core_replan_L15_escape",
"core_replan_L15_via",
"held_RXD1_source_and_eastern_trunk",
"held_RXD1_source_and_eastern_trunk_via",
"held_RXD1_source_and_eastern_trunk_via_0",
"held_RXD1_source_and_eastern_trunk_via_1",
"held_RXD1_source_and_eastern_trunk_via_2",
"held_RXD1_source_and_eastern_trunk_via_3",
"pcb_smtpad_1281",
"pcb_smtpad_262",
"proposal_receiver_RMII1_RXD1_top",
"proposal_receiver_RMII1_RXD1_via",
"receiver_joint_RMII1_RXD1_eastern_bridge",
"receiver_joint_RMII1_RXD1_eastern_bridge_via",
"receiver_joint_RMII1_RXD1_eastern_bridge_via_0",
"receiver_joint_RMII1_RXD1_eastern_bridge_via_1"
],
"required_terminals": [
"pcb_port_1293",
"pcb_port_262"
]
},
{
"root": "263",
"nets": [],
"objects": [
"pcb_smtpad_263"
],
"required_terminals": []
},
{
"root": "265",
"nets": [],
"objects": [
"pcb_smtpad_265"
],
"required_terminals": []
},
{
"root": "267",
"nets": [],
"objects": [
"pcb_smtpad_267"
],
"required_terminals": []
},
{
"root": "268",
"nets": [],
"objects": [
"pcb_smtpad_268"
],
"required_terminals": []
},
{
"root": "269",
"nets": [],
"objects": [
"pcb_smtpad_269"
],
"required_terminals": []
},
{
"root": "270",
"nets": [],
"objects": [
"pcb_smtpad_270"
],
"required_terminals": []
},
{
"root": "271",
"nets": [],
"objects": [
"pcb_smtpad_271"
],
"required_terminals": []
},
{
"root": "13591",
"nets": [
"I2C0_SCL"
],
"objects": [
"baseline_closure_24237100_U_PMIC_3_settled_root",
"baseline_closure_24237100_U_PMIC_3_settled_root_via_0",
"baseline_closure_9ea03c89_I2C0_SCL_escape_0_1",
"baseline_closure_9ea03c89_I2C0_SCL_escape_0_1_via",
"baseline_closure_9ea03c89_I2C0_SCL_escape_0_1_via_0",
"baseline_closure_9ea03c89_I2C0_SCL_escape_1_2",
"baseline_closure_9ea03c89_I2C0_SCL_escape_1_2_via",
"baseline_closure_9ea03c89_I2C0_SCL_escape_1_2_via_0",
"baseline_support_escape_U1_C16",
"baseline_support_via_U1_C16",
"hdmi_low_speed_I2C0_SCL_0",
"hdmi_low_speed_I2C0_SCL_0_via",
"hdmi_low_speed_I2C0_SCL_0_via_0",
"hdmi_low_speed_I2C0_SCL_0_via_1",
"pcb_smtpad_272",
"pcb_smtpad_422",
"pcb_smtpad_521",
"pcb_smtpad_hdmi_pcb_smtpad_11"
],
"required_terminals": [
"pcb_port_272",
"pcb_port_422",
"pcb_port_521",
"pcb_port_hdmi_pcb_port_11"
]
},
{
"root": "273",
"nets": [],
"objects": [
"pcb_smtpad_273"
],
"required_terminals": []
},
{
"root": "12091",
"nets": [
"UART0_TX"
],
"objects": [
"baseline_reset_ijump_09b69059_5",
"baseline_reset_ijump_09b69059_5_via",
"baseline_reset_ijump_09b69059_5_via_27",
"baseline_support_escape_U1_E16",
"baseline_support_via_U1_E16",
"pcb_smtpad_274",
"pcb_smtpad_902"
],
"required_terminals": [
"pcb_port_274",
"pcb_port_902"
]
},
{
"root": "275",
"nets": [],
"objects": [
"pcb_smtpad_275"
],
"required_terminals": []
},
{
"root": "12099",
"nets": [
"MMC0_DAT0"
],
"objects": [
"baseline_closure_331a33a6_MMC0_DAT0_group_0_1",
"baseline_closure_331a33a6_MMC0_DAT0_group_0_1_via",
"baseline_closure_331a33a6_MMC0_DAT0_group_0_1_via_0",
"baseline_reset_ijump_58fa5da9_1",
"baseline_reset_ijump_58fa5da9_1_via",
"baseline_reset_ijump_58fa5da9_1_via_10",
"baseline_reset_ijump_58fa5da9_1_via_6",
"baseline_support_escape_U1_G16",
"baseline_support_via_U1_G16",
"pcb_smtpad_276",
"pcb_smtpad_753",
"pcb_smtpad_764"
],
"required_terminals": [
"pcb_port_276",
"pcb_port_753",
"pcb_port_764"
]
},
{
"root": "277",
"nets": [],
"objects": [
"pcb_smtpad_277"
],
"required_terminals": []
},
{
"root": "13240",
"nets": [
"RMII1_TX_EN"
],
"objects": [
"core_replan_J16_escape",
"core_replan_J16_via",
"pcb_smtpad_278",
"source_damping_R_ETH_TX_EN_SRC_source_pad",
"source_damping_R_ETH_TX_EN_SRC_source_pad_via",
"source_damping_R_ETH_TX_EN_SRC_source_via",
"source_damping_pcb_smtpad_1338"
],
"required_terminals": [
"pcb_port_278",
"source_damping_pcb_port_1350"
]
},
{
"root": "13256",
"nets": [
"RMII1_TXD1"
],
"objects": [
"core_replan_K16_escape",
"core_replan_K16_via",
"pcb_smtpad_279",
"source_damping_R_ETH_TXD1_SRC_source_pad",
"source_damping_R_ETH_TXD1_SRC_source_via",
"source_damping_TXD1_CPU_source_local_0",
"source_damping_TXD1_CPU_source_local_1",
"source_damping_TXD1_CPU_transfer_0",
"source_damping_pcb_smtpad_1342"
],
"required_terminals": [
"pcb_port_279",
"source_damping_pcb_port_1354"
]
},
{
"root": "280",
"nets": [],
"objects": [
"pcb_smtpad_280"
],
"required_terminals": []
},
{
"root": "13438",
"nets": [
"RMII1_RXD0"
],
"objects": [
"core_replan_M16_escape",
"core_replan_M16_via",
"held_RXD0_short_eastern_trunk",
"held_RXD0_short_eastern_trunk_via",
"held_RXD0_short_eastern_trunk_via_0",
"held_RXD0_short_eastern_trunk_via_1",
"held_RXD0_short_eastern_trunk_via_2",
"held_RXD0_short_eastern_trunk_via_3",
"held_RXD0_short_eastern_trunk_via_4",
"held_RXD0_short_eastern_trunk_via_5",
"held_RXD0_short_eastern_trunk_via_6",
"held_RXD0_short_eastern_trunk_via_7",
"pcb_smtpad_1280",
"pcb_smtpad_281",
"proposal_receiver_RMII1_RXD0_top",
"proposal_receiver_RMII1_RXD0_via"
],
"required_terminals": [
"pcb_port_1292",
"pcb_port_281"
]
},
{
"root": "283",
"nets": [],
"objects": [
"pcb_smtpad_283"
],
"required_terminals": []
},
{
"root": "285",
"nets": [],
"objects": [
"pcb_smtpad_285"
],
"required_terminals": []
},
{
"root": "13578",
"nets": [
"MMC0_CD_N"
],
"objects": [
"baseline_reset_ijump_a3c6bd23_1",
"baseline_reset_ijump_a3c6bd23_1_via",
"baseline_reset_ijump_a3c6bd23_1_via_18",
"baseline_reset_ijump_a3c6bd23_1_via_21",
"hdmi_mmc_cd_U16_escape",
"hdmi_mmc_cd_U16_escape_via",
"hdmi_mmc_cd_U16_via",
"pcb_smtpad_286",
"pcb_smtpad_755",
"pcb_smtpad_772"
],
"required_terminals": [
"pcb_port_286",
"pcb_port_755",
"pcb_port_772"
]
},
{
"root": "287",
"nets": [],
"objects": [
"pcb_smtpad_287"
],
"required_terminals": []
},
{
"root": "288",
"nets": [],
"objects": [
"pcb_smtpad_288"
],
"required_terminals": []
},
{
"root": "289",
"nets": [],
"objects": [
"pcb_smtpad_289"
],
"required_terminals": []
},
{
"root": "13606",
"nets": [
"I2C0_SDA"
],
"objects": [
"baseline_closure_24237100_U_PMIC_2_settled_root",
"baseline_closure_24237100_U_PMIC_2_settled_root_via_0",
"baseline_closure_9ea03c89_I2C0_SDA_escape_0_1",
"baseline_closure_9ea03c89_I2C0_SDA_escape_1_2",
"baseline_closure_9ea03c89_I2C0_SDA_escape_1_2_via",
"baseline_closure_9ea03c89_I2C0_SDA_escape_1_2_via_0",
"baseline_support_escape_U1_C17",
"baseline_support_via_U1_C17",
"hdmi_low_speed_I2C0_SDA_0",
"hdmi_low_speed_I2C0_SDA_0_via",
"hdmi_low_speed_I2C0_SDA_0_via_0",
"hdmi_low_speed_I2C0_SDA_0_via_1",
"pcb_smtpad_290",
"pcb_smtpad_421",
"pcb_smtpad_519",
"pcb_smtpad_hdmi_pcb_smtpad_10"
],
"required_terminals": [
"pcb_port_290",
"pcb_port_421",
"pcb_port_519",
"pcb_port_hdmi_pcb_port_10"
]
},
{
"root": "291",
"nets": [],
"objects": [
"pcb_smtpad_291"
],
"required_terminals": []
},
{
"root": "292",
"nets": [],
"objects": [
"pcb_smtpad_292"
],
"required_terminals": []
},
{
"root": "11884",
"nets": [
"MMC0_DAT3"
],
"objects": [
"baseline_reset_ijump_a3c6bd23_11",
"baseline_reset_ijump_a3c6bd23_11_via",
"baseline_reset_ijump_a3c6bd23_11_via_13",
"baseline_reset_ijump_a3c6bd23_11_via_20",
"baseline_reset_ijump_c09a341b_8",
"baseline_reset_ijump_c09a341b_8_via",
"baseline_reset_ijump_c09a341b_8_via_11",
"baseline_reset_ijump_c09a341b_8_via_17",
"baseline_support_escape_U1_F17",
"baseline_support_via_U1_F17",
"pcb_smtpad_293",
"pcb_smtpad_748",
"pcb_smtpad_770"
],
"required_terminals": [
"pcb_port_293",
"pcb_port_748",
"pcb_port_770"
]
},
{
"root": "11905",
"nets": [
"MMC0_CLK"
],
"objects": [
"baseline_reset_ijump_c09a341b_1",
"baseline_support_escape_U1_G17",
"baseline_support_via_U1_G17",
"pcb_smtpad_294",
"pcb_smtpad_877"
],
"required_terminals": [
"pcb_port_294",
"pcb_port_881"
]
},
{
"root": "13283",
"nets": [
"RMII1_CRS_DV"
],
"objects": [
"core_replan_H17_escape",
"core_replan_H17_via",
"pcb_smtpad_1282",
"pcb_smtpad_295",
"resume_lcd_RMII1_CRS_DV",
"resume_lcd_RMII1_CRS_DV_via",
"resume_lcd_RMII1_CRS_DV_via_0",
"resume_lcd_RMII1_CRS_DV_via_1",
"resume_lcd_RMII1_CRS_DV_via_2",
"resume_lcd_RMII1_CRS_DV_via_3",
"resume_lcd_RMII1_CRS_DV_via_4",
"resume_lcd_RMII1_CRS_DV_via_5"
],
"required_terminals": [
"pcb_port_1294",
"pcb_port_295"
]
},
{
"root": "296",
"nets": [],
"objects": [
"pcb_smtpad_296"
],
"required_terminals": []
},
{
"root": "13252",
"nets": [
"RMII1_TXD0"
],
"objects": [
"core_replan_K17_escape",
"core_replan_K17_via",
"pcb_smtpad_297",
"source_damping_R_ETH_TXD0_SRC_source_pad",
"source_damping_R_ETH_TXD0_SRC_source_via",
"source_damping_TXD0_source_corridor",
"source_damping_pcb_smtpad_1340"
],
"required_terminals": [
"pcb_port_297",
"source_damping_pcb_port_1352"
]
},
{
"root": "298",
"nets": [],
"objects": [
"pcb_smtpad_298"
],
"required_terminals": []
},
{
"root": "13213",
"nets": [
"ETH_MDIO"
],
"objects": [
"closure_1fb16f50_CPU_escape_ETH_MDIO",
"closure_1fb16f50_CPU_escape_ETH_MDIO_via_0",
"closure_982db102_two_layer_ETH_MDIO",
"closure_982db102_two_layer_ETH_MDIO_via",
"closure_982db102_two_layer_ETH_MDIO_via_0",
"closure_982db102_two_layer_ETH_MDIO_via_1",
"closure_982db102_two_layer_ETH_MDIO_via_2",
"closure_982db102_two_layer_ETH_MDIO_via_3",
"closure_c1082fb3_LCD_local_escape_ETH_MDIO",
"closure_c1082fb3_LCD_local_escape_ETH_MDIO_via_0",
"pcb_smtpad_1299",
"pcb_smtpad_299"
],
"required_terminals": [
"pcb_port_1311",
"pcb_port_299"
]
},
{
"root": "300",
"nets": [],
"objects": [
"pcb_smtpad_300"
],
"required_terminals": []
},
{
"root": "301",
"nets": [],
"objects": [
"pcb_smtpad_301"
],
"required_terminals": []
},
{
"root": "302",
"nets": [],
"objects": [
"pcb_smtpad_302"
],
"required_terminals": []
},
{
"root": "303",
"nets": [],
"objects": [
"pcb_smtpad_303"
],
"required_terminals": []
},
{
"root": "304",
"nets": [],
"objects": [
"pcb_smtpad_304"
],
"required_terminals": []
},
{
"root": "13621",
"nets": [
"HDMI_INT_N"
],
"objects": [
"hdmi_low_speed_HDMI_INT_N_0",
"hdmi_low_speed_HDMI_INT_N_0_via",
"hdmi_low_speed_HDMI_INT_N_0_via_0",
"hdmi_low_speed_HDMI_INT_N_0_via_1",
"hdmi_low_speed_HDMI_INT_N_1",
"hdmi_low_speed_HDMI_INT_N_1_via",
"hdmi_low_speed_HDMI_INT_N_1_via_0",
"pcb_smtpad_305",
"pcb_smtpad_hdmi_pcb_smtpad_128",
"pcb_smtpad_hdmi_pcb_smtpad_9"
],
"required_terminals": [
"pcb_port_305",
"pcb_port_hdmi_pcb_port_128",
"pcb_port_hdmi_pcb_port_9"
]
},
{
"root": "307",
"nets": [],
"objects": [
"pcb_smtpad_307"
],
"required_terminals": []
},
{
"root": "13640",
"nets": [
"HDMI_RESET_GPIO_N"
],
"objects": [
"hdmi_low_speed_HDMI_RESET_GPIO_N_0",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via_0",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via_1",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via_2",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via_3",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via_4",
"hdmi_low_speed_HDMI_RESET_GPIO_N_0_via_5",
"hdmi_low_speed_HDMI_RESET_GPIO_N_1",
"pcb_smtpad_308",
"pcb_smtpad_hdmi_pcb_smtpad_146",
"pcb_smtpad_hdmi_pcb_smtpad_154"
],
"required_terminals": [
"pcb_port_308",
"pcb_port_hdmi_pcb_port_146",
"pcb_port_hdmi_pcb_port_154"
]
},
{
"root": "309",
"nets": [],
"objects": [
"pcb_smtpad_309"
],
"required_terminals": []
},
{
"root": "310",
"nets": [],
"objects": [
"pcb_smtpad_310"
],
"required_terminals": []
},
{
"root": "12772",
"nets": [
"MMC0_DAT2"
],
"objects": [
"baseline_closure_925266cf_MMC0_DAT2_group_0_1",
"baseline_closure_e5158c8d_dat2_pullup_card_contact",
"baseline_closure_fe0927a2_J_MICROSD_1_ordinary_contact_root",
"baseline_closure_fe0927a2_J_MICROSD_1_ordinary_contact_root_via_0",
"baseline_support_escape_U1_F18",
"baseline_support_via_U1_F18",
"pcb_smtpad_311",
"pcb_smtpad_747",
"pcb_smtpad_768"
],
"required_terminals": [
"pcb_port_311",
"pcb_port_747",
"pcb_port_768"
]
},
{
"root": "11873",
"nets": [
"MMC0_CMD"
],
"objects": [
"baseline_reset_ijump_a3c6bd23_3",
"baseline_reset_ijump_a3c6bd23_3_via",
"baseline_reset_ijump_a3c6bd23_3_via_3",
"baseline_reset_ijump_a3c6bd23_3_via_9",
"baseline_reset_ijump_a3c6bd23_4",
"baseline_reset_ijump_a3c6bd23_4_via",
"baseline_reset_ijump_a3c6bd23_4_via_13",
"baseline_reset_ijump_a3c6bd23_4_via_19",
"baseline_support_escape_U1_G18",
"baseline_support_via_U1_G18",
"pcb_smtpad_312",
"pcb_smtpad_749",
"pcb_smtpad_762"
],
"required_terminals": [
"pcb_port_312",
"pcb_port_749",
"pcb_port_762"
]
},
{
"root": "12896",
"nets": [
"RMII1_REFCLK"
],
"objects": [
"closure_88c738dc_RMII1_REFCLK_cpu_surface_0",
"pcb_smtpad_1284",
"pcb_smtpad_313"
],
"required_terminals": [
"pcb_port_1296",
"pcb_port_313"
]
},
{
"root": "314",
"nets": [],
"objects": [
"pcb_smtpad_314"
],
"required_terminals": []
},
{
"root": "315",
"nets": [],
"objects": [
"pcb_smtpad_315"
],
"required_terminals": []
},
{
"root": "316",
"nets": [],
"objects": [
"pcb_smtpad_316"
],
"required_terminals": []
},
{
"root": "13253",
"nets": [
"ETH_MDC"
],
"objects": [
"closure_1fb16f50_CPU_escape_ETH_MDC",
"closure_1fb16f50_CPU_escape_ETH_MDC_via_0",
"pcb_smtpad_317",
"source_damping_MDC_CPU_source_local_0",
"source_damping_MDC_CPU_source_local_1",
"source_damping_MDC_CPU_transfer_0",
"source_damping_R_ETH_MDC_SRC_source_pad",
"source_damping_R_ETH_MDC_SRC_source_via",
"source_damping_pcb_smtpad_1344"
],
"required_terminals": [
"pcb_port_317",
"source_damping_pcb_port_1356"
]
},
{
"root": "318",
"nets": [],
"objects": [
"pcb_smtpad_318"
],
"required_terminals": []
},
{
"root": "319",
"nets": [],
"objects": [
"pcb_smtpad_319"
],
"required_terminals": []
},
{
"root": "320",
"nets": [],
"objects": [
"pcb_smtpad_320"
],
"required_terminals": []
},
{
"root": "321",
"nets": [],
"objects": [
"pcb_smtpad_321"
],
"required_terminals": []
},
{
"root": "322",
"nets": [],
"objects": [
"pcb_smtpad_322"
],
"required_terminals": []
},
{
"root": "332",
"nets": [],
"objects": [
"pcb_smtpad_332"
],
"required_terminals": []
},
{
"root": "334",
"nets": [],
"objects": [
"pcb_smtpad_334"
],
"required_terminals": []
},
{
"root": "371",
"nets": [],
"objects": [
"pcb_smtpad_371"
],
"required_terminals": []
},
{
"root": "383",
"nets": [],
"objects": [
"pcb_smtpad_383"
],
"required_terminals": []
},
{
"root": "387",
"nets": [],
"objects": [
"pcb_smtpad_387"
],
"required_terminals": []
},
{
"root": "11996",
"nets": [
"DDR_ZQ"
],
"objects": [
"baseline_reset_ijump_d886ba68_4",
"baseline_reset_ijump_d886ba68_4_via",
"baseline_reset_ijump_d886ba68_4_via_4",
"baseline_reset_ijump_d886ba68_4_via_8",
"baseline_support_escape_U3_L8",
"baseline_support_via_U3_L8",
"pcb_smtpad_398",
"pcb_smtpad_655"
],
"required_terminals": [
"pcb_port_398",
"pcb_port_655"
]
},
{
"root": "412",
"nets": [],
"objects": [
"pcb_smtpad_412"
],
"required_terminals": []
},
{
"root": "414",
"nets": [],
"objects": [
"pcb_smtpad_414"
],
"required_terminals": []
},
{
"root": "12345",
"nets": [
"SYS_5V"
],
"objects": [
"baseline_closure_5a412b81_C_PWR6_pin1_rotated_local",
"baseline_closure_a53f450e_C_EFUSE_OUT_pin1_SYS0",
"baseline_closure_a53f450e_C_EFUSE_OUT_pin1_SYS0_via_0",
"baseline_closure_a53f450e_C_PWR1_pin1_SYS0",
"baseline_closure_a53f450e_C_PWR1_pin1_SYS0_via_0",
"baseline_closure_a53f450e_C_PWR1_pin1_SYS1",
"baseline_closure_a53f450e_C_PWR1_pin1_SYS1_via_0",
"baseline_closure_a53f450e_C_PWR2_pin1_SYS0",
"baseline_closure_a53f450e_C_PWR2_pin1_SYS0_via_0",
"baseline_closure_a53f450e_C_PWR2_pin1_SYS1",
"baseline_closure_a53f450e_C_PWR2_pin1_SYS1_via_0",
"baseline_closure_a53f450e_C_PWR3_pin1_SYS0",
"baseline_closure_a53f450e_C_PWR3_pin1_SYS0_via_0",
"baseline_closure_a53f450e_C_PWR3_pin1_SYS1",
"baseline_closure_a53f450e_C_PWR3_pin1_SYS1_via_0",
"baseline_closure_a53f450e_C_PWR4_pin1_SYS0",
"baseline_closure_a53f450e_C_PWR4_pin1_SYS0_via_0",
"baseline_closure_a53f450e_C_PWR4_pin1_SYS1",
"baseline_closure_a53f450e_C_PWR4_pin1_SYS1_via_0",
"baseline_closure_a53f450e_C_PWR5_pin1_SYS0",
"baseline_closure_a53f450e_C_PWR5_pin1_SYS0_via_0",
"baseline_closure_a53f450e_R_PWR7_pin2_SYS0",
"baseline_closure_a53f450e_R_PWR7_pin2_SYS0_via_0",
"baseline_closure_a53f450e_R_SYS_BLEED_pin1_SYS0",
"baseline_closure_a53f450e_R_SYS_BLEED_pin1_SYS0_via_0",
"baseline_closure_a53f450e_SYS_trunk_0_1",
"baseline_closure_a53f450e_SYS_trunk_10_13",
"baseline_closure_a53f450e_SYS_trunk_11_8",
"baseline_closure_a53f450e_SYS_trunk_13_14",
"baseline_closure_a53f450e_SYS_trunk_1_5",
"baseline_closure_a53f450e_SYS_trunk_2_11",
"baseline_closure_a53f450e_SYS_trunk_3_2",
"baseline_closure_a53f450e_SYS_trunk_4_6",
"baseline_closure_a53f450e_SYS_trunk_5_3",
"baseline_closure_a53f450e_SYS_trunk_5_4",
"baseline_closure_a53f450e_SYS_trunk_6_7",
"baseline_closure_a53f450e_SYS_trunk_7_10",
"baseline_closure_a53f450e_SYS_trunk_8_9",
"baseline_closure_a53f450e_U_INPUT_EFUSE_5_SYS0",
"baseline_closure_a53f450e_U_INPUT_EFUSE_5_SYS0_via_0",
"baseline_closure_a53f450e_U_INPUT_EFUSE_5_SYS1",
"baseline_closure_a53f450e_U_INPUT_EFUSE_5_SYS1_via_0",
"baseline_closure_a53f450e_U_PMIC_36_SYS0",
"baseline_closure_a53f450e_U_PMIC_36_SYS0_via_0",
"baseline_closure_a53f450e_U_PMIC_6_SYS0",
"baseline_closure_a53f450e_U_PMIC_6_SYS0_via_0",
"baseline_closure_cd4b9ff3_PFI_input_escape",
"baseline_closure_cd4b9ff3_PFI_input_escape_via_0",
"baseline_closure_f76f742f_R_SYS_BLEED_pin1_fed_signal_branch",
"baseline_closure_f76f742f_U_PMIC_16_fed_signal_branch",
"baseline_local_input_3f1bc542_DCDC1_input",
"baseline_local_input_4d73c9ba_DCDC3_input",
"baseline_local_input_4d73c9ba_DCDC4_input",
"baseline_local_input_e09f275e_DCDC2_input",
"baseline_local_support_5",
"baseline_reset_ijump_af73141d_0",
"baseline_reset_ijump_af73141d_0_via",
"baseline_reset_ijump_af73141d_0_via_6",
"closure_81c27571_SYS5V_extension_feed",
"closure_81c27571_SYS5V_extension_feed_via_0",
"closure_adeb6f65_C_ETH_LDO_IN_pin1_tap0",
"closure_adeb6f65_C_ETH_LDO_IN_pin1_tap0_via_0",
"closure_adeb6f65_C_LCD_BL_IN_pin1_tap0",
"closure_adeb6f65_C_LCD_BL_IN_pin1_tap0_via_0",
"closure_adeb6f65_C_LCD_LDO_IN_pin1_tap0",
"closure_adeb6f65_C_LCD_LDO_IN_pin1_tap0_via_0",
"closure_adeb6f65_L_LCD_BL_pin1_tap0",
"closure_adeb6f65_L_LCD_BL_pin1_tap0_via_0",
"closure_ff49e202_U_ETH_LDO_1_tap0",
"closure_ff49e202_U_ETH_LDO_1_tap0_via_0",
"closure_ff49e202_U_LCD_BL_5_tap0",
"closure_ff49e202_U_LCD_BL_5_tap0_via_0",
"closure_ff49e202_U_LCD_LDO_1_tap0",
"closure_ff49e202_U_LCD_LDO_1_tap0_via_0",
"dbg_pcb_smtpad_0",
"dbg_pcb_trace_0",
"interface_plan_SYS5V_EXT_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0",
"pcb_smtpad_420",
"pcb_smtpad_424",
"pcb_smtpad_425",
"pcb_smtpad_431",
"pcb_smtpad_435",
"pcb_smtpad_455",
"pcb_smtpad_456",
"pcb_smtpad_462",
"pcb_smtpad_477",
"pcb_smtpad_479",
"pcb_smtpad_481",
"pcb_smtpad_483",
"pcb_smtpad_485",
"pcb_smtpad_487",
"pcb_smtpad_524",
"pcb_smtpad_829",
"pcb_smtpad_854",
"pcb_smtpad_856",
"pcb_smtpad_947",
"pcb_smtpad_952"
],
"required_terminals": [
"dbg_pcb_port_0",
"pcb_port_420",
"pcb_port_424",
"pcb_port_425",
"pcb_port_431",
"pcb_port_435",
"pcb_port_455",
"pcb_port_456",
"pcb_port_462",
"pcb_port_477",
"pcb_port_479",
"pcb_port_481",
"pcb_port_483",
"pcb_port_485",
"pcb_port_487",
"pcb_port_524",
"pcb_port_833",
"pcb_port_858",
"pcb_port_860",
"pcb_port_947",
"pcb_port_952"
]
},
{
"root": "426",
"nets": [],
"objects": [
"pcb_smtpad_426"
],
"required_terminals": []
},
{
"root": "12072",
"nets": [
"PMIC_PGOOD"
],
"objects": [
"baseline_pgood_root_7ded2787",
"baseline_reset_ijump_0d4daf32_0",
"baseline_reset_ijump_0d4daf32_0_via",
"baseline_reset_ijump_0d4daf32_0_via_14",
"baseline_reset_ijump_f8b6f07c_0",
"baseline_reset_ijump_f8b6f07c_1",
"baseline_reset_ijump_f8b6f07c_2",
"baseline_reset_ijump_f8b6f07c_2_via",
"baseline_reset_ijump_f8b6f07c_2_via_12",
"pcb_smtpad_427",
"pcb_smtpad_859",
"pcb_smtpad_865",
"pcb_smtpad_873",
"pcb_smtpad_893",
"pg7_pcb_smtpad_13",
"pg7_route_raw_input"
],
"required_terminals": [
"pcb_port_427",
"pcb_port_863",
"pcb_port_869",
"pcb_port_877",
"pcb_port_893",
"pg7_pcb_port_13"
]
},
{
"root": "429",
"nets": [],
"objects": [
"pcb_smtpad_429"
],
"required_terminals": []
},
{
"root": "430",
"nets": [],
"objects": [
"pcb_smtpad_430"
],
"required_terminals": []
},
{
"root": "12067",
"nets": [
"PMIC_SW4A"
],
"objects": [
"baseline_pmic_switch_67e395c2_PMIC_SW4A",
"pcb_smtpad_432",
"pcb_smtpad_475"
],
"required_terminals": [
"pcb_port_432",
"pcb_port_475"
]
},
{
"root": "12066",
"nets": [
"PMIC_SW4B"
],
"objects": [
"baseline_pmic_switch_67e395c2_PMIC_SW4B",
"pcb_smtpad_433",
"pcb_smtpad_476"
],
"required_terminals": [
"pcb_port_433",
"pcb_port_476"
]
},
{
"root": "12301",
"nets": [
"PMIC_DC34_SEL"
],
"objects": [
"baseline_closure_fcadd8db_DC34_selector",
"baseline_closure_fcadd8db_DC34_selector_via",
"baseline_closure_fcadd8db_DC34_selector_via_0",
"pcb_smtpad_436",
"pcb_smtpad_511"
],
"required_terminals": [
"pcb_port_436",
"pcb_port_511"
]
},
{
"root": "437",
"nets": [],
"objects": [
"pcb_smtpad_437"
],
"required_terminals": []
},
{
"root": "438",
"nets": [],
"objects": [
"pcb_smtpad_438"
],
"required_terminals": []
},
{
"root": "447",
"nets": [],
"objects": [
"pcb_smtpad_447"
],
"required_terminals": []
},
{
"root": "448",
"nets": [],
"objects": [
"pcb_smtpad_448"
],
"required_terminals": []
},
{
"root": "453",
"nets": [],
"objects": [
"pcb_smtpad_453"
],
"required_terminals": []
},
{
"root": "12319",
"nets": [
"PMIC_INT_LDO"
],
"objects": [
"baseline_closure_c0cec685_INT_LDO_short_bypass",
"baseline_closure_c0cec685_INT_LDO_short_bypass_via",
"baseline_closure_c0cec685_INT_LDO_short_bypass_via_0",
"pcb_smtpad_454",
"pcb_smtpad_509"
],
"required_terminals": [
"pcb_port_454",
"pcb_port_509"
]
},
{
"root": "12202",
"nets": [
"PMIC_SW3"
],
"objects": [
"baseline_pmic_switch_8fa167aa_PMIC_SW3",
"pcb_smtpad_457",
"pcb_smtpad_473"
],
"required_terminals": [
"pcb_port_457",
"pcb_port_473"
]
},
{
"root": "459",
"nets": [],
"objects": [
"pcb_smtpad_459"
],
"required_terminals": []
},
{
"root": "12203",
"nets": [
"PMIC_SW2"
],
"objects": [
"baseline_pmic_switch_8fa167aa_PMIC_SW2",
"pcb_smtpad_461",
"pcb_smtpad_471"
],
"required_terminals": [
"pcb_port_461",
"pcb_port_471"
]
},
{
"root": "526",
"nets": [
"PMIC_PB_N"
],
"objects": [
"baseline_closure_24237100_U_PMIC_44_settled_root",
"baseline_closure_24237100_U_PMIC_44_settled_root_via_0",
"baseline_closure_ad3e3501_PMIC_PB_N_group_0_1",
"baseline_closure_ad3e3501_PMIC_PB_N_group_0_1_via",
"baseline_closure_ad3e3501_PMIC_PB_N_group_0_1_via_0",
"baseline_closure_ad3e3501_PMIC_PB_N_group_1_2",
"pcb_smtpad_463",
"pcb_smtpad_523",
"pcb_smtpad_525",
"pcb_smtpad_526"
],
"required_terminals": [
"pcb_port_463",
"pcb_port_523",
"pcb_port_525"
]
},
{
"root": "12191",
"nets": [
"PMIC_SW1"
],
"objects": [
"baseline_pmic_switch_9eea90e0_PMIC_SW1",
"pcb_smtpad_467",
"pcb_smtpad_469"
],
"required_terminals": [
"pcb_port_467",
"pcb_port_469"
]
},
{
"root": "12489",
"nets": [
"OSC24_OE"
],
"objects": [
"baseline_closure_50a6dd03_U_CLOCK_GATE_4_clock_crossing_inner",
"baseline_closure_50a6dd03_U_CLOCK_GATE_4_clock_crossing_surface",
"baseline_closure_50a6dd03_U_CLOCK_GATE_4_clock_crossing_surface_via_0",
"baseline_closure_847f7e5f_OSC24_OE_group_0_2",
"baseline_closure_847f7e5f_OSC24_OE_group_0_2_via",
"baseline_closure_847f7e5f_OSC24_OE_group_0_2_via_0",
"baseline_closure_847f7e5f_OSC24_OE_group_0_2_via_1",
"pcb_smtpad_741",
"pcb_smtpad_861",
"pcb_smtpad_875"
],
"required_terminals": [
"pcb_port_741",
"pcb_port_865",
"pcb_port_879"
]
},
{
"root": "12668",
"nets": [
"SD_CLK"
],
"objects": [
"baseline_closure_6297a836_SD_CLK_escape_0_1",
"baseline_closure_6297a836_SD_CLK_escape_0_1_via",
"baseline_closure_6297a836_SD_CLK_escape_0_1_via_0",
"baseline_closure_6297a836_SD_CLK_escape_0_1_via_1",
"pcb_smtpad_751",
"pcb_smtpad_878"
],
"required_terminals": [
"pcb_port_751",
"pcb_port_882"
]
},
{
"root": "12574",
"nets": [
"USBC_VBUS_RAW"
],
"objects": [
"baseline_closure_6ee4a10a_C_RAW_EFUSE_pin1_RAW0",
"baseline_closure_6ee4a10a_C_RAW_EFUSE_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_C_RAW_NOR_pin1_RAW0",
"baseline_closure_6ee4a10a_C_RAW_NOR_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_C_RAW_TYPEC_pin1_RAW0",
"baseline_closure_6ee4a10a_C_RAW_TYPEC_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_J_POWER_A4_RAW0",
"baseline_closure_6ee4a10a_J_POWER_A4_RAW0_via_0",
"baseline_closure_6ee4a10a_J_POWER_A4_RAW1",
"baseline_closure_6ee4a10a_J_POWER_A4_RAW1_via_0",
"baseline_closure_6ee4a10a_J_POWER_A9_RAW0",
"baseline_closure_6ee4a10a_J_POWER_A9_RAW0_via_0",
"baseline_closure_6ee4a10a_J_POWER_A9_RAW1",
"baseline_closure_6ee4a10a_J_POWER_A9_RAW1_via_0",
"baseline_closure_6ee4a10a_R_INPUT_FAULT_pin1_RAW0",
"baseline_closure_6ee4a10a_R_INPUT_FAULT_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_R_TYPEC_OUT1_pin1_RAW0",
"baseline_closure_6ee4a10a_R_TYPEC_OUT1_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_R_TYPEC_OUT2_pin1_RAW0",
"baseline_closure_6ee4a10a_R_TYPEC_OUT2_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_R_TYPEC_VBUS_pin1_RAW0",
"baseline_closure_6ee4a10a_R_TYPEC_VBUS_pin1_RAW0_via_0",
"baseline_closure_6ee4a10a_U_INPUT_EFUSE_3_RAW0",
"baseline_closure_6ee4a10a_U_INPUT_EFUSE_3_RAW0_via_0",
"baseline_closure_6ee4a10a_U_INPUT_EFUSE_4_RAW0",
"baseline_closure_6ee4a10a_U_INPUT_EFUSE_4_RAW0_via_0",
"baseline_closure_6ee4a10a_U_TYPEC_12_RAW0",
"baseline_closure_6ee4a10a_U_TYPEC_12_RAW0_via_0",
"baseline_closure_6ee4a10a_U_TYPEC_NOR_3_RAW0",
"baseline_closure_6ee4a10a_U_TYPEC_NOR_3_RAW0_via_0",
"baseline_closure_6ee4a10a_VBUS_input_trunk_0_1",
"baseline_closure_6ee4a10a_VBUS_input_trunk_10_13",
"baseline_closure_6ee4a10a_VBUS_input_trunk_12_6",
"baseline_closure_6ee4a10a_VBUS_input_trunk_13_14",
"baseline_closure_6ee4a10a_VBUS_input_trunk_1_3",
"baseline_closure_6ee4a10a_VBUS_input_trunk_2_12",
"baseline_closure_6ee4a10a_VBUS_input_trunk_3_2",
"baseline_closure_6ee4a10a_VBUS_input_trunk_4_7",
"baseline_closure_6ee4a10a_VBUS_input_trunk_5_4",
"baseline_closure_6ee4a10a_VBUS_input_trunk_6_5",
"baseline_closure_6ee4a10a_VBUS_input_trunk_6_9",
"baseline_closure_6ee4a10a_VBUS_input_trunk_7_10",
"baseline_closure_6ee4a10a_VBUS_input_trunk_7_8",
"baseline_closure_6ee4a10a_VBUS_input_trunk_9_11",
"baseline_closure_8edffe10_nor_vbus_supply_closed",
"pcb_smtpad_778",
"pcb_smtpad_783",
"pcb_smtpad_786",
"pcb_smtpad_791",
"pcb_smtpad_818",
"pcb_smtpad_821",
"pcb_smtpad_823",
"pcb_smtpad_827",
"pcb_smtpad_828",
"pcb_smtpad_834",
"pcb_smtpad_836",
"pcb_smtpad_838",
"pcb_smtpad_844",
"pcb_smtpad_848",
"pcb_smtpad_850",
"pcb_smtpad_852"
],
"required_terminals": [
"pcb_port_778",
"pcb_port_783",
"pcb_port_786",
"pcb_port_791",
"pcb_port_822",
"pcb_port_825",
"pcb_port_827",
"pcb_port_831",
"pcb_port_832",
"pcb_port_838",
"pcb_port_840",
"pcb_port_842",
"pcb_port_848",
"pcb_port_852",
"pcb_port_854",
"pcb_port_856"
]
},
{
"root": "12584",
"nets": [
"USBC_CC1"
],
"objects": [
"baseline_closure_0f7132e1_USBC_CC1_group_0_1",
"baseline_closure_0f7132e1_USBC_CC1_group_0_1_via",
"baseline_closure_0f7132e1_USBC_CC1_group_0_1_via_0",
"baseline_closure_0f7132e1_USBC_CC1_group_0_1_via_1",
"pcb_smtpad_779",
"pcb_smtpad_807"
],
"required_terminals": [
"pcb_port_779",
"pcb_port_811"
]
},
{
"root": "780",
"nets": [],
"objects": [
"pcb_smtpad_780"
],
"required_terminals": []
},
{
"root": "781",
"nets": [],
"objects": [
"pcb_smtpad_781"
],
"required_terminals": []
},
{
"root": "782",
"nets": [],
"objects": [
"pcb_smtpad_782"
],
"required_terminals": []
},
{
"root": "12727",
"nets": [
"USBC_CC2"
],
"objects": [
"baseline_closure_04781cc1_USBC_CC2_escape_0_1",
"baseline_closure_fe0927a2_J_POWER_B5_ordinary_contact_root",
"baseline_closure_fe0927a2_J_POWER_B5_ordinary_contact_root_via_0",
"pcb_smtpad_787",
"pcb_smtpad_808"
],
"required_terminals": [
"pcb_port_787",
"pcb_port_812"
]
},
{
"root": "788",
"nets": [],
"objects": [
"pcb_smtpad_788"
],
"required_terminals": []
},
{
"root": "789",
"nets": [],
"objects": [
"pcb_smtpad_789"
],
"required_terminals": []
},
{
"root": "790",
"nets": [],
"objects": [
"pcb_smtpad_790"
],
"required_terminals": []
},
{
"root": "12593",
"nets": [
"TYPEC_VBUS_DET"
],
"objects": [
"baseline_closure_0f7132e1_TYPEC_VBUS_DET_group_0_1",
"pcb_smtpad_810",
"pcb_smtpad_835"
],
"required_terminals": [
"pcb_port_814",
"pcb_port_839"
]
},
{
"root": "811",
"nets": [],
"objects": [
"pcb_smtpad_811"
],
"required_terminals": []
},
{
"root": "812",
"nets": [],
"objects": [
"pcb_smtpad_812"
],
"required_terminals": []
},
{
"root": "12447",
"nets": [
"TYPEC_OUT1"
],
"objects": [
"baseline_closure_0f7132e1_TYPEC_OUT1_group_0_1",
"baseline_closure_0f7132e1_TYPEC_OUT1_group_0_1_via",
"baseline_closure_0f7132e1_TYPEC_OUT1_group_0_1_via_0",
"baseline_closure_0f7132e1_TYPEC_OUT1_group_0_1_via_1",
"baseline_reset_ijump_fec437dc_6",
"baseline_reset_ijump_fec437dc_6_via",
"baseline_reset_ijump_fec437dc_6_via_6",
"baseline_reset_ijump_fec437dc_6_via_8",
"pcb_smtpad_813",
"pcb_smtpad_819",
"pcb_smtpad_837"
],
"required_terminals": [
"pcb_port_817",
"pcb_port_823",
"pcb_port_841"
]
},
{
"root": "12458",
"nets": [
"TYPEC_OUT2"
],
"objects": [
"baseline_closure_0f7132e1_TYPEC_OUT2_group_0_1",
"baseline_closure_0f7132e1_TYPEC_OUT2_group_0_1_via",
"baseline_closure_0f7132e1_TYPEC_OUT2_group_0_1_via_0",
"baseline_reset_ijump_fec437dc_7",
"baseline_reset_ijump_fec437dc_7_via",
"baseline_reset_ijump_fec437dc_7_via_10",
"baseline_reset_ijump_fec437dc_7_via_12",
"pcb_smtpad_814",
"pcb_smtpad_824",
"pcb_smtpad_839"
],
"required_terminals": [
"pcb_port_818",
"pcb_port_828",
"pcb_port_843"
]
},
{
"root": "815",
"nets": [],
"objects": [
"pcb_smtpad_815"
],
"required_terminals": []
},
{
"root": "12730",
"nets": [
"TYPEC_3A_OK"
],
"objects": [
"baseline_closure_0f7132e1_TYPEC_3A_OK_group_0_1",
"baseline_closure_8edffe10_nor_output_bridge_coplan",
"baseline_closure_8edffe10_nor_output_bridge_coplan_via",
"baseline_closure_8edffe10_nor_output_bridge_coplan_via_0",
"baseline_closure_8edffe10_nor_output_bridge_coplan_via_1",
"pcb_smtpad_822",
"pcb_smtpad_826",
"pcb_smtpad_840"
],
"required_terminals": [
"pcb_port_826",
"pcb_port_830",
"pcb_port_844"
]
},
{
"root": "12432",
"nets": [
"INPUT_DVDT"
],
"objects": [
"baseline_reset_ijump_fec437dc_0",
"pcb_smtpad_825",
"pcb_smtpad_846"
],
"required_terminals": [
"pcb_port_829",
"pcb_port_850"
]
},
{
"root": "12435",
"nets": [
"INPUT_FAULT_N"
],
"objects": [
"baseline_reset_ijump_fec437dc_1",
"baseline_reset_ijump_fec437dc_1_via",
"baseline_reset_ijump_fec437dc_1_via_16",
"baseline_reset_ijump_fec437dc_1_via_18",
"pcb_smtpad_830",
"pcb_smtpad_845"
],
"required_terminals": [
"pcb_port_834",
"pcb_port_849"
]
},
{
"root": "12444",
"nets": [
"INPUT_ILM"
],
"objects": [
"baseline_reset_ijump_fec437dc_2",
"pcb_smtpad_831",
"pcb_smtpad_842"
],
"required_terminals": [
"pcb_port_835",
"pcb_port_846"
]
},
{
"root": "858",
"nets": [],
"objects": [
"pcb_smtpad_858"
],
"required_terminals": []
},
{
"root": "866",
"nets": [],
"objects": [
"pcb_smtpad_866"
],
"required_terminals": []
},
{
"root": "880",
"nets": [],
"objects": [
"pcb_smtpad_880"
],
"required_terminals": []
},
{
"root": "885",
"nets": [],
"objects": [
"pcb_smtpad_885"
],
"required_terminals": []
},
{
"root": "892",
"nets": [],
"objects": [
"pcb_smtpad_892"
],
"required_terminals": []
},
{
"root": "950",
"nets": [],
"objects": [
"pcb_smtpad_950"
],
"required_terminals": []
},
{
"root": "13174",
"nets": [
"ETH_3V3_PRE"
],
"objects": [
"closure_57dcc704_private_ETH_DC_feed_lane",
"closure_57dcc704_private_ETH_DC_feed_lane_via",
"closure_57dcc704_private_ETH_DC_feed_lane_via_0",
"closure_57dcc704_private_ETH_DC_feed_lane_via_1",
"closure_ff49e202_powerfix_U_ETH_LDO_5_C_ETH_LDO_OUT_pin1",
"pcb_smtpad_1268",
"pcb_smtpad_951",
"pcb_smtpad_954"
],
"required_terminals": [
"pcb_port_1280",
"pcb_port_951",
"pcb_port_954"
]
},
{
"root": "13163",
"nets": [
"PHY_TX_EN"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_1",
"closure_a473a0c2_PHY_ordered_escape_1_via_0",
"closure_ae7b6f4e_PHY_TX_EN_carrier_34",
"closure_ae7b6f4e_PHY_TX_EN_carrier_34_via",
"closure_ae7b6f4e_PHY_TX_EN_carrier_34_via_0",
"pcb_smtpad_965",
"pcb_smtpad_991"
],
"required_terminals": [
"pcb_port_965",
"pcb_port_991"
]
},
{
"root": "13121",
"nets": [
"PHY_REFCLK"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_2",
"closure_a473a0c2_PHY_ordered_escape_2_via_0",
"closure_ae7b6f4e_PHY_REFCLK_carrier_13",
"closure_ae7b6f4e_PHY_REFCLK_carrier_13_via",
"closure_ae7b6f4e_PHY_REFCLK_carrier_13_via_0",
"closure_ae7b6f4e_PHY_REFCLK_carrier_13_via_1",
"closure_ae7b6f4e_PHY_REFCLK_carrier_16",
"pcb_smtpad_1006",
"pcb_smtpad_1014",
"pcb_smtpad_966"
],
"required_terminals": [
"pcb_port_1006",
"pcb_port_1014",
"pcb_port_966"
]
},
{
"root": "13094",
"nets": [
"PHY_INT_N"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_3",
"closure_a473a0c2_PHY_ordered_escape_3_via_0",
"closure_ae7b6f4e_PHY_INT_N_carrier_7",
"closure_ae7b6f4e_PHY_INT_N_carrier_7_via",
"closure_ae7b6f4e_PHY_INT_N_carrier_7_via_0",
"pcb_smtpad_1024",
"pcb_smtpad_967"
],
"required_terminals": [
"pcb_port_1024",
"pcb_port_967"
]
},
{
"root": "13100",
"nets": [
"PHY_LED0"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_4",
"closure_a473a0c2_PHY_ordered_escape_4_via_0",
"closure_ae7b6f4e_PHY_LED0_carrier_11",
"closure_ae7b6f4e_PHY_LED0_carrier_9",
"closure_ae7b6f4e_PHY_LED0_carrier_9_via",
"closure_ae7b6f4e_PHY_LED0_carrier_9_via_0",
"pcb_smtpad_1018",
"pcb_smtpad_1060",
"pcb_smtpad_968"
],
"required_terminals": [
"pcb_port_1018",
"pcb_port_1074",
"pcb_port_968"
]
},
{
"root": "13123",
"nets": [
"PHY_RESET_N"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_5",
"closure_a473a0c2_PHY_ordered_escape_5_via_0",
"closure_ae7b6f4e_PHY_RESET_N_carrier_17",
"closure_ae7b6f4e_PHY_RESET_N_carrier_18",
"closure_ae7b6f4e_PHY_RESET_N_carrier_18_via",
"closure_ae7b6f4e_PHY_RESET_N_carrier_18_via_0",
"closure_ae7b6f4e_PHY_RESET_N_carrier_20",
"pcb_smtpad_1034",
"pcb_smtpad_1040",
"pcb_smtpad_1321",
"pcb_smtpad_969"
],
"required_terminals": [
"pcb_port_1034",
"pcb_port_1040",
"pcb_port_1333",
"pcb_port_969"
]
},
{
"root": "14686",
"nets": [
"ETH_3V3"
],
"objects": [
"closure_0d2751e3_C_ETH_A0_pin1_tap0",
"closure_0d2751e3_C_ETH_A0_pin1_tap0_via_0",
"closure_0d2751e3_C_ETH_A1_pin1_existing",
"closure_0d2751e3_C_ETH_A2_pin1_existing",
"closure_0d2751e3_C_ETH_IO0_pin1_tap0",
"closure_0d2751e3_C_ETH_IO0_pin1_tap0_via_0",
"closure_0d2751e3_C_ETH_IO1_pin1_tap0",
"closure_0d2751e3_C_ETH_IO1_pin1_tap0_via_0",
"closure_0d2751e3_R_ETH_INT_PU_pin2_tap0",
"closure_0d2751e3_R_ETH_INT_PU_pin2_tap0_via_0",
"closure_0d2751e3_R_ETH_MDIO_PU_pin2_existing",
"closure_0d2751e3_U_ETH_PHY_19_C_ETH_IO0_pin1",
"closure_0d2751e3_U_ETH_PHY_6_C_ETH_A0_pin1",
"closure_0d2751e3_U_ETH_PHY_6_C_ETH_A1_pin1",
"closure_1badfd88_named_bypass_U_ETH_ISO1_20",
"closure_48c4415c_bypass_U_ETH_ISO0_20_C_ETH_ISO0_pin1",
"closure_48c4415c_bypass_U_ETH_RAMP_5_U_ETH_RAMP_6",
"closure_adeb6f65_C_ETH_A2_pin1_tap0_via_0",
"closure_adeb6f65_C_ETH_A3_pin1_tap0",
"closure_adeb6f65_C_ETH_A3_pin1_tap0_via_0",
"closure_adeb6f65_C_ETH_IO2_pin1_tap0",
"closure_adeb6f65_C_ETH_IO2_pin1_tap0_via_0",
"closure_adeb6f65_C_ETH_IO3_pin1_tap0",
"closure_adeb6f65_C_ETH_IO3_pin1_tap0_via_0",
"closure_adeb6f65_C_ETH_ISO_OE_pin1_tap0",
"closure_adeb6f65_C_ETH_ISO_OE_pin1_tap0_via_0",
"closure_adeb6f65_C_ETH_OSC_pin1_existing",
"closure_adeb6f65_C_ETH_RESET_pin1_tap0",
"closure_adeb6f65_C_ETH_RESET_pin1_tap0_via_0",
"closure_adeb6f65_R_ETH_ISO_OE_PU_pin2_tap0",
"closure_adeb6f65_R_ETH_ISO_OE_PU_pin2_tap0_via_0",
"closure_adeb6f65_R_ETH_RESET_PU_pin2_existing",
"closure_adeb6f65_U_ETH_RAMP_6_tap0",
"closure_adeb6f65_U_ETH_RAMP_6_tap0_via_0",
"closure_ff49e202_R_ETH_YELLOW_pin1_existing",
"closure_ff49e202_U_ETH_ISO0_20_tap0",
"closure_ff49e202_U_ETH_ISO0_20_tap0_via_0",
"closure_ff49e202_U_ETH_ISO1_20_existing",
"closure_ff49e202_U_ETH_ISO_OE_5_tap0",
"closure_ff49e202_U_ETH_ISO_OE_5_tap0_via_0",
"closure_ff49e202_U_ETH_RESET_5_existing",
"closure_ff49e202_U_ETH_RESET_6_tap0",
"closure_ff49e202_U_ETH_RESET_6_tap0_via_0",
"closure_ff49e202_Y_ETH_1_tap0",
"closure_ff49e202_Y_ETH_1_tap0_via_0",
"closure_ff49e202_Y_ETH_4_existing",
"interface_plan_ETH_3V3_EXT_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0_clip0",
"pcb_smtpad_1023",
"pcb_smtpad_1025",
"pcb_smtpad_1026",
"pcb_smtpad_1029",
"pcb_smtpad_1032",
"pcb_smtpad_1038",
"pcb_smtpad_1039",
"pcb_smtpad_1041",
"pcb_smtpad_1042",
"pcb_smtpad_1044",
"pcb_smtpad_1046",
"pcb_smtpad_1048",
"pcb_smtpad_1050",
"pcb_smtpad_1052",
"pcb_smtpad_1054",
"pcb_smtpad_1056",
"pcb_smtpad_1058",
"pcb_smtpad_1062",
"pcb_smtpad_1272",
"pcb_smtpad_1273",
"pcb_smtpad_1295",
"pcb_smtpad_1296",
"pcb_smtpad_1317",
"pcb_smtpad_1318",
"pcb_smtpad_1324",
"pcb_smtpad_1326",
"pcb_smtpad_1327",
"pcb_smtpad_970",
"pcb_smtpad_983"
],
"required_terminals": [
"pcb_port_1023",
"pcb_port_1025",
"pcb_port_1026",
"pcb_port_1029",
"pcb_port_1032",
"pcb_port_1038",
"pcb_port_1039",
"pcb_port_1041",
"pcb_port_1042",
"pcb_port_1044",
"pcb_port_1046",
"pcb_port_1048",
"pcb_port_1050",
"pcb_port_1052",
"pcb_port_1054",
"pcb_port_1056",
"pcb_port_1058",
"pcb_port_1076",
"pcb_port_1284",
"pcb_port_1285",
"pcb_port_1307",
"pcb_port_1308",
"pcb_port_1329",
"pcb_port_1330",
"pcb_port_1336",
"pcb_port_1338",
"pcb_port_1339",
"pcb_port_970",
"pcb_port_983"
]
},
{
"root": "13028",
"nets": [
"ETH_RX_N"
],
"objects": [
"closure_0d2751e3_U_ETH_PHY_7_U_ETH_ESD_5",
"closure_0d2751e3_U_ETH_PHY_7_U_ETH_ESD_5_via_0",
"closure_3b087c41_MDI_RX_ETH_RX_N",
"pcb_plated_hole_9",
"pcb_smtpad_1076",
"pcb_smtpad_971"
],
"required_terminals": [
"pcb_port_1065",
"pcb_port_1090",
"pcb_port_971"
]
},
{
"root": "13029",
"nets": [
"ETH_RX_P"
],
"objects": [
"closure_0d2751e3_U_ETH_PHY_8_U_ETH_ESD_4",
"closure_0d2751e3_U_ETH_PHY_8_U_ETH_ESD_4_via_0",
"closure_3b087c41_MDI_RX_ETH_RX_P",
"pcb_plated_hole_7",
"pcb_smtpad_1075",
"pcb_smtpad_972"
],
"required_terminals": [
"pcb_port_1063",
"pcb_port_1089",
"pcb_port_972"
]
},
{
"root": "13030",
"nets": [
"ETH_TX_N"
],
"objects": [
"closure_0d2751e3_U_ETH_PHY_10_U_ETH_ESD_2",
"closure_0d2751e3_U_ETH_PHY_10_U_ETH_ESD_2_via_0",
"closure_3b087c41_MDI_TX_ETH_TX_N",
"pcb_plated_hole_6",
"pcb_smtpad_1073",
"pcb_smtpad_974"
],
"required_terminals": [
"pcb_port_1062",
"pcb_port_1087",
"pcb_port_974"
]
},
{
"root": "13031",
"nets": [
"ETH_TX_P"
],
"objects": [
"closure_0d2751e3_U_ETH_PHY_11_U_ETH_ESD_1",
"closure_0d2751e3_U_ETH_PHY_11_U_ETH_ESD_1_via_0",
"closure_3b087c41_MDI_TX_ETH_TX_P",
"pcb_plated_hole_4",
"pcb_smtpad_1072",
"pcb_smtpad_975"
],
"required_terminals": [
"pcb_port_1060",
"pcb_port_1086",
"pcb_port_975"
]
},
{
"root": "967",
"nets": [],
"objects": [
"pcb_smtpad_976"
],
"required_terminals": []
},
{
"root": "13068",
"nets": [
"PHY_XI"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_13",
"closure_a473a0c2_PHY_ordered_escape_13_via_0",
"closure_ae7b6f4e_PHY_XI_carrier_36",
"pcb_smtpad_1031",
"pcb_smtpad_977"
],
"required_terminals": [
"pcb_port_1031",
"pcb_port_977"
]
},
{
"root": "12919",
"nets": [
"PHY_RBIAS"
],
"objects": [
"closure_0d2751e3_U_ETH_PHY_14_R_ETH_BIAS_pin1",
"pcb_smtpad_1020",
"pcb_smtpad_978"
],
"required_terminals": [
"pcb_port_1020",
"pcb_port_978"
]
},
{
"root": "13081",
"nets": [
"ETH_MDIO_ISO"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_15",
"closure_a473a0c2_PHY_ordered_escape_15_via_0",
"closure_ae7b6f4e_ETH_MDIO_ISO_carrier_1",
"closure_ae7b6f4e_ETH_MDIO_ISO_carrier_2",
"closure_ae7b6f4e_ETH_MDIO_ISO_carrier_2_via",
"closure_ae7b6f4e_ETH_MDIO_ISO_carrier_2_via_0",
"pcb_smtpad_1022",
"pcb_smtpad_1315",
"pcb_smtpad_979"
],
"required_terminals": [
"pcb_port_1022",
"pcb_port_1327",
"pcb_port_979"
]
},
{
"root": "13109",
"nets": [
"PHY_MDC"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_16",
"closure_a473a0c2_PHY_ordered_escape_16_via_0",
"closure_ae7b6f4e_PHY_MDC_carrier_12",
"pcb_smtpad_980",
"pcb_smtpad_997"
],
"required_terminals": [
"pcb_port_980",
"pcb_port_997"
]
},
{
"root": "13142",
"nets": [
"PHY_RXD1"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_17",
"closure_a473a0c2_PHY_ordered_escape_17_via_0",
"closure_ae7b6f4e_PHY_RXD1_carrier_25",
"closure_ae7b6f4e_PHY_RXD1_carrier_25_via",
"closure_ae7b6f4e_PHY_RXD1_carrier_25_via_0",
"closure_ae7b6f4e_PHY_RXD1_carrier_27",
"closure_ae7b6f4e_PHY_RXD1_carrier_27_via",
"closure_ae7b6f4e_PHY_RXD1_carrier_27_via_0",
"pcb_smtpad_1000",
"pcb_smtpad_1012",
"pcb_smtpad_981"
],
"required_terminals": [
"pcb_port_1000",
"pcb_port_1012",
"pcb_port_981"
]
},
{
"root": "13136",
"nets": [
"PHY_RXD0"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_18",
"closure_a473a0c2_PHY_ordered_escape_18_via_0",
"closure_ae7b6f4e_PHY_RXD0_carrier_21",
"closure_ae7b6f4e_PHY_RXD0_carrier_21_via",
"closure_ae7b6f4e_PHY_RXD0_carrier_21_via_0",
"closure_ae7b6f4e_PHY_RXD0_carrier_23",
"closure_ae7b6f4e_PHY_RXD0_carrier_23_via",
"closure_ae7b6f4e_PHY_RXD0_carrier_23_via_0",
"pcb_smtpad_1008",
"pcb_smtpad_982",
"pcb_smtpad_998"
],
"required_terminals": [
"pcb_port_1008",
"pcb_port_982",
"pcb_port_998"
]
},
{
"root": "13088",
"nets": [
"PHY_CRS_DV"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_20",
"closure_a473a0c2_PHY_ordered_escape_20_via_0",
"closure_ae7b6f4e_PHY_CRS_DV_carrier_4",
"closure_ae7b6f4e_PHY_CRS_DV_carrier_5",
"closure_ae7b6f4e_PHY_CRS_DV_carrier_5_via",
"closure_ae7b6f4e_PHY_CRS_DV_carrier_5_via_0",
"pcb_smtpad_1002",
"pcb_smtpad_1010",
"pcb_smtpad_984"
],
"required_terminals": [
"pcb_port_1002",
"pcb_port_1010",
"pcb_port_984"
]
},
{
"root": "13155",
"nets": [
"PHY_RX_ER"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_22",
"closure_a473a0c2_PHY_ordered_escape_22_via_0",
"closure_ae7b6f4e_PHY_RX_ER_carrier_29",
"closure_ae7b6f4e_PHY_RX_ER_carrier_30",
"closure_ae7b6f4e_PHY_RX_ER_carrier_30_via",
"closure_ae7b6f4e_PHY_RX_ER_carrier_30_via_0",
"pcb_smtpad_1004",
"pcb_smtpad_1016",
"pcb_smtpad_986"
],
"required_terminals": [
"pcb_port_1004",
"pcb_port_1016",
"pcb_port_986"
]
},
{
"root": "13075",
"nets": [
"PHY_TXD0"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_23",
"closure_a473a0c2_PHY_ordered_escape_23_via_0",
"closure_ae7b6f4e_PHY_TXD0_carrier_32",
"pcb_smtpad_987",
"pcb_smtpad_993"
],
"required_terminals": [
"pcb_port_987",
"pcb_port_993"
]
},
{
"root": "13076",
"nets": [
"PHY_TXD1"
],
"objects": [
"closure_a473a0c2_PHY_ordered_escape_24",
"closure_a473a0c2_PHY_ordered_escape_24_via_0",
"closure_ae7b6f4e_PHY_TXD1_carrier_33",
"pcb_smtpad_988",
"pcb_smtpad_995"
],
"required_terminals": [
"pcb_port_988",
"pcb_port_995"
]
},
{
"root": "13019",
"nets": [
"RMII1_TX_EN_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_TX_EN_ISO_carrier_54",
"closure_41f0c9f4_RMII1_TX_EN_ISO_carrier_54_via",
"closure_41f0c9f4_RMII1_TX_EN_ISO_carrier_54_via_0",
"closure_41f0c9f4_RMII1_TX_EN_ISO_carrier_54_via_1",
"pcb_smtpad_1293",
"pcb_smtpad_990"
],
"required_terminals": [
"pcb_port_1305",
"pcb_port_990"
]
},
{
"root": "12901",
"nets": [
"RMII1_TXD0_ISO"
],
"objects": [
"closure_78a9aa82_RMII1_TXD0_ISO_carrier_9",
"closure_78a9aa82_RMII1_TXD0_ISO_carrier_9_via",
"closure_78a9aa82_RMII1_TXD0_ISO_carrier_9_via_0",
"closure_78a9aa82_RMII1_TXD0_ISO_carrier_9_via_1",
"pcb_smtpad_1292",
"pcb_smtpad_992"
],
"required_terminals": [
"pcb_port_1304",
"pcb_port_992"
]
},
{
"root": "13004",
"nets": [
"RMII1_TXD1_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_TXD1_ISO_carrier_51",
"closure_41f0c9f4_RMII1_TXD1_ISO_carrier_51_via",
"closure_41f0c9f4_RMII1_TXD1_ISO_carrier_51_via_0",
"closure_41f0c9f4_RMII1_TXD1_ISO_carrier_51_via_1",
"pcb_smtpad_1291",
"pcb_smtpad_994"
],
"required_terminals": [
"pcb_port_1303",
"pcb_port_994"
]
},
{
"root": "13079",
"nets": [
"ETH_MDC_ISO"
],
"objects": [
"closure_ae7b6f4e_ETH_MDC_ISO_carrier_0",
"pcb_smtpad_1314",
"pcb_smtpad_996"
],
"required_terminals": [
"pcb_port_1326",
"pcb_port_996"
]
},
{
"root": "12963",
"nets": [
"RMII1_RXD0_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_RXD0_ISO_carrier_42",
"closure_41f0c9f4_RMII1_RXD0_ISO_carrier_42_via",
"closure_41f0c9f4_RMII1_RXD0_ISO_carrier_42_via_0",
"closure_41f0c9f4_RMII1_RXD0_ISO_carrier_42_via_1",
"pcb_smtpad_1290",
"pcb_smtpad_999"
],
"required_terminals": [
"pcb_port_1302",
"pcb_port_999"
]
},
{
"root": "12978",
"nets": [
"RMII1_RXD1_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_RXD1_ISO_carrier_45",
"closure_41f0c9f4_RMII1_RXD1_ISO_carrier_45_via",
"closure_41f0c9f4_RMII1_RXD1_ISO_carrier_45_via_0",
"closure_41f0c9f4_RMII1_RXD1_ISO_carrier_45_via_1",
"pcb_smtpad_1001",
"pcb_smtpad_1289"
],
"required_terminals": [
"pcb_port_1001",
"pcb_port_1301"
]
},
{
"root": "12941",
"nets": [
"RMII1_CRS_DV_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_CRS_DV_ISO_carrier_36",
"closure_41f0c9f4_RMII1_CRS_DV_ISO_carrier_36_via",
"closure_41f0c9f4_RMII1_CRS_DV_ISO_carrier_36_via_0",
"closure_41f0c9f4_RMII1_CRS_DV_ISO_carrier_36_via_1",
"pcb_smtpad_1003",
"pcb_smtpad_1288"
],
"required_terminals": [
"pcb_port_1003",
"pcb_port_1300"
]
},
{
"root": "12993",
"nets": [
"RMII1_RX_ER_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_RX_ER_ISO_carrier_48",
"closure_41f0c9f4_RMII1_RX_ER_ISO_carrier_48_via",
"closure_41f0c9f4_RMII1_RX_ER_ISO_carrier_48_via_0",
"closure_41f0c9f4_RMII1_RX_ER_ISO_carrier_48_via_1",
"pcb_smtpad_1005",
"pcb_smtpad_1287"
],
"required_terminals": [
"pcb_port_1005",
"pcb_port_1299"
]
},
{
"root": "12952",
"nets": [
"RMII1_REFCLK_ISO"
],
"objects": [
"closure_41f0c9f4_RMII1_REFCLK_ISO_carrier_39",
"closure_41f0c9f4_RMII1_REFCLK_ISO_carrier_39_via",
"closure_41f0c9f4_RMII1_REFCLK_ISO_carrier_39_via_0",
"closure_41f0c9f4_RMII1_REFCLK_ISO_carrier_39_via_1",
"pcb_smtpad_1007",
"pcb_smtpad_1286"
],
"required_terminals": [
"pcb_port_1007",
"pcb_port_1298"
]
},
{
"root": "12777",
"nets": [
"PHY_OSC25"
],
"objects": [
"closure_bb435855_PHY_OSC25_0",
"pcb_smtpad_1028",
"pcb_smtpad_1030"
],
"required_terminals": [
"pcb_port_1028",
"pcb_port_1030"
]
},
{
"root": "1028",
"nets": [],
"objects": [
"pcb_smtpad_1037"
],
"required_terminals": []
},
{
"root": "12784",
"nets": [
"ETH_LED_GREEN_A"
],
"objects": [
"closure_e09a5d32_ETH_LED_GREEN_A_layered_117",
"closure_e09a5d32_ETH_LED_GREEN_A_layered_117_via",
"closure_e09a5d32_ETH_LED_GREEN_A_layered_117_via_0",
"closure_e09a5d32_ETH_LED_GREEN_A_layered_117_via_1",
"pcb_plated_hole_13",
"pcb_smtpad_1061"
],
"required_terminals": [
"pcb_port_1069",
"pcb_port_1075"
]
},
{
"root": "12795",
"nets": [
"ETH_LED_YELLOW_A"
],
"objects": [
"closure_e09a5d32_ETH_LED_YELLOW_A_layered_120",
"closure_e09a5d32_ETH_LED_YELLOW_A_layered_120_via",
"closure_e09a5d32_ETH_LED_YELLOW_A_layered_120_via_0",
"closure_e09a5d32_ETH_LED_YELLOW_A_layered_120_via_1",
"pcb_plated_hole_15",
"pcb_smtpad_1063"
],
"required_terminals": [
"pcb_port_1071",
"pcb_port_1077"
]
},
{
"root": "13036",
"nets": [
"ETH_TX_CT"
],
"objects": [
"closure_48c4415c_bypass_C_ETH_CT_TX_100N_pin1_C_ETH_CT_TX_1U_pin1",
"closure_48c4415c_bypass_C_ETH_CT_TX_100N_pin1_J_ETH_2",
"pcb_plated_hole_5",
"pcb_smtpad_1064",
"pcb_smtpad_1066"
],
"required_terminals": [
"pcb_port_1061",
"pcb_port_1078",
"pcb_port_1080"
]
},
{
"root": "13078",
"nets": [
"ETH_RX_CT"
],
"objects": [
"closure_1badfd88_named_bypass_C_ETH_CT_RX_100N_pin1",
"closure_48c4415c_bypass_C_ETH_CT_RX_100N_pin1_J_ETH_5",
"pcb_plated_hole_8",
"pcb_smtpad_1068",
"pcb_smtpad_1070"
],
"required_terminals": [
"pcb_port_1064",
"pcb_port_1082",
"pcb_port_1084"
]
},
{
"root": "1068",
"nets": [],
"objects": [
"pcb_smtpad_1077"
],
"required_terminals": []
},
{
"root": "1069",
"nets": [],
"objects": [
"pcb_smtpad_1078"
],
"required_terminals": []
},
{
"root": "1071",
"nets": [],
"objects": [
"pcb_smtpad_1080"
],
"required_terminals": []
},
{
"root": "1072",
"nets": [],
"objects": [
"pcb_smtpad_1081"
],
"required_terminals": []
},
{
"root": "13038",
"nets": [
"CHASSIS"
],
"objects": [
"closure_48c4415c_bypass_C_ETH_CHASSIS_pin1_R_ETH_CHASSIS_pin1",
"closure_48c4415c_bypass_J_ETH_8_J_ETH_pin13_internal_1",
"closure_48c4415c_bypass_J_ETH_SH_J_ETH_pin13_internal_1",
"closure_48c4415c_bypass_J_ETH_pin13_internal_1_C_ETH_CHASSIS_pin1",
"pcb_plated_hole_11",
"pcb_plated_hole_16",
"pcb_plated_hole_17",
"pcb_smtpad_1082",
"pcb_smtpad_1084"
],
"required_terminals": [
"pcb_port_1067",
"pcb_port_1072",
"pcb_port_1096",
"pcb_port_1098"
]
},
{
"root": "12778",
"nets": [
"ETH_RAMP_CT"
],
"objects": [
"closure_bb435855_ETH_RAMP_CT_6",
"pcb_smtpad_1271",
"pcb_smtpad_1274"
],
"required_terminals": [
"pcb_port_1283",
"pcb_port_1286"
]
},
{
"root": "1085",
"nets": [],
"objects": [
"pcb_smtpad_1276"
],
"required_terminals": []
},
{
"root": "13275",
"nets": [
"RMII1_TX_EN_DAMPED"
],
"objects": [
"pcb_smtpad_1277",
"resume_lcd_RMII1_TX_EN_DAMPED",
"resume_lcd_RMII1_TX_EN_DAMPED_via",
"resume_lcd_RMII1_TX_EN_DAMPED_via_1",
"source_damping_R_ETH_TX_EN_SRC_damped_pad",
"source_damping_R_ETH_TX_EN_SRC_damped_via",
"source_damping_pcb_smtpad_1339"
],
"required_terminals": [
"pcb_port_1289",
"source_damping_pcb_port_1351"
]
},
{
"root": "13261",
"nets": [
"RMII1_TXD0_DAMPED"
],
"objects": [
"pcb_smtpad_1278",
"resume_lcd_RMII1_TXD0_DAMPED",
"resume_lcd_RMII1_TXD0_DAMPED_via",
"resume_lcd_RMII1_TXD0_DAMPED_via_0",
"resume_lcd_RMII1_TXD0_DAMPED_via_1",
"resume_lcd_RMII1_TXD0_DAMPED_via_2",
"resume_lcd_RMII1_TXD0_DAMPED_via_3",
"source_damping_R_ETH_TXD0_SRC_damped_pad",
"source_damping_R_ETH_TXD0_SRC_damped_via",
"source_damping_pcb_smtpad_1341"
],
"required_terminals": [
"pcb_port_1290",
"source_damping_pcb_port_1353"
]
},
{
"root": "13324",
"nets": [
"RMII1_TXD1_DAMPED"
],
"objects": [
"pcb_smtpad_1279",
"resume_lcd_RMII1_TXD1_DAMPED",
"resume_lcd_RMII1_TXD1_DAMPED_via",
"resume_lcd_RMII1_TXD1_DAMPED_via_0",
"resume_lcd_RMII1_TXD1_DAMPED_via_1",
"resume_lcd_RMII1_TXD1_DAMPED_via_2",
"resume_lcd_RMII1_TXD1_DAMPED_via_3",
"source_damping_R_ETH_TXD1_SRC_damped_pad",
"source_damping_R_ETH_TXD1_SRC_damped_via",
"source_damping_pcb_smtpad_1343"
],
"required_terminals": [
"pcb_port_1291",
"source_damping_pcb_port_1355"
]
},
{
"root": "12779",
"nets": [
"ETH_ISO_OE_N"
],
"objects": [
"closure_bb435855_ETH_ISO_OE_N_7",
"closure_bb435855_ETH_ISO_OE_N_8",
"closure_bb435855_ETH_ISO_OE_N_9",
"pcb_smtpad_1294",
"pcb_smtpad_1316",
"pcb_smtpad_1323",
"pcb_smtpad_1325"
],
"required_terminals": [
"pcb_port_1306",
"pcb_port_1328",
"pcb_port_1335",
"pcb_port_1337"
]
},
{
"root": "1107",
"nets": [],
"objects": [
"pcb_smtpad_1298"
],
"required_terminals": []
},
{
"root": "13197",
"nets": [
"ETH_MDC_DAMPED"
],
"objects": [
"closure_be1cfec0_two_layer_ETH_MDC",
"closure_be1cfec0_two_layer_ETH_MDC_via",
"closure_be1cfec0_two_layer_ETH_MDC_via_0",
"closure_be1cfec0_two_layer_ETH_MDC_via_1",
"closure_c1082fb3_LCD_local_escape_ETH_MDC",
"closure_c1082fb3_LCD_local_escape_ETH_MDC_via_0",
"pcb_smtpad_1300",
"reference_repair_ETH_MDC_via_0",
"reference_repair_ETH_MDC_via_1",
"source_damping_MDC_downstream_rejoin",
"source_damping_R_ETH_MDC_SRC_damped_pad",
"source_damping_R_ETH_MDC_SRC_damped_via",
"source_damping_pcb_smtpad_1345"
],
"required_terminals": [
"pcb_port_1312",
"source_damping_pcb_port_1357"
]
},
{
"root": "1129",
"nets": [],
"objects": [
"pcb_smtpad_1320"
],
"required_terminals": []
},
{
"root": "1159",
"nets": [],
"objects": [
"pg7_pcb_smtpad_0"
],
"required_terminals": []
},
{
"root": "13500",
"nets": [
"PG_LED_SENSE"
],
"objects": [
"pg7_pcb_smtpad_1",
"pg7_pcb_smtpad_14",
"pg7_pcb_smtpad_15",
"pg7_route_isolated_input",
"pg7_route_schmitt_input"
],
"required_terminals": [
"pg7_pcb_port_1",
"pg7_pcb_port_14",
"pg7_pcb_port_15"
]
},
{
"root": "13505",
"nets": [
"PG_LED_K"
],
"objects": [
"pg7_pcb_smtpad_3",
"pg7_pcb_smtpad_5",
"pg7_pcb_smtpad_9",
"pg7_route_sink_bleeder",
"pg7_route_sink_led"
],
"required_terminals": [
"pg7_pcb_port_3",
"pg7_pcb_port_5",
"pg7_pcb_port_9"
]
},
{
"root": "13507",
"nets": [
"PG_LED_A"
],
"objects": [
"pg7_pcb_smtpad_10",
"pg7_pcb_smtpad_6",
"pg7_pcb_smtpad_8",
"pg7_route_anode_bleeder",
"pg7_route_anode_resistor"
],
"required_terminals": [
"pg7_pcb_port_10",
"pg7_pcb_port_6",
"pg7_pcb_port_8"
]
},
{
"root": "14097",
"nets": [
"HDMI_OVDD_3V3"
],
"objects": [
"hdmi_power_trace_final_013_IT_decap_1",
"hdmi_power_trace_final_014_IT_decap_34",
"hdmi_power_trace_final_014_IT_decap_34_via",
"hdmi_power_trace_final_103_distribution_HDMI_OVDD_3V3",
"hdmi_power_trace_final_104_distribution_HDMI_OVDD_3V3",
"hdmi_power_trace_final_104_distribution_HDMI_OVDD_3V3_via",
"hdmi_power_via_final_001",
"hdmi_power_via_final_002",
"hdmi_power_via_final_098",
"hdmi_power_via_final_099",
"pcb_smtpad_hdmi_pcb_smtpad_0",
"pcb_smtpad_hdmi_pcb_smtpad_103",
"pcb_smtpad_hdmi_pcb_smtpad_105",
"pcb_smtpad_hdmi_pcb_smtpad_115",
"pcb_smtpad_hdmi_pcb_smtpad_33"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_0",
"pcb_port_hdmi_pcb_port_103",
"pcb_port_hdmi_pcb_port_105",
"pcb_port_hdmi_pcb_port_115",
"pcb_port_hdmi_pcb_port_33"
]
},
{
"root": "14222",
"nets": [
"HDMI_IVDD_1V2"
],
"objects": [
"hdmi_power_trace_final_008_IT_decap_8",
"hdmi_power_trace_final_009_IT_decap_35",
"hdmi_power_trace_final_010_IT_decap_56",
"hdmi_power_trace_final_093_distribution_HDMI_IVDD_1V2",
"hdmi_power_trace_final_093_distribution_HDMI_IVDD_1V2_via",
"hdmi_power_trace_final_094_distribution_HDMI_IVDD_1V2",
"hdmi_power_trace_final_094_distribution_HDMI_IVDD_1V2_via",
"hdmi_power_trace_final_095_distribution_HDMI_IVDD_1V2",
"hdmi_power_trace_final_095_distribution_HDMI_IVDD_1V2_via",
"hdmi_power_trace_final_096_distribution_HDMI_IVDD_1V2",
"hdmi_power_via_final_081",
"hdmi_power_via_final_082",
"hdmi_power_via_final_083",
"hdmi_power_via_final_084",
"hdmi_power_via_final_085",
"hdmi_power_via_final_086",
"pcb_smtpad_hdmi_pcb_smtpad_117",
"pcb_smtpad_hdmi_pcb_smtpad_34",
"pcb_smtpad_hdmi_pcb_smtpad_55",
"pcb_smtpad_hdmi_pcb_smtpad_7",
"pcb_smtpad_hdmi_pcb_smtpad_71",
"pcb_smtpad_hdmi_pcb_smtpad_75",
"pcb_smtpad_hdmi_pcb_smtpad_77",
"pcb_smtpad_hdmi_pcb_smtpad_79"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_117",
"pcb_port_hdmi_pcb_port_34",
"pcb_port_hdmi_pcb_port_55",
"pcb_port_hdmi_pcb_port_7",
"pcb_port_hdmi_pcb_port_71",
"pcb_port_hdmi_pcb_port_75",
"pcb_port_hdmi_pcb_port_77",
"pcb_port_hdmi_pcb_port_79"
]
},
{
"root": "14353",
"nets": [
"HDMI_3V3"
],
"objects": [
"hdmi_power_pin9_all8_barrel",
"hdmi_power_reserved_U_HDMI_pin9_dogbone",
"hdmi_power_trace_1016_C178_selected_power",
"hdmi_power_trace_final_011_IT_decap_19",
"hdmi_power_trace_final_105_distribution_HDMI_3V3",
"hdmi_power_trace_final_105_distribution_HDMI_3V3_via",
"hdmi_power_trace_final_106_distribution_HDMI_3V3",
"hdmi_power_trace_final_106_distribution_HDMI_3V3_via",
"hdmi_power_trace_final_107_distribution_HDMI_3V3",
"hdmi_power_trace_final_107_distribution_HDMI_3V3_via",
"hdmi_power_trace_final_131_IT_9_join",
"hdmi_power_via_final_100",
"hdmi_power_via_final_101",
"hdmi_power_via_final_102",
"hdmi_power_via_final_103",
"hdmi_power_via_final_104",
"hdmi_power_via_final_105",
"pcb_smtpad_hdmi_pcb_smtpad_119",
"pcb_smtpad_hdmi_pcb_smtpad_12",
"pcb_smtpad_hdmi_pcb_smtpad_18",
"pcb_smtpad_hdmi_pcb_smtpad_8",
"pcb_smtpad_hdmi_pcb_smtpad_83",
"pcb_smtpad_hdmi_pcb_smtpad_85",
"pcb_smtpad_hdmi_pcb_smtpad_87"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_119",
"pcb_port_hdmi_pcb_port_12",
"pcb_port_hdmi_pcb_port_18",
"pcb_port_hdmi_pcb_port_8",
"pcb_port_hdmi_pcb_port_83",
"pcb_port_hdmi_pcb_port_85",
"pcb_port_hdmi_pcb_port_87"
]
},
{
"root": "13695",
"nets": [
"HDMI_HPD"
],
"objects": [
"hdmi_low_speed_HDMI_HPD_0",
"hdmi_low_speed_HDMI_HPD_0_via",
"hdmi_low_speed_HDMI_HPD_0_via_0",
"hdmi_low_speed_HDMI_HPD_1",
"hdmi_low_speed_HDMI_HPD_1_via",
"hdmi_low_speed_HDMI_HPD_1_via_0",
"hdmi_low_speed_HDMI_HPD_1_via_1",
"hdmi_low_speed_HDMI_HPD_2",
"hdmi_low_speed_HDMI_HPD_2_via",
"hdmi_low_speed_HDMI_HPD_2_via_0",
"hdmi_low_speed_HDMI_HPD_2_via_1",
"pcb_smtpad_hdmi_pcb_smtpad_13",
"pcb_smtpad_hdmi_pcb_smtpad_140",
"pcb_smtpad_hdmi_pcb_smtpad_162",
"pcb_smtpad_hdmi_pcb_smtpad_201"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_13",
"pcb_port_hdmi_pcb_port_140",
"pcb_port_hdmi_pcb_port_162",
"pcb_port_hdmi_pcb_port_201"
]
},
{
"root": "13836",
"nets": [
"HDMI_DDC_SDA"
],
"objects": [
"hdmi_low_speed_HDMI_DDC_SDA_0",
"hdmi_low_speed_HDMI_DDC_SDA_1",
"hdmi_low_speed_HDMI_DDC_SDA_1_via",
"hdmi_low_speed_HDMI_DDC_SDA_1_via_0",
"hdmi_low_speed_HDMI_DDC_SDA_1_via_1",
"hdmi_low_speed_HDMI_DDC_SDA_2",
"hdmi_low_speed_HDMI_DDC_SDA_2_via",
"hdmi_low_speed_HDMI_DDC_SDA_2_via_0",
"hdmi_low_speed_HDMI_DDC_SDA_2_via_1",
"pcb_smtpad_hdmi_pcb_smtpad_126",
"pcb_smtpad_hdmi_pcb_smtpad_14",
"pcb_smtpad_hdmi_pcb_smtpad_176",
"pcb_smtpad_hdmi_pcb_smtpad_198"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_126",
"pcb_port_hdmi_pcb_port_14",
"pcb_port_hdmi_pcb_port_176",
"pcb_port_hdmi_pcb_port_198"
]
},
{
"root": "13751",
"nets": [
"HDMI_DDC_SCL"
],
"objects": [
"hdmi_low_speed_HDMI_DDC_SCL_0",
"hdmi_low_speed_HDMI_DDC_SCL_0_via",
"hdmi_low_speed_HDMI_DDC_SCL_0_via_0",
"hdmi_low_speed_HDMI_DDC_SCL_0_via_1",
"hdmi_low_speed_HDMI_DDC_SCL_1",
"hdmi_low_speed_HDMI_DDC_SCL_1_via",
"hdmi_low_speed_HDMI_DDC_SCL_1_via_0",
"hdmi_low_speed_HDMI_DDC_SCL_1_via_1",
"hdmi_low_speed_HDMI_DDC_SCL_2",
"hdmi_low_speed_HDMI_DDC_SCL_2_via",
"hdmi_low_speed_HDMI_DDC_SCL_2_via_0",
"hdmi_low_speed_HDMI_DDC_SCL_2_via_1",
"pcb_smtpad_hdmi_pcb_smtpad_124",
"pcb_smtpad_hdmi_pcb_smtpad_15",
"pcb_smtpad_hdmi_pcb_smtpad_175",
"pcb_smtpad_hdmi_pcb_smtpad_197"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_124",
"pcb_port_hdmi_pcb_port_15",
"pcb_port_hdmi_pcb_port_175",
"pcb_port_hdmi_pcb_port_197"
]
},
{
"root": "13778",
"nets": [
"HDMI_CEC"
],
"objects": [
"hdmi_low_speed_HDMI_CEC_0",
"hdmi_low_speed_HDMI_CEC_1",
"hdmi_low_speed_HDMI_CEC_1_via",
"hdmi_low_speed_HDMI_CEC_1_via_0",
"hdmi_low_speed_HDMI_CEC_1_via_1",
"hdmi_low_speed_HDMI_CEC_2",
"hdmi_low_speed_HDMI_CEC_2_via",
"hdmi_low_speed_HDMI_CEC_2_via_0",
"hdmi_low_speed_HDMI_CEC_2_via_1",
"pcb_smtpad_hdmi_pcb_smtpad_109",
"pcb_smtpad_hdmi_pcb_smtpad_16",
"pcb_smtpad_hdmi_pcb_smtpad_161",
"pcb_smtpad_hdmi_pcb_smtpad_195"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_109",
"pcb_port_hdmi_pcb_port_16",
"pcb_port_hdmi_pcb_port_161",
"pcb_port_hdmi_pcb_port_195"
]
},
{
"root": "14161",
"nets": [
"HDMI_PVCC_1V2"
],
"objects": [
"hdmi_power_trace_final_074_IT_decap_18",
"hdmi_power_trace_final_074_IT_decap_18_via",
"hdmi_power_trace_final_100_distribution_HDMI_PVCC_1V2",
"hdmi_power_trace_final_101_distribution_HDMI_PVCC_1V2",
"hdmi_power_trace_final_101_distribution_HDMI_PVCC_1V2_via",
"hdmi_power_via_final_059",
"hdmi_power_via_final_060",
"hdmi_power_via_final_094",
"hdmi_power_via_final_095",
"pcb_smtpad_hdmi_pcb_smtpad_113",
"pcb_smtpad_hdmi_pcb_smtpad_17",
"pcb_smtpad_hdmi_pcb_smtpad_65",
"pcb_smtpad_hdmi_pcb_smtpad_89"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_113",
"pcb_port_hdmi_pcb_port_17",
"pcb_port_hdmi_pcb_port_65",
"pcb_port_hdmi_pcb_port_89"
]
},
{
"root": "14563",
"nets": [
"HDMI_REXT"
],
"objects": [
"hdmi_power_trace_1014_REXT_original_target",
"hdmi_power_trace_1015_REXT_quiet_inner4",
"hdmi_power_trace_final_135_REXT_escape",
"hdmi_power_via_1013",
"hdmi_power_via_final_133",
"pcb_smtpad_hdmi_pcb_smtpad_133",
"pcb_smtpad_hdmi_pcb_smtpad_19"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_133",
"pcb_port_hdmi_pcb_port_19"
]
},
{
"root": "14079",
"nets": [
"HDMI_TXC_N"
],
"objects": [
"hdmi_tmds_bottom_C_N_stage1",
"hdmi_tmds_bottom_C_N_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_167",
"pcb_smtpad_hdmi_pcb_smtpad_194",
"pcb_smtpad_hdmi_pcb_smtpad_20",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_n_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_n_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_n_it",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_n_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_n_j",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_n_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_txc_n_esd",
"pcb_via_hdmi_tmds_btm_hdmi_txc_n_it",
"pcb_via_hdmi_tmds_btm_hdmi_txc_n_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_167",
"pcb_port_hdmi_pcb_port_194",
"pcb_port_hdmi_pcb_port_20"
]
},
{
"root": "14082",
"nets": [
"HDMI_TXC_P"
],
"objects": [
"hdmi_tmds_bottom_C_P_stage1",
"hdmi_tmds_bottom_C_P_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_168",
"pcb_smtpad_hdmi_pcb_smtpad_192",
"pcb_smtpad_hdmi_pcb_smtpad_21",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_p_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_p_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_p_it",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_p_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_p_j",
"pcb_trace_hdmi_tmds_btm_hdmi_txc_p_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_txc_p_esd",
"pcb_via_hdmi_tmds_btm_hdmi_txc_p_it",
"pcb_via_hdmi_tmds_btm_hdmi_txc_p_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_168",
"pcb_port_hdmi_pcb_port_192",
"pcb_port_hdmi_pcb_port_21"
]
},
{
"root": "14575",
"nets": [
"HDMI_AVCC_1V2"
],
"objects": [
"hdmi_power_trace_1022_reconciled_local_23",
"hdmi_power_trace_1024_reconciled_HDMI_AVCC_1V2",
"hdmi_power_trace_1025_reconciled_HDMI_AVCC_1V2",
"hdmi_power_trace_1025_reconciled_HDMI_AVCC_1V2_via",
"hdmi_power_trace_final_098_distribution_HDMI_AVCC_1V2",
"hdmi_power_trace_final_098_distribution_HDMI_AVCC_1V2_via",
"hdmi_power_via_1026",
"hdmi_power_via_1027",
"hdmi_power_via_final_089",
"hdmi_power_via_final_090",
"pcb_smtpad_hdmi_pcb_smtpad_111",
"pcb_smtpad_hdmi_pcb_smtpad_22",
"pcb_smtpad_hdmi_pcb_smtpad_91",
"pcb_smtpad_hdmi_pcb_smtpad_93",
"pcb_smtpad_hdmi_pcb_smtpad_95"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_111",
"pcb_port_hdmi_pcb_port_22",
"pcb_port_hdmi_pcb_port_91",
"pcb_port_hdmi_pcb_port_93",
"pcb_port_hdmi_pcb_port_95"
]
},
{
"root": "14073",
"nets": [
"HDMI_TX0_N"
],
"objects": [
"bus_lane_HDMI_TX0_N_stage1",
"hdmi_tmds_bottom_0_N_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_169",
"pcb_smtpad_hdmi_pcb_smtpad_191",
"pcb_smtpad_hdmi_pcb_smtpad_23",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_n_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_n_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_n_it",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_n_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_n_j",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_n_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_tx0_n_esd",
"pcb_via_hdmi_tmds_btm_hdmi_tx0_n_it",
"pcb_via_hdmi_tmds_btm_hdmi_tx0_n_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_169",
"pcb_port_hdmi_pcb_port_191",
"pcb_port_hdmi_pcb_port_23"
]
},
{
"root": "14074",
"nets": [
"HDMI_TX0_P"
],
"objects": [
"bus_lane_HDMI_TX0_P_stage1",
"hdmi_tmds_bottom_0_P_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_170",
"pcb_smtpad_hdmi_pcb_smtpad_189",
"pcb_smtpad_hdmi_pcb_smtpad_24",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_p_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_p_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_p_it",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_p_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_p_j",
"pcb_trace_hdmi_tmds_btm_hdmi_tx0_p_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_tx0_p_esd",
"pcb_via_hdmi_tmds_btm_hdmi_tx0_p_it",
"pcb_via_hdmi_tmds_btm_hdmi_tx0_p_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_170",
"pcb_port_hdmi_pcb_port_189",
"pcb_port_hdmi_pcb_port_24"
]
},
{
"root": "14071",
"nets": [
"HDMI_TX1_N"
],
"objects": [
"bus_lane_HDMI_TX1_N_stage1",
"hdmi_tmds_bottom_1_N_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_171",
"pcb_smtpad_hdmi_pcb_smtpad_188",
"pcb_smtpad_hdmi_pcb_smtpad_25",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_n_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_n_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_n_it",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_n_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_n_j",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_n_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_tx1_n_esd",
"pcb_via_hdmi_tmds_btm_hdmi_tx1_n_it",
"pcb_via_hdmi_tmds_btm_hdmi_tx1_n_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_171",
"pcb_port_hdmi_pcb_port_188",
"pcb_port_hdmi_pcb_port_25"
]
},
{
"root": "14072",
"nets": [
"HDMI_TX1_P"
],
"objects": [
"bus_lane_HDMI_TX1_P_stage1",
"hdmi_tmds_bottom_1_P_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_172",
"pcb_smtpad_hdmi_pcb_smtpad_186",
"pcb_smtpad_hdmi_pcb_smtpad_26",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_p_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_p_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_p_it",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_p_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_p_j",
"pcb_trace_hdmi_tmds_btm_hdmi_tx1_p_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_tx1_p_esd",
"pcb_via_hdmi_tmds_btm_hdmi_tx1_p_it",
"pcb_via_hdmi_tmds_btm_hdmi_tx1_p_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_172",
"pcb_port_hdmi_pcb_port_186",
"pcb_port_hdmi_pcb_port_26"
]
},
{
"root": "14543",
"nets": [
"HDMI_DVDD_1V2"
],
"objects": [
"hdmi_power_trace_1023_reconciled_local_28",
"hdmi_power_trace_final_102_distribution_HDMI_DVDD_1V2",
"hdmi_power_trace_final_102_distribution_HDMI_DVDD_1V2_via",
"hdmi_power_trace_final_132_C185_escape",
"hdmi_power_trace_final_133_C185_join",
"hdmi_power_via_final_096",
"hdmi_power_via_final_097",
"hdmi_power_via_final_131",
"pcb_smtpad_hdmi_pcb_smtpad_121",
"pcb_smtpad_hdmi_pcb_smtpad_27",
"pcb_smtpad_hdmi_pcb_smtpad_97",
"pcb_smtpad_hdmi_pcb_smtpad_99"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_121",
"pcb_port_hdmi_pcb_port_27",
"pcb_port_hdmi_pcb_port_97",
"pcb_port_hdmi_pcb_port_99"
]
},
{
"root": "14077",
"nets": [
"HDMI_TX2_N"
],
"objects": [
"bus_lane_HDMI_TX2_N_stage1",
"bus_lane_HDMI_TX2_N_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_173",
"pcb_smtpad_hdmi_pcb_smtpad_185",
"pcb_smtpad_hdmi_pcb_smtpad_28",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_n_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_n_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_n_it",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_n_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_n_j",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_n_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_tx2_n_esd",
"pcb_via_hdmi_tmds_btm_hdmi_tx2_n_it",
"pcb_via_hdmi_tmds_btm_hdmi_tx2_n_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_173",
"pcb_port_hdmi_pcb_port_185",
"pcb_port_hdmi_pcb_port_28"
]
},
{
"root": "14078",
"nets": [
"HDMI_TX2_P"
],
"objects": [
"bus_lane_HDMI_TX2_P_stage1",
"bus_lane_HDMI_TX2_P_stage2",
"pcb_smtpad_hdmi_pcb_smtpad_174",
"pcb_smtpad_hdmi_pcb_smtpad_183",
"pcb_smtpad_hdmi_pcb_smtpad_29",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_p_esd",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_p_esd_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_p_it",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_p_it_via",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_p_j",
"pcb_trace_hdmi_tmds_btm_hdmi_tx2_p_j_via",
"pcb_via_hdmi_tmds_btm_hdmi_tx2_p_esd",
"pcb_via_hdmi_tmds_btm_hdmi_tx2_p_it",
"pcb_via_hdmi_tmds_btm_hdmi_tx2_p_j"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_174",
"pcb_port_hdmi_pcb_port_183",
"pcb_port_hdmi_pcb_port_29"
]
},
{
"root": "14184",
"nets": [
"HDMI_ENTEST"
],
"objects": [
"hdmi_power_trace_final_085_distribution_HDMI_ENTEST",
"hdmi_power_trace_final_085_distribution_HDMI_ENTEST_via",
"hdmi_power_via_final_071",
"hdmi_power_via_final_072",
"pcb_smtpad_hdmi_pcb_smtpad_131",
"pcb_smtpad_hdmi_pcb_smtpad_30"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_131",
"pcb_port_hdmi_pcb_port_30"
]
},
{
"root": "14550",
"nets": [
"HDMI_PCADR"
],
"objects": [
"hdmi_power_trace_1005_PCADR_repaired",
"hdmi_power_trace_1005_PCADR_repaired_via",
"hdmi_power_via_1006",
"hdmi_power_via_1007",
"pcb_smtpad_hdmi_pcb_smtpad_135",
"pcb_smtpad_hdmi_pcb_smtpad_31"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_135",
"pcb_port_hdmi_pcb_port_31"
]
},
{
"root": "13586",
"nets": [
"HDMI_RESET_N"
],
"objects": [
"hdmi_low_speed_HDMI_RESET_N_0",
"hdmi_low_speed_HDMI_RESET_N_1",
"hdmi_low_speed_HDMI_RESET_N_2",
"pcb_smtpad_hdmi_pcb_smtpad_107",
"pcb_smtpad_hdmi_pcb_smtpad_138",
"pcb_smtpad_hdmi_pcb_smtpad_149",
"pcb_smtpad_hdmi_pcb_smtpad_32"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_107",
"pcb_port_hdmi_pcb_port_138",
"pcb_port_hdmi_pcb_port_149",
"pcb_port_hdmi_pcb_port_32"
]
},
{
"root": "1211",
"nets": [
"HDMI_D23"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_35"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_35"
]
},
{
"root": "1212",
"nets": [
"HDMI_D22"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_36"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_36"
]
},
{
"root": "1213",
"nets": [
"HDMI_D21"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_37"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_37"
]
},
{
"root": "1214",
"nets": [
"HDMI_D20"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_38"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_38"
]
},
{
"root": "1215",
"nets": [
"HDMI_D19"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_39"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_39"
]
},
{
"root": "1216",
"nets": [
"HDMI_D18"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_40"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_40"
]
},
{
"root": "1217",
"nets": [
"HDMI_D17"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_41"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_41"
]
},
{
"root": "1218",
"nets": [
"HDMI_D16"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_42"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_42"
]
},
{
"root": "1219",
"nets": [
"HDMI_D15"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_43"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_43"
]
},
{
"root": "1220",
"nets": [
"HDMI_D14"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_44"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_44"
]
},
{
"root": "1221",
"nets": [
"HDMI_D13"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_45"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_45"
]
},
{
"root": "1222",
"nets": [
"HDMI_D12"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_46"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_46"
]
},
{
"root": "1223",
"nets": [
"HDMI_D11"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_47"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_47"
]
},
{
"root": "1224",
"nets": [
"HDMI_D10"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_48"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_48"
]
},
{
"root": "1225",
"nets": [
"HDMI_D9"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_49"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_49"
]
},
{
"root": "1226",
"nets": [
"HDMI_PCLK_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_50"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_50"
]
},
{
"root": "1227",
"nets": [
"HDMI_D8"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_51"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_51"
]
},
{
"root": "1228",
"nets": [
"HDMI_D7"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_52"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_52"
]
},
{
"root": "1229",
"nets": [
"HDMI_D6"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_53"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_53"
]
},
{
"root": "1230",
"nets": [
"HDMI_D5"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_54"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_54"
]
},
{
"root": "1232",
"nets": [
"HDMI_D4"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_56"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_56"
]
},
{
"root": "1233",
"nets": [
"HDMI_D3"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_57"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_57"
]
},
{
"root": "1234",
"nets": [
"HDMI_D2"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_58"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_58"
]
},
{
"root": "1235",
"nets": [
"HDMI_D1"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_59"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_59"
]
},
{
"root": "1236",
"nets": [
"HDMI_D0"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_60"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_60"
]
},
{
"root": "1237",
"nets": [
"HDMI_DE_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_61"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_61"
]
},
{
"root": "1238",
"nets": [
"HDMI_HSYNC_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_62"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_62"
]
},
{
"root": "1239",
"nets": [
"HDMI_VSYNC_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_63"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_63"
]
},
{
"root": "14432",
"nets": [
"HDMI_1V2"
],
"objects": [
"hdmi_power_trace_final_006_LDO_Cout_C145",
"hdmi_power_trace_final_007_LDO_Cout_C146",
"hdmi_power_trace_final_108_distribution_HDMI_1V2",
"hdmi_power_trace_final_108_distribution_HDMI_1V2_via",
"hdmi_power_trace_final_109_distribution_HDMI_1V2",
"hdmi_power_trace_final_109_distribution_HDMI_1V2_via",
"hdmi_power_trace_final_110_distribution_HDMI_1V2",
"hdmi_power_trace_final_110_distribution_HDMI_1V2_via",
"hdmi_power_trace_final_111_distribution_HDMI_1V2",
"hdmi_power_trace_final_111_distribution_HDMI_1V2_via",
"hdmi_power_trace_final_112_distribution_HDMI_1V2",
"hdmi_power_trace_final_112_distribution_HDMI_1V2_via",
"hdmi_power_via_final_106",
"hdmi_power_via_final_107",
"hdmi_power_via_final_108",
"hdmi_power_via_final_109",
"hdmi_power_via_final_110",
"hdmi_power_via_final_111",
"hdmi_power_via_final_112",
"hdmi_power_via_final_113",
"hdmi_power_via_final_114",
"hdmi_power_via_final_115",
"pcb_smtpad_hdmi_pcb_smtpad_112",
"pcb_smtpad_hdmi_pcb_smtpad_114",
"pcb_smtpad_hdmi_pcb_smtpad_118",
"pcb_smtpad_hdmi_pcb_smtpad_122",
"pcb_smtpad_hdmi_pcb_smtpad_145",
"pcb_smtpad_hdmi_pcb_smtpad_67",
"pcb_smtpad_hdmi_pcb_smtpad_69",
"pcb_smtpad_hdmi_pcb_smtpad_73"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_112",
"pcb_port_hdmi_pcb_port_114",
"pcb_port_hdmi_pcb_port_118",
"pcb_port_hdmi_pcb_port_122",
"pcb_port_hdmi_pcb_port_145",
"pcb_port_hdmi_pcb_port_67",
"pcb_port_hdmi_pcb_port_69",
"pcb_port_hdmi_pcb_port_73"
]
},
{
"root": "13793",
"nets": [
"HDMI_CEC_PULLUP"
],
"objects": [
"hdmi_low_speed_HDMI_CEC_PULLUP_0",
"hdmi_low_speed_HDMI_CEC_PULLUP_0_via",
"hdmi_low_speed_HDMI_CEC_PULLUP_0_via_0",
"hdmi_low_speed_HDMI_CEC_PULLUP_0_via_1",
"pcb_smtpad_hdmi_pcb_smtpad_110",
"pcb_smtpad_hdmi_pcb_smtpad_129"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_110",
"pcb_port_hdmi_pcb_port_129"
]
},
{
"root": "14590",
"nets": [
"HDMI_5V"
],
"objects": [
"hdmi_power_trace_1034_TPD5V_output_joint_proposal",
"hdmi_power_trace_1034_TPD5V_output_joint_proposal_via",
"hdmi_power_trace_final_090_distribution_HDMI_5V",
"hdmi_power_trace_final_091_distribution_HDMI_5V",
"hdmi_power_trace_final_092_distribution_HDMI_5V",
"hdmi_power_via_1035",
"hdmi_power_via_1036",
"pcb_smtpad_hdmi_pcb_smtpad_123",
"pcb_smtpad_hdmi_pcb_smtpad_125",
"pcb_smtpad_hdmi_pcb_smtpad_164",
"pcb_smtpad_hdmi_pcb_smtpad_179",
"pcb_smtpad_hdmi_pcb_smtpad_200"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_123",
"pcb_port_hdmi_pcb_port_125",
"pcb_port_hdmi_pcb_port_164",
"pcb_port_hdmi_pcb_port_179",
"pcb_port_hdmi_pcb_port_200"
]
},
{
"root": "14118",
"nets": [
"HDMI_1V2_EN"
],
"objects": [
"hdmi_power_trace_final_027_LDO_EN_C",
"hdmi_power_trace_final_028_LDO_EN_R",
"pcb_smtpad_hdmi_pcb_smtpad_143",
"pcb_smtpad_hdmi_pcb_smtpad_152",
"pcb_smtpad_hdmi_pcb_smtpad_157"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_143",
"pcb_port_hdmi_pcb_port_152",
"pcb_port_hdmi_pcb_port_157"
]
},
{
"root": "1320",
"nets": [],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_144"
],
"required_terminals": []
},
{
"root": "14195",
"nets": [
"HDMI_5V_SUPPLY"
],
"objects": [
"hdmi_power_reserved_TPD_SUPPLY_dogbone",
"hdmi_power_trace_1009_TPD_SUPPLY_inner4",
"hdmi_power_trace_final_002_boost_Cout_primary",
"hdmi_power_trace_final_019_boost_sense_bottom",
"hdmi_power_trace_final_020_boost_Kelvin_sense",
"hdmi_power_trace_final_026_boost_Cout_bulk",
"hdmi_power_trace_final_088_distribution_HDMI_5V_SUPPLY",
"hdmi_power_trace_final_088_distribution_HDMI_5V_SUPPLY_via",
"hdmi_power_via_1008",
"hdmi_power_via_final_005",
"hdmi_power_via_final_077",
"hdmi_power_via_final_078",
"pcb_smtpad_hdmi_pcb_smtpad_163",
"pcb_smtpad_hdmi_pcb_smtpad_177",
"pcb_smtpad_hdmi_pcb_smtpad_265",
"pcb_smtpad_hdmi_pcb_smtpad_268",
"pcb_smtpad_hdmi_pcb_smtpad_274",
"pcb_smtpad_hdmi_pcb_smtpad_276"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_163",
"pcb_port_hdmi_pcb_port_177",
"pcb_port_hdmi_pcb_port_269",
"pcb_port_hdmi_pcb_port_272",
"pcb_port_hdmi_pcb_port_278",
"pcb_port_hdmi_pcb_port_280"
]
},
{
"root": "14610",
"nets": [
"HDMI_UTILITY"
],
"objects": [
"hdmi_low_speed_HDMI_UTILITY_0",
"hdmi_low_speed_HDMI_UTILITY_1",
"hdmi_low_speed_HDMI_UTILITY_1_proposed_extra_via_0",
"hdmi_low_speed_HDMI_UTILITY_1_via",
"hdmi_low_speed_HDMI_UTILITY_1_via_0",
"hdmi_low_speed_HDMI_UTILITY_1_via_1",
"pcb_smtpad_hdmi_pcb_smtpad_165",
"pcb_smtpad_hdmi_pcb_smtpad_181",
"pcb_smtpad_hdmi_pcb_smtpad_196"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_165",
"pcb_port_hdmi_pcb_port_181",
"pcb_port_hdmi_pcb_port_196"
]
},
{
"root": "1378",
"nets": [
"HDMI_RGB_D16"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_202"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_206"
]
},
{
"root": "1380",
"nets": [
"HDMI_RGB_D18"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_204"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_208"
]
},
{
"root": "1381",
"nets": [
"HDMI_RGB_D19"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_205"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_209"
]
},
{
"root": "1382",
"nets": [
"HDMI_D9"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_206"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_210"
]
},
{
"root": "1383",
"nets": [
"HDMI_D17"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_207"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_211"
]
},
{
"root": "1384",
"nets": [
"HDMI_D2"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_208"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_212"
]
},
{
"root": "1385",
"nets": [
"HDMI_D18"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_209"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_213"
]
},
{
"root": "1386",
"nets": [
"HDMI_RGB_D20"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_210"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_214"
]
},
{
"root": "1387",
"nets": [
"HDMI_RGB_D21"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_211"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_215"
]
},
{
"root": "1388",
"nets": [
"HDMI_RGB_D22"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_212"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_216"
]
},
{
"root": "1389",
"nets": [
"HDMI_RGB_D23"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_213"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_217"
]
},
{
"root": "1390",
"nets": [
"HDMI_D0"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_214"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_218"
]
},
{
"root": "1391",
"nets": [
"HDMI_D8"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_215"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_219"
]
},
{
"root": "1392",
"nets": [
"HDMI_D16"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_216"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_220"
]
},
{
"root": "1393",
"nets": [
"HDMI_D1"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_217"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_221"
]
},
{
"root": "1394",
"nets": [
"SYSBOOT15"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_218"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_222"
]
},
{
"root": "1395",
"nets": [
"SYSBOOT3"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_219"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_223"
]
},
{
"root": "1396",
"nets": [
"SYSBOOT7"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_220"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_224"
]
},
{
"root": "1397",
"nets": [
"SYSBOOT11"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_221"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_225"
]
},
{
"root": "1398",
"nets": [
"HDMI_D3"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_222"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_226"
]
},
{
"root": "1399",
"nets": [
"HDMI_D12"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_223"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_227"
]
},
{
"root": "1400",
"nets": [
"HDMI_D22"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_224"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_228"
]
},
{
"root": "1401",
"nets": [
"HDMI_D7"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_225"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_229"
]
},
{
"root": "1402",
"nets": [
"SYSBOOT14"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_226"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_230"
]
},
{
"root": "1403",
"nets": [
"SYSBOOT2"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_227"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_231"
]
},
{
"root": "1404",
"nets": [
"SYSBOOT6"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_228"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_232"
]
},
{
"root": "1405",
"nets": [
"SYSBOOT10"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_229"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_233"
]
},
{
"root": "1406",
"nets": [
"HDMI_D15"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_230"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_234"
]
},
{
"root": "1407",
"nets": [
"HDMI_D11"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_231"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_235"
]
},
{
"root": "1408",
"nets": [
"HDMI_D21"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_232"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_236"
]
},
{
"root": "1409",
"nets": [
"HDMI_D6"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_233"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_237"
]
},
{
"root": "1410",
"nets": [
"SYSBOOT13"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_234"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_238"
]
},
{
"root": "1411",
"nets": [
"SYSBOOT1"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_235"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_239"
]
},
{
"root": "1412",
"nets": [
"SYSBOOT5"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_236"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_240"
]
},
{
"root": "1413",
"nets": [
"SYSBOOT9"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_237"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_241"
]
},
{
"root": "1414",
"nets": [
"HDMI_D14"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_238"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_242"
]
},
{
"root": "1415",
"nets": [
"HDMI_D10"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_239"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_243"
]
},
{
"root": "1416",
"nets": [
"HDMI_D20"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_240"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_244"
]
},
{
"root": "1417",
"nets": [
"HDMI_D5"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_241"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_245"
]
},
{
"root": "1418",
"nets": [
"SYSBOOT12"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_242"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_246"
]
},
{
"root": "1419",
"nets": [
"SYSBOOT0"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_243"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_247"
]
},
{
"root": "1420",
"nets": [
"SYSBOOT4"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_244"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_248"
]
},
{
"root": "1421",
"nets": [
"SYSBOOT8"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_245"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_249"
]
},
{
"root": "1422",
"nets": [
"HDMI_D13"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_246"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_250"
]
},
{
"root": "1423",
"nets": [
"HDMI_D23"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_247"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_251"
]
},
{
"root": "1424",
"nets": [
"HDMI_D19"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_248"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_252"
]
},
{
"root": "1425",
"nets": [
"HDMI_D4"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_249"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_253"
]
},
{
"root": "1426",
"nets": [
"LCD_PCLK"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_250"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_254"
]
},
{
"root": "1427",
"nets": [
"LCD_DE"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_251"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_255"
]
},
{
"root": "1428",
"nets": [
"HDMI_HSYNC"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_252"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_256"
]
},
{
"root": "1429",
"nets": [
"HDMI_VSYNC"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_253"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_257"
]
},
{
"root": "1430",
"nets": [
"HDMI_VSYNC_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_254"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_258"
]
},
{
"root": "1431",
"nets": [
"HDMI_HSYNC_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_255"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_259"
]
},
{
"root": "1432",
"nets": [
"HDMI_DE_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_256"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_260"
]
},
{
"root": "1433",
"nets": [
"HDMI_PCLK_RX"
],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_257"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_261"
]
},
{
"root": "1437",
"nets": [],
"objects": [
"pcb_smtpad_hdmi_pcb_smtpad_261"
],
"required_terminals": []
},
{
"root": "14109",
"nets": [
"HDMI_5V_FB"
],
"objects": [
"hdmi_power_trace_final_016_boost_FB_IC",
"hdmi_power_trace_final_017_boost_FB_bottom",
"hdmi_power_trace_final_018_boost_FB_join",
"hdmi_power_via_final_004",
"pcb_smtpad_hdmi_pcb_smtpad_262",
"pcb_smtpad_hdmi_pcb_smtpad_269",
"pcb_smtpad_hdmi_pcb_smtpad_270"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_266",
"pcb_port_hdmi_pcb_port_273",
"pcb_port_hdmi_pcb_port_274"
]
},
{
"root": "14083",
"nets": [
"HDMI_5V_SW"
],
"objects": [
"hdmi_power_trace_final_001_boost_SW",
"pcb_smtpad_hdmi_pcb_smtpad_264",
"pcb_smtpad_hdmi_pcb_smtpad_267"
],
"required_terminals": [
"pcb_port_hdmi_pcb_port_268",
"pcb_port_hdmi_pcb_port_271"
]
},
{
"root": "1534",
"nets": [],
"objects": [
"pcb_plated_hole_10"
],
"required_terminals": []
},
{
"root": "14621",
"nets": [
"GND"
],
"objects": [
"baseline_pcb_copper_pour_1_1"
],
"required_terminals": []
},
{
"root": "14623",
"nets": [
"GND"
],
"objects": [
"baseline_pcb_copper_pour_1_6"
],
"required_terminals": []
},
{
"root": "14631",
"nets": [
"V1V8"
],
"objects": [
"baseline_rail_region_V1V8_distribution_4"
],
"required_terminals": []
},
{
"root": "14634",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_rail_region_CORE_backside_decoupling_bank_0"
],
"required_terminals": []
},
{
"root": "14636",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_rail_region_CORE_backside_decoupling_bank_2"
],
"required_terminals": []
},
{
"root": "14637",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_rail_region_CORE_backside_decoupling_bank_4"
],
"required_terminals": []
},
{
"root": "14638",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_rail_region_CORE_backside_decoupling_bank_5"
],
"required_terminals": []
},
{
"root": "14639",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_rail_region_CORE_backside_decoupling_bank_6"
],
"required_terminals": []
},
{
"root": "14640",
"nets": [
"VDD_CORE"
],
"objects": [
"baseline_rail_region_CORE_backside_decoupling_bank_7"
],
"required_terminals": []
},
{
"root": "14641",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_0"
],
"required_terminals": []
},
{
"root": "14642",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_1"
],
"required_terminals": []
},
{
"root": "14644",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_4"
],
"required_terminals": []
},
{
"root": "14645",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_6"
],
"required_terminals": []
},
{
"root": "14646",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_7"
],
"required_terminals": []
},
{
"root": "14647",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_8"
],
"required_terminals": []
},
{
"root": "14648",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_9"
],
"required_terminals": []
},
{
"root": "14649",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_10"
],
"required_terminals": []
},
{
"root": "14650",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_12"
],
"required_terminals": []
},
{
"root": "14651",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_CPU_IO_bridge_15"
],
"required_terminals": []
},
{
"root": "14653",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_1"
],
"required_terminals": []
},
{
"root": "14654",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_2"
],
"required_terminals": []
},
{
"root": "14655",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_3"
],
"required_terminals": []
},
{
"root": "14656",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_4"
],
"required_terminals": []
},
{
"root": "14657",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_5"
],
"required_terminals": []
},
{
"root": "14658",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_6"
],
"required_terminals": []
},
{
"root": "14659",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_9"
],
"required_terminals": []
},
{
"root": "14660",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_10"
],
"required_terminals": []
},
{
"root": "14661",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_11"
],
"required_terminals": []
},
{
"root": "14662",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_12"
],
"required_terminals": []
},
{
"root": "14663",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_15"
],
"required_terminals": []
},
{
"root": "14664",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_16"
],
"required_terminals": []
},
{
"root": "14665",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_17"
],
"required_terminals": []
},
{
"root": "14666",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_19"
],
"required_terminals": []
},
{
"root": "14667",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_22"
],
"required_terminals": []
},
{
"root": "14668",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_29"
],
"required_terminals": []
},
{
"root": "14669",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_30"
],
"required_terminals": []
},
{
"root": "14670",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_31"
],
"required_terminals": []
},
{
"root": "14671",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_32"
],
"required_terminals": []
},
{
"root": "14672",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_33"
],
"required_terminals": []
},
{
"root": "14673",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_34"
],
"required_terminals": []
},
{
"root": "14674",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_35"
],
"required_terminals": []
},
{
"root": "14675",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_39"
],
"required_terminals": []
},
{
"root": "14676",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_40"
],
"required_terminals": []
},
{
"root": "14677",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_42"
],
"required_terminals": []
},
{
"root": "14678",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_43"
],
"required_terminals": []
},
{
"root": "14683",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_87"
],
"required_terminals": []
},
{
"root": "14684",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_88"
],
"required_terminals": []
},
{
"root": "14685",
"nets": [
"V3V3"
],
"objects": [
"baseline_rail_region_V3V3_bottom_distribution_90"
],
"required_terminals": []
}
]
}
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