tscircuit/autorouting-dataset-01
This code manages the hardware and electronic components for circuit design and PCB layout, defining components like resistors, capacitors, transistors, connectors, and footprints, and providing tools for component placement, PCB topology, and electrical connections.
- Version
- 1.0.102
- License
- unset
- Stars
- 4
dist/lib/circuit/circuit126/circuit.json
PCB
Schematic
[
{
"type": "source_group",
"source_group_id": "source_group_0",
"is_subcircuit": true,
"was_automatically_named": true,
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_0",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_1",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_0",
"ftype": "simple_resistor",
"name": "resistor-1",
"supplier_part_numbers": {
"jlcpcb": [
"C17513",
"C2907295",
"C25623"
]
},
"resistance": 1000,
"display_resistance": "1kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_2",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_3",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_component",
"source_component_id": "source_component_1",
"ftype": "simple_capacitor",
"name": "capacitor-1",
"supplier_part_numbers": {
"jlcpcb": [
"C49678",
"C28233",
"C1711"
]
},
"capacitance": 1e-7,
"display_capacitance": "0.1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_4",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_5",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_component",
"source_component_id": "source_component_2",
"name": "inductor-1",
"ftype": "simple_inductor",
"inductance": "10uH",
"display_inductance": "10µH",
"supplier_part_numbers": {
"jlcpcb": []
},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_6",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"left",
"1"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_7",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"right",
"2"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_3",
"ftype": "simple_diode",
"name": "diode-1",
"supplier_part_numbers": {
"jlcpcb": []
},
"are_pins_interchangeable": false,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_8",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_9",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"2"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_10",
"name": "pin3",
"pin_number": 3,
"port_hints": [
"pin3",
"3"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_11",
"name": "pin4",
"pin_number": 4,
"port_hints": [
"pin4",
"4"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_12",
"name": "pin5",
"pin_number": 5,
"port_hints": [
"pin5",
"5"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_13",
"name": "pin6",
"pin_number": 6,
"port_hints": [
"pin6",
"6"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_14",
"name": "pin7",
"pin_number": 7,
"port_hints": [
"pin7",
"7"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_15",
"name": "pin8",
"pin_number": 8,
"port_hints": [
"pin8",
"8"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_component",
"source_component_id": "source_component_4",
"ftype": "simple_chip",
"name": "chip-1",
"manufacturer_part_number": "GENERIC",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0"
},
{
"type": "source_net",
"source_net_id": "source_net_0",
"name": "N2",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_net",
"source_net_id": "source_net_1",
"name": "N4",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_net",
"source_net_id": "source_net_2",
"name": "N1",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_net",
"source_net_id": "source_net_3",
"name": "N3",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_net",
"source_net_id": "source_net_4",
"name": "N6",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_net",
"source_net_id": "source_net_5",
"name": "N5",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_net",
"source_net_id": "source_net_6",
"name": "N7",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_board",
"source_board_id": "source_board_0",
"source_group_id": "source_group_0"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "Component resistor-1 has ftype=\"simple_resistor\" but reference designator should start with R",
"source_component_id": "source_component_0",
"refdes": "resistor-1",
"source_component_ftype": "simple_resistor",
"expected_prefixes": [
"R"
],
"actual_prefix": "RESISTOR",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_0"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "Component capacitor-1 has ftype=\"simple_capacitor\" but reference designator should start with C",
"source_component_id": "source_component_1",
"refdes": "capacitor-1",
"source_component_ftype": "simple_capacitor",
"expected_prefixes": [
"C"
],
"actual_prefix": "CAPACITOR",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_1"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "Component inductor-1 has ftype=\"simple_inductor\" but reference designator should start with one of L, FB",
"source_component_id": "source_component_2",
"refdes": "inductor-1",
"source_component_ftype": "simple_inductor",
"expected_prefixes": [
"L",
"FB"
],
"actual_prefix": "INDUCTOR",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_2"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "Component diode-1 has ftype=\"simple_diode\" but reference designator should start with D",
"source_component_id": "source_component_3",
"refdes": "diode-1",
"source_component_ftype": "simple_diode",
"expected_prefixes": [
"D"
],
"actual_prefix": "DIODE",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_3"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "The \"C\" prefix is being used with a <chip />, try using it with a <capacitor />",
"source_component_id": "source_component_4",
"refdes": "chip-1",
"source_component_ftype": "simple_chip",
"expected_prefixes": [
"U",
"IC"
],
"actual_prefix": "CHIP",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_4"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_0",
"connected_source_port_ids": [
"source_port_1"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".resistor-1 > .pin2 to net.N2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_0",
"message": "<trace#3642(from:.resistor-1 > .pin2 to:net.N2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_0",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_1",
"connected_source_port_ids": [
"source_port_0"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".resistor-1 > .pin1 to net.N4",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_1",
"message": "<trace#3643(from:.resistor-1 > .pin1 to:net.N4) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_1",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_2",
"connected_source_port_ids": [
"source_port_3"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".capacitor-1 > .pin2 to net.N1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_2",
"message": "<trace#3644(from:.capacitor-1 > .pin2 to:net.N1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_2",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_3",
"connected_source_port_ids": [
"source_port_2"
],
"connected_source_net_ids": [
"source_net_3"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".capacitor-1 > .pin1 to net.N3",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_3",
"message": "<trace#3645(from:.capacitor-1 > .pin1 to:net.N3) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_3",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_4",
"connected_source_port_ids": [
"source_port_4"
],
"connected_source_net_ids": [
"source_net_4"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".inductor-1 > .pin1 to net.N6",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_4",
"message": "<trace#3646(from:.inductor-1 > .pin1 to:net.N6) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_4",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_5",
"connected_source_port_ids": [
"source_port_5"
],
"connected_source_net_ids": [
"source_net_4"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".inductor-1 > .pin2 to net.N6",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_5",
"message": "<trace#3647(from:.inductor-1 > .pin2 to:net.N6) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_5",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_6",
"connected_source_port_ids": [
"source_port_7"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".diode-1 > .pin2 to net.N2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_6",
"message": "<trace#3648(from:.diode-1 > .pin2 to:net.N2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_6",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_7",
"connected_source_port_ids": [
"source_port_6"
],
"connected_source_net_ids": [
"source_net_3"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".diode-1 > .pin1 to net.N3",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_7",
"message": "<trace#3649(from:.diode-1 > .pin1 to:net.N3) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_7",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_8",
"connected_source_port_ids": [
"source_port_14"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin7 to net.N1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_8",
"message": "<trace#3650(from:.chip-1 > .pin7 to:net.N1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_8",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_9",
"connected_source_port_ids": [
"source_port_11"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin4 to net.N1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_9",
"message": "<trace#3651(from:.chip-1 > .pin4 to:net.N1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_9",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_10",
"connected_source_port_ids": [
"source_port_9"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin2 to net.N2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_10",
"message": "<trace#3652(from:.chip-1 > .pin2 to:net.N2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_10",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_11",
"connected_source_port_ids": [
"source_port_13"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin6 to net.N4",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_11",
"message": "<trace#3653(from:.chip-1 > .pin6 to:net.N4) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_11",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_12",
"connected_source_port_ids": [
"source_port_10"
],
"connected_source_net_ids": [
"source_net_5"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin3 to net.N5",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_12",
"message": "<trace#3654(from:.chip-1 > .pin3 to:net.N5) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_12",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_13",
"connected_source_port_ids": [
"source_port_15"
],
"connected_source_net_ids": [
"source_net_5"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin8 to net.N5",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_13",
"message": "<trace#3655(from:.chip-1 > .pin8 to:net.N5) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_13",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_14",
"connected_source_port_ids": [
"source_port_8"
],
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"source_net_6"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".chip-1 > .pin1 to net.N7",
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},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_14",
"message": "<trace#3656(from:.chip-1 > .pin1 to:net.N7) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_14",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
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"source_port_12"
],
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"source_net_6"
],
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"display_name": ".chip-1 > .pin5 to net.N7",
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},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_15",
"message": "<trace#3657(from:.chip-1 > .pin5 to:net.N7) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_15",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "schematic_component",
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"y": -2.4399999999999995
},
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"height": 0.65
},
"source_component_id": "source_component_0",
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"symbol_name": "boxresistor_right",
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},
{
"type": "schematic_component",
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"y": -4.3999999999999995
},
"size": {
"width": 0.6,
"height": 0.65
},
"source_component_id": "source_component_1",
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"symbol_name": "capacitor_right",
"symbol_display_value": "0.1uF",
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},
{
"type": "schematic_component",
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},
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"height": 0.4599472908242199
},
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"symbol_name": "inductor_right",
"symbol_display_value": "10µH",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_component",
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"center": {
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"y": -6.1899999999999995
},
"size": {
"width": 1.04,
"height": 0.54
},
"source_component_id": "source_component_3",
"is_box_with_pins": true,
"symbol_name": "diode_right",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_4",
"center": {
"x": 0,
"y": 0
},
"rotation": 0,
"size": {
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"height": 1
},
"pin_spacing": 0.2,
"port_labels": {},
"source_component_id": "source_component_4",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_0",
"text": "GENERIC",
"schematic_component_id": "schematic_component_4",
"anchor": "left",
"rotation": 0,
"position": {
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"y": -0.63
},
"color": "#006464",
"font_size": 0.18
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_1",
"text": "chip-1",
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"anchor": "left",
"rotation": 0,
"position": {
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"y": 0.63
},
"color": "#006464",
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},
{
"type": "schematic_group",
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"subcircuit_id": "subcircuit_source_group_0",
"name": "unnamed_board1",
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"y": 0
},
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"height": 0,
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},
{
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"schematic_component_id": "schematic_component_0",
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},
"source_port_id": "source_port_0",
"facing_direction": "left",
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"pin_number": 1,
"display_pin_label": "anode",
"is_connected": true
},
{
"type": "schematic_port",
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"schematic_component_id": "schematic_component_0",
"center": {
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"y": -2.4399999999999995
},
"source_port_id": "source_port_1",
"facing_direction": "right",
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"pin_number": 2,
"display_pin_label": "cathode",
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},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_2",
"schematic_component_id": "schematic_component_1",
"center": {
"x": -0.3,
"y": -4.3999999999999995
},
"source_port_id": "source_port_2",
"facing_direction": "left",
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"pin_number": 1,
"display_pin_label": "pos",
"is_connected": true
},
{
"type": "schematic_port",
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"center": {
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},
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"facing_direction": "right",
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"is_connected": true
},
{
"type": "schematic_port",
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},
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},
{
"type": "schematic_port",
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"y": -2.348754199999999
},
"source_port_id": "source_port_5",
"facing_direction": "right",
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"pin_number": 2,
"display_pin_label": "cathode",
"is_connected": true
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_6",
"schematic_component_id": "schematic_component_3",
"center": {
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"y": -6.1899999999999995
},
"source_port_id": "source_port_6",
"facing_direction": "left",
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"pin_number": 1,
"display_pin_label": "pos",
"is_connected": true
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_7",
"schematic_component_id": "schematic_component_3",
"center": {
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"y": -6.1899999999999995
},
"source_port_id": "source_port_7",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"pin_number": 2,
"display_pin_label": "neg",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_8",
"schematic_component_id": "schematic_component_4",
"center": {
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"y": 0.30000000000000004
},
"source_port_id": "source_port_8",
"facing_direction": "left",
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"side_of_component": "left",
"pin_number": 1,
"true_ccw_index": 0,
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_9",
"schematic_component_id": "schematic_component_4",
"center": {
"x": -0.6000000000000001,
"y": 0.10000000000000003
},
"source_port_id": "source_port_9",
"facing_direction": "left",
"distance_from_component_edge": 0.4,
"side_of_component": "left",
"pin_number": 2,
"true_ccw_index": 1,
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_10",
"schematic_component_id": "schematic_component_4",
"center": {
"x": -0.6000000000000001,
"y": -0.09999999999999998
},
"source_port_id": "source_port_10",
"facing_direction": "left",
"distance_from_component_edge": 0.4,
"side_of_component": "left",
"pin_number": 3,
"true_ccw_index": 2,
"is_connected": true
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_11",
"schematic_component_id": "schematic_component_4",
"center": {
"x": -0.6000000000000001,
"y": -0.30000000000000004
},
"source_port_id": "source_port_11",
"facing_direction": "left",
"distance_from_component_edge": 0.4,
"side_of_component": "left",
"pin_number": 4,
"true_ccw_index": 3,
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_12",
"schematic_component_id": "schematic_component_4",
"center": {
"x": 0.6000000000000001,
"y": -0.30000000000000004
},
"source_port_id": "source_port_12",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 5,
"true_ccw_index": 4,
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_13",
"schematic_component_id": "schematic_component_4",
"center": {
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"y": -0.10000000000000003
},
"source_port_id": "source_port_13",
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"side_of_component": "right",
"pin_number": 6,
"true_ccw_index": 5,
"is_connected": true
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_14",
"schematic_component_id": "schematic_component_4",
"center": {
"x": 0.6000000000000001,
"y": 0.09999999999999998
},
"source_port_id": "source_port_14",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 7,
"true_ccw_index": 6,
"is_connected": true
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_15",
"schematic_component_id": "schematic_component_4",
"center": {
"x": 0.6000000000000001,
"y": 0.30000000000000004
},
"source_port_id": "source_port_15",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 8,
"true_ccw_index": 7,
"is_connected": true
},
{
"type": "schematic_trace",
"schematic_trace_id": "schematic_trace_0",
"source_trace_id": "schematic_port_2-schematic_port_6",
"edges": [
{
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},
"to": {
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},
{
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"to": {
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},
{
"from": {
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},
{
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}
],
"junctions": [],
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
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"source_trace_id": "schematic_port_4-schematic_port_5",
"edges": [
{
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{
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},
{
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},
{
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{
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{
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"to": {
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}
],
"junctions": [],
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "schematic_trace",
"schematic_trace_id": "schematic_trace_2",
"source_trace_id": "schematic_port_0-schematic_port_13",
"edges": [
{
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"to": {
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},
{
"from": {
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},
{
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},
{
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{
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},
{
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{
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],
"junctions": [],
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
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"source_trace_id": "schematic_port_3-schematic_port_14",
"edges": [
{
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{
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{
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{
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{
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],
"junctions": [],
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "schematic_trace",
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"source_trace_id": "schematic_port_10-schematic_port_15",
"edges": [
{
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{
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{
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{
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{
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],
"junctions": [],
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"x": 0,
"y": 6,
"z": -0.7
},
"rotation": {
"x": 0,
"y": 180,
"z": 0
},
"pcb_component_id": "pcb_component_0",
"source_component_id": "source_component_0",
"model_origin_alignment": "center_of_component_on_board_surface",
"anchor_alignment": "center_of_component_on_board_surface",
"footprinter_string": "res0805"
},
{
"type": "cad_component",
"cad_component_id": "cad_component_1",
"position": {
"x": 2,
"y": -4,
"z": -0.7
},
"rotation": {
"x": 0,
"y": 180,
"z": 0
},
"pcb_component_id": "pcb_component_1",
"source_component_id": "source_component_1",
"model_origin_alignment": "center_of_component_on_board_surface",
"anchor_alignment": "center_of_component_on_board_surface",
"footprinter_string": "cap0805"
},
{
"type": "cad_component",
"cad_component_id": "cad_component_2",
"position": {
"x": -6,
"y": 0,
"z": 0.7
},
"rotation": {
"x": 0,
"y": 0,
"z": 0
},
"pcb_component_id": "pcb_component_2",
"source_component_id": "source_component_2",
"model_origin_alignment": "center_of_component_on_board_surface",
"anchor_alignment": "center_of_component_on_board_surface",
"footprinter_string": "0603"
},
{
"type": "cad_component",
"cad_component_id": "cad_component_3",
"position": {
"x": 2,
"y": 6,
"z": 0.7
},
"rotation": {
"x": 0,
"y": 0,
"z": 90
},
"pcb_component_id": "pcb_component_3",
"source_component_id": "source_component_3",
"model_origin_alignment": "center_of_component_on_board_surface",
"anchor_alignment": "center_of_component_on_board_surface",
"footprinter_string": "sod323"
},
{
"type": "cad_component",
"cad_component_id": "cad_component_4",
"position": {
"x": 0,
"y": -0.9999999999999996,
"z": 0.7
},
"rotation": {
"x": 0,
"y": 0,
"z": 45
},
"pcb_component_id": "pcb_component_4",
"source_component_id": "source_component_4",
"model_origin_alignment": "center_of_component_on_board_surface",
"anchor_alignment": "center_of_component_on_board_surface",
"footprinter_string": "pinrow8"
},
{
"type": "pcb_courtyard_overlap_error",
"pcb_error_id": "pcb_courtyard_overlap_pcb_component_3_pcb_component_4",
"error_type": "pcb_courtyard_overlap_error",
"message": "Courtyard of diode-1 overlaps with courtyard of chip-1",
"pcb_component_ids": [
"pcb_component_3",
"pcb_component_4"
],
"pcb_courtyard_overlap_error_id": "pcb_courtyard_overlap_error_0"
},
{
"type": "source_component_pins_underspecified_warning",
"source_component_pins_underspecified_warning_id": "source_component_pins_underspecified_warning_0",
"warning_type": "source_component_pins_underspecified_warning",
"message": "All pins on chip-1 are underspecified (no pinAttributes set)",
"source_component_id": "source_component_4",
"source_port_ids": [
"source_port_8",
"source_port_9",
"source_port_10",
"source_port_11",
"source_port_12",
"source_port_13",
"source_port_14",
"source_port_15"
],
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_no_power_pin_defined_warning",
"source_no_power_pin_defined_warning_id": "source_no_power_pin_defined_warning_0",
"warning_type": "source_no_power_pin_defined_warning",
"message": "chip-1 has no pin with requires_power=true",
"source_component_id": "source_component_4",
"source_port_ids": [
"source_port_8",
"source_port_9",
"source_port_10",
"source_port_11",
"source_port_12",
"source_port_13",
"source_port_14",
"source_port_15"
],
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_no_ground_pin_defined_warning",
"source_no_ground_pin_defined_warning_id": "source_no_ground_pin_defined_warning_0",
"warning_type": "source_no_ground_pin_defined_warning",
"message": "chip-1 has no pin with requires_ground=true",
"source_component_id": "source_component_4",
"source_port_ids": [
"source_port_8",
"source_port_9",
"source_port_10",
"source_port_11",
"source_port_12",
"source_port_13",
"source_port_14",
"source_port_15"
],
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_project_metadata",
"source_filesystem_md5_hash": "3fbdf5adbcca5810255d1c815ce964f6"
}
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