shibosoftwaredev/f1c100s-linux-nema8-stepper-controller
Restores component part numbers and CAD models, removes test-point 3D bodies, and validates that solder paste exists only on top-side SMT pads without altering copper or DRC.
- Version
- 0.3.5
- License
- unset
- Stars
- 0
work/build-fixed-board-traces.mjs
import { readFile, writeFile } from "node:fs/promises"
const cache = JSON.parse(await readFile(
".tscircuit/cache/ec26294d87-4c02c8b3893cff2d8cf98fdf1f5b7767.json",
"utf8",
))
const movePrimaryLdoEndpoint = (point) => {
if (point.route_type !== "wire") return point
const at = (x, y) => Math.abs(point.x - x) < 1e-6 && Math.abs(point.y - y) < 1e-6
if (at(-23.475, 10.905)) return { ...point, x: -22.3, y: 8.05 }
if (at(-18.525, 7.095)) return { ...point, x: -19.7, y: 9.95 }
if (at(-18.525, 8.365) || at(-18.525, 9.635)) return { ...point, x: -19.7, y: 9 }
if (at(-18.525, 10.905)) return { ...point, x: -19.7, y: 8.05 }
return point
}
const wire = (x, y, width = 0.12, layer = "top") => ({ route_type: "wire", x, y, width, layer })
const via = (x, y) => ({ route_type: "via", x, y, from_layer: "top", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 })
const primaryLdoRoutes = {
"source_trace_124__source_trace_178__source_net_1_mst1_0": [
wire(-16.1125, 10.905), wire(-19.7, 8.05),
],
"source_trace_124__source_trace_178__source_net_1_mst2_0": [
wire(-19.7, 9.95), wire(-18.7, 9.95), wire(-16.1125, 10.905),
],
"source_trace_126__source_trace_131__source_trace_139__source_trace_147__source_trace_160__source_trace_256__source_net_2_mst10_0": [
wire(-25.8875, 10.905), wire(-22.3, 8.05),
],
"source_trace_126__source_trace_131__source_trace_139__source_trace_147__source_trace_160__source_trace_256__source_net_2_mst22_0": [
wire(-22.3, 8.05), wire(-23, 7.2), wire(-23, 5.5), wire(-21.5, 4),
wire(-20.5, 3), wire(-19.7, 2.2), wire(-19.7, 0.95),
],
"source_net_0_mst23_0": [
wire(-19.7, 9, 0.3), via(-19.7, 9), wire(-19.7, 9, 0.3, "bottom"),
wire(-14.8, 11.6, 0.3, "bottom"), via(-14.8, 11.6), wire(-14.8, 11.6, 0.3),
wire(-14.2875, 10.905, 0.3),
],
"source_net_0_mst37_0": [
wire(-19.7, 9, 0.3), via(-19.7, 9), wire(-19.7, 9, 0.3, "bottom"),
wire(-19.7, 2.5, 0.3, "bottom"), wire(-20.1, 2.1, 0.3, "bottom"),
wire(-20.1, 0, 0.3, "bottom"), wire(-19.7, 0, 0.3, "bottom"),
via(-19.7, 0), wire(-19.7, 0, 0.3),
],
"source_net_0_mst39_0": [
wire(-19.7, 9, 0.3), via(-19.7, 9), wire(-19.7, 9, 0.3, "bottom"),
wire(-27.7125, 10.905, 0.3, "bottom"), via(-27.7125, 10.905), wire(-27.7125, 10.905, 0.3),
],
}
const traces = cache.traces
.filter((trace) => trace.pcb_trace_id !== "source_net_0_mst0_0")
.map((cachedTrace) => {
const trace = { ...cachedTrace, route: cachedTrace.route.map(movePrimaryLdoEndpoint) }
const localReplacement = primaryLdoRoutes[trace.pcb_trace_id]
if (localReplacement) return { ...trace, route: localReplacement }
const connection = trace.source_trace_id ?? trace.connection_name
if (connection === "source_trace_244") {
return {
...trace,
route: trace.route.flatMap((point, index, route) => {
const next = route[index + 1]
if (point.route_type === "wire" && point.layer === "inner1" &&
Math.abs(point.x - 37.99995495235459) < 1e-6 && point.y < -10 &&
next?.route_type === "wire" && next.layer === "inner1" &&
next.y > -5) {
return [point,
{ route_type: "wire", x: 37.99995495235459, y: -6.4, width: 0.12, layer: "inner1" },
{ route_type: "wire", x: 37.2, y: -5.9, width: 0.12, layer: "inner1" },
{ route_type: "wire", x: 37.2, y: -4.5, width: 0.12, layer: "inner1" },
]
}
return point
}),
}
}
if (connection !== "source_trace_212") return trace
return {
...trace,
route: [
{ route_type: "wire", x: 37.89, y: -5.2, width: 0.12, layer: "top" },
{ route_type: "via", x: 37.89, y: -5.2, from_layer: "top", to_layer: "bottom", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 37.89, y: -5.2, width: 0.12, layer: "bottom" },
{ route_type: "wire", x: 36.074936, y: -2.865755, width: 0.12, layer: "bottom" },
{ route_type: "via", x: 36.074936, y: -2.865755, from_layer: "bottom", to_layer: "top", via_diameter: 0.45, via_hole_diameter: 0.3 },
{ route_type: "wire", x: 36.074936, y: -2.865755, width: 0.12, layer: "top" },
],
}
})
.map((trace) => {
const connection = trace.source_trace_id ?? trace.connection_name
const startId = trace.route[0]?.start_pcb_port_id
const endId = trace.route.at(-1)?.end_pcb_port_id
const endpoint = (point, which) => ({ ...point,
...(which === "start" && startId ? { start_pcb_port_id: startId } : {}),
...(which === "end" && endId ? { end_pcb_port_id: endId } : {}),
})
const highCurrentRoutes = {
// Route over the blocking diode's cathode pad rather than through it.
source_trace_193: [
endpoint(wire(34.4375, 11.3, 0.8), "start"),
wire(34.4375, 13, 0.8), wire(39.692402, 13, 0.8),
endpoint(wire(39.692402, 11.2, 0.8), "end"),
],
}
if (highCurrentRoutes[connection]) return { ...trace, route: highCurrentRoutes[connection] }
if (["source_trace_244", "source_trace_245", "source_trace_246", "source_trace_247"].includes(connection)) {
const neckEndY = -7
const fullWidthY = -7.2
const route = []
for (let i = 0; i < trace.route.length; i++) {
const point = trace.route[i]
route.push(point.route_type === "wire"
? { ...point, width: point.y <= fullWidthY ? 0.3 : 0.12 }
: point)
const next = trace.route[i + 1]
if (point.route_type !== "wire" || next?.route_type !== "wire" || point.layer !== next.layer) continue
const atY = (y, width) => ({ ...point, x: point.x + (next.x - point.x) * ((y - point.y) / (next.y - point.y)), y, width })
if (point.y > neckEndY && next.y < fullWidthY) {
route.push(atY(neckEndY, 0.12), atY(fullWidthY, 0.3))
} else if (point.y < fullWidthY && next.y > neckEndY) {
route.push(atY(fullWidthY, 0.3), atY(neckEndY, 0.12))
}
}
const separatedRoute = connection === "source_trace_245"
? route.map((point) => point.route_type === "wire" && point.layer === "bottom" &&
point.y <= fullWidthY && point.y > -21
? { ...point, x: 40.6 }
: point)
: route
return { ...trace, route: separatedRoute }
}
const requestedWidth = {
// Widen just the diode-to-bulk-capacitor branch of the merged VMOTOR tree.
source_trace_204__source_trace_206__source_net_47_mst4_0: 0.8,
}[trace.pcb_trace_id]
if (!requestedWidth) return trace
return {
...trace,
route: trace.route.map((point) => point.route_type === "wire"
? { ...point, width: requestedWidth }
: point),
}
})
await writeFile("saved-board-traces.json", `${JSON.stringify(traces, null, 2)}\n`)
console.log(`saved ${traces.length} deterministic board traces`)
