shibosoftwaredev/f1c100s-linux-nema8-stepper-controller
Restores component part numbers and CAD models, removes test-point 3D bodies, and validates that solder paste exists only on top-side SMT pads without altering copper or DRC.
- Version
- 0.3.5
- License
- unset
- Stars
- 0
fixed-board-router.ts
import frozenCircuit from "./frozen-electrical-circuit.json"
const wire = (
x: number,
y: number,
width = 0.15,
layer = "top",
endpoint: Record<string, string> = {},
) => ({ route_type: "wire", x, y, width, layer, ...endpoint })
const via = (x: number, y: number, from_layer: string, to_layer: string) => ({
route_type: "via",
x,
y,
from_layer,
to_layer,
via_diameter: 0.45,
via_hole_diameter: 0.3,
})
/**
* The full-board autorouter result is frozen here so local and website builds
* are deterministic. A few short routes are replaced below to remove the last
* post-autorouter clearance defects around the USB-PD switch, W5500, and
* DRV8825 reference divider. Every via is explicitly 0.30 mm drill / 0.45 mm
* pad.
*/
export async function fixedBoardRouter(input: any) {
const handlers: Record<string, Array<(event: any) => void>> = {
complete: [], error: [], progress: [],
}
let isRouting = false
return {
input,
get isRouting() { return isRouting },
on(event: string, handler: (event: any) => void) {
handlers[event]?.push(handler)
},
start() {
isRouting = true
queueMicrotask(() => {
if (!isRouting) return
isRouting = false
const frozenDirectTraces = new Set(["pcb_trace_3", "pcb_trace_5", "pcb_trace_10", "pcb_trace_17", "pcb_trace_32"])
const traces = (frozenCircuit as any[])
.filter((element) =>
element.type === "pcb_trace" &&
element.subcircuit_id === "subcircuit_source_group_19" &&
(!/^pcb_trace_\d+$/.test(element.pcb_trace_id) || frozenDirectTraces.has(element.pcb_trace_id)))
.map((trace) => {
if (frozenDirectTraces.has(trace.pcb_trace_id)) return {
...trace,
pcb_trace_id: `frozen_${trace.pcb_trace_id}`,
}
if (trace.pcb_trace_id === "source_net_50_mst2_0") return {
...trace,
route: [
...trace.route.slice(0, 10),
wire(38.2, 5.8, 0.15, "inner1"),
via(38.2, 5.8, "inner1", "top"), wire(38.2, 5.8),
wire(38.49, 5, 0.15, "top", { end_pcb_port_id: "pcb_port_569" }),
],
}
if (trace.pcb_trace_id === "source_trace_391__source_trace_392__source_trace_397__source_net_5_mst4_0") return {
...trace,
route: [
wire(-24.250062, -18.750072, 0.15, "top", { start_pcb_port_id: "pcb_port_298" }),
wire(-24.250062, -17.65),
via(-24.250062, -17.65, "top", "inner1"),
wire(-24.250062, -17.65, 0.15, "inner1"),
wire(-25.749932, -17.65, 0.15, "inner1"),
via(-25.749932, -17.65, "inner1", "top"),
wire(-25.749932, -17.65),
wire(-25.749932, -18.750072, 0.15, "top", { end_pcb_port_id: "pcb_port_301" }),
],
}
if (trace.pcb_trace_id === "source_trace_169__source_trace_369__source_trace_399__source_trace_401__source_net_0_mst25_0") {
const turnIndex = trace.route.findIndex((point: any) =>
point.x === -24.304871794871797 && point.y === -17.08974358974359)
return {
...trace,
route: [
...trace.route.slice(0, turnIndex + 1),
wire(-24.75, -17.2, 0.12),
wire(-24.749934, -18.750072, 0.12, "top", { end_pcb_port_id: "pcb_port_299" }),
],
}
}
if (trace.pcb_trace_id === "source_trace_169__source_trace_369__source_trace_399__source_trace_401__source_net_0_mst36_0") {
const turnIndex = trace.route.findIndex((point: any) =>
point.x === -24.304871794871797 && point.y === -17.08974358974359)
return {
...trace,
route: [
wire(-24.749934, -18.750072, 0.12, "top", { start_pcb_port_id: "pcb_port_299" }),
wire(-24.75, -17.2, 0.12),
wire(-24.304871794871797, -17.08974358974359, 0.12),
...trace.route.slice(turnIndex + 1),
],
}
}
if (trace.pcb_trace_id === "source_trace_86__source_trace_97__source_trace_107__source_trace_386__source_trace_387_mst4_0") return {
...trace,
route: [
...trace.route.slice(0, 8),
wire(0.5, 21.875, 0.8, "bottom"),
wire(5, 21.875, 0.8, "bottom"),
wire(5, 23.346486046910684, 0.8, "bottom"),
wire(10.299477504694808, 23.346486046910684, 0.8, "bottom"),
...trace.route.slice(15),
],
}
if (trace.pcb_trace_id === "source_net_50_mst3_0") return {
...trace,
route: [
wire(38.49, 5, 0.15, "top", { start_pcb_port_id: "pcb_port_569" }),
wire(38.2, 5.8),
wire(38.2, 5.8, 0.15, "inner1"),
...trace.route.slice(5),
],
}
// The right edge is 5 mm tighter in revision D. Keep the dense
// frozen routing intact and replace only the five branches whose
// endpoints moved with the TVS and motor bulk capacitor.
if (trace.pcb_trace_id === "source_trace_323__source_trace_325__source_net_49_mst8_0") return {
...trace,
route: [
wire(39.692402, 11.2, 0.12, "top", { start_pcb_port_id: "pcb_port_494" }),
wire(40.5, 14.2), wire(47.15, 14.2),
wire(47.15, 12.2, 0.12, "top", { end_pcb_port_id: "pcb_port_496" }),
],
}
if (trace.pcb_trace_id === "source_trace_169__source_trace_369__source_trace_399__source_trace_401__source_net_0_mst62_0") return {
...trace,
route: [
wire(42.85, 12.2, 0.12, "top", { start_pcb_port_id: "pcb_port_497" }),
wire(42.85, 10.9),
wire(40.4625, 8.5, 0.12, "top", { end_pcb_port_id: "pcb_port_501" }),
],
}
if (trace.pcb_trace_id === "source_trace_169__source_trace_369__source_trace_399__source_trace_401__source_net_0_mst71_0") return {
...trace,
route: [
wire(48.1125, 23.05, 0.12, "top", { start_pcb_port_id: "pcb_port_459" }),
wire(49, 22.2), wire(49, 9.5), wire(42.85, 9.5),
wire(42.85, 12.2, 0.12, "top", { end_pcb_port_id: "pcb_port_497" }),
],
}
if (trace.pcb_trace_id === "source_trace_323__source_trace_325__source_net_49_mst6_0") return {
...trace,
route: [
wire(47, -1.352419, 0.12, "top", { start_pcb_port_id: "pcb_port_499" }),
wire(47, -4.667), wire(45.986, -4.667),
...trace.route.slice(3),
],
}
if (trace.pcb_trace_id === "source_trace_169__source_trace_369__source_trace_399__source_trace_401__source_net_0_mst63_0") return {
...trace,
route: [
wire(47, 5.352419, 0.12, "top", { start_pcb_port_id: "pcb_port_498" }),
wire(49, 7.35), wire(49, 9.5), wire(42.85, 9.5),
wire(42.85, 12.2, 0.12, "top", { end_pcb_port_id: "pcb_port_497" }),
],
}
if (trace.pcb_trace_id === "source_trace_197__source_trace_395_mst0_0") return {
...trace,
route: [
wire(-23.250064, -18.750072, 0.12, "top", { start_pcb_port_id: "pcb_port_296" }),
wire(-23.26148500146501, -18.220138634873294, 0.12),
wire(-23.26148500146501, -18.220138634873294, 0.12, "inner2"),
wire(-23.5, -16.7, 0.12, "inner2"),
via(-23.5, -16.7, "inner2", "top"), wire(-23.5, -16.7, 0.12),
wire(-23.5, -17.01, 0.12, "top", { end_pcb_port_id: "pcb_port_381" }),
],
}
return trace
})
handlers.complete.forEach((handler) => handler({ type: "complete", traces }))
})
},
stop() { isRouting = false },
solveSync() {
throw new Error("fixedBoardRouter requires start()")
},
}
}
