shibosoftwaredev/f1c100s-linux-nema8-stepper-controller

ethernet.tsx

import { W5500 } from "./imports/W5500"
import { HR911105A } from "./imports/HR911105A"
import { X322525MSB4SI } from "./imports/X322525MSB4SI"

const wire = (name: string, from: string, to: string, thickness = 0.15) =>
  <trace name={name} from={from} to={to} thickness={thickness} />

const resistor = (name: string, value: string, lcsc: string, x: number, y: number, rotation = 0, schX = x, schY = y) =>
  <resistor name={name} resistance={value} footprint="0402"
    supplierPartNumbers={{jlcpcb:[lcsc]}} pcbX={x} pcbY={y} pcbRotation={rotation} schX={schX} schY={schY} />

const bypass = (name: string, x: number, y: number, schX: number, schY: number) => <>
  <capacitor name={name} capacitance="100nF" maxVoltageRating={16} footprint="0402"
    supplierPartNumbers={{jlcpcb:["C1525"]}} pcbX={x} pcbY={y} schX={schX} schY={schY} />
  {wire(`${name}_VDD`, `.${name} > .pin1`, "net.ETH_3V3")}
  {wire(`${name}_GND`, `.${name} > .pin2`, "net.BOARD_GND")}
</>

/** W5500 gives the Linux system a deterministic 10/100 Ethernet interface over SPI1. */
export function EthernetSection() {
  const powerPins = [4,8,11,15,17,21,28]
  const groundPins = [3,9,14,16,19,29,48]
  return <group name="ETHERNET" pcbX={0} pcbY={0} schX={27} schY={22} schSheetName="ethernet">
    <HR911105A name="J_ETH" pcbX={-5.5} pcbY={-24.5} pcbRotation={0}
      schX={-39} schY={-25}
      noConnect={["NC","pin8","pin9","pin10","pin11","pin12"]} />
    <W5500 name="U_ETH" pcbX={-23.5} pcbY={-23} pcbRotation={180}
      schX={-27} schY={-25} schWidth={6} schHeight={9}
      noConnect={["DNC","VBG","SPDLED","LINKLED","DUPLED","ACTLED","RSVD2","RSVD3","RSVD4","RSVD5","RSVD6"]} />

    {/* A ferrite bead isolates PHY switching current from the SoC rail. */}
    <chip name="FB_ETH" manufacturerPartNumber="BLM18AG601SN1D"
      supplierPartNumbers={{jlcpcb:["C19330"]}} footprint="0603"
      pinLabels={{pin1:"V3V3",pin2:"ETH_3V3"}} pcbX={-29.5} pcbY={-14.5} schX={-42} schY={-13} />
    {wire("ETH_BEAD_IN", ".FB_ETH > .pin1", "net.V3V3", 0.3)}
    {wire("ETH_BEAD_OUT", ".FB_ETH > .pin2", "net.ETH_3V3", 0.3)}
    <capacitor name="C_ETH_BULK" capacitance="4.7uF" maxVoltageRating={25} footprint="0805"
      manufacturerPartNumber="CL21A475KAQNNNE" supplierPartNumbers={{jlcpcb:["C1779"]}}
      pcbX={-25.5} pcbY={-14.5} schX={-36} schY={-13} />
    {wire("ETH_BULK_VDD", ".C_ETH_BULK > .pin1", "net.ETH_3V3", 0.3)}
    {wire("ETH_BULK_GND", ".C_ETH_BULK > .pin2", "net.BOARD_GND", 0.3)}

    {/* The W5500 is a 0.5 mm-pitch QFN; 0.15 mm escapes preserve clearance
        between alternating AVDD/AGND pins before widening into the planes. */}
    {powerPins.map(pin => wire(`ETH_POWER_${pin}`, `.U_ETH > .pin${pin}`, "net.ETH_3V3", 0.15))}
    {groundPins.map(pin => wire(`ETH_GROUND_${pin}`, `.U_ETH > .pin${pin}`, "net.BOARD_GND", 0.15))}
    {/* Escape the alternating corner supplies to different internal layers. This
        is the normal four-layer QFN solution and preserves 0.10 mm clearance. */}
    <trace name="ETH_AVDD_CORNER" from=".U_ETH > .pin4" to=".U_ETH > .pin45" thickness={0.15}
      pcbPath={[".U_ETH > .pin4",
        {x:-1.25,y:-3.4,via:true,fromLayer:"top",toLayer:"inner1"},
        {x:-3.4,y:-1.25,via:true,fromLayer:"inner1",toLayer:"top"},
        ".U_ETH > .pin45"]} />
    <trace name="ETH_AGND_CORNER" from=".U_ETH > .pin3" to=".U_ETH > .pin48" thickness={0.15}
      pcbPath={[".U_ETH > .pin3",
        {x:-1.75,y:-2.9,via:true,fromLayer:"top",toLayer:"inner2"},
        {x:-2.9,y:-2.75,via:true,fromLayer:"inner2",toLayer:"top"},
        ".U_ETH > .pin48"]} />
    {bypass("C_ETH_1", -27, -17, -35, -32)}
    {bypass("C_ETH_2", -22, -15.5, -31, -32)}
    {bypass("C_ETH_3", -22, -17, -27, -32)}
    {bypass("C_ETH_4", -27, -29, -23, -32)}
    {bypass("C_ETH_5", -29, -30, -19, -32)}
    {bypass("C_ETH_6", -19, -29, -15, -32)}
    {bypass("C_ETH_7", -17, -29, -11, -32)}

    {/* Datasheet reference, regulator and oscillator support. */}
    {resistor("R_ETH_EXRES", "12.4k", "C11692", -25.5, -16, 0, -30, -13)}
    <trace name="ETH_EXRES" from=".U_ETH > .EXRES1" to=".R_ETH_EXRES > .pin1"
      thickness={0.15}
      pcbPath={[".U_ETH > .EXRES1", {x:1.75,y:-6}, ".R_ETH_EXRES > .pin1"]} />
    {wire("ETH_EXRES_GND", ".R_ETH_EXRES > .pin2", "net.BOARD_GND")}
    <capacitor name="C_ETH_TOCAP" capacitance="4.7uF" maxVoltageRating={25} footprint="0805"
      manufacturerPartNumber="CL21A475KAQNNNE" supplierPartNumbers={{jlcpcb:["C1779"]}}
      pcbX={-30} pcbY={-21} pcbRotation={90} schX={-31} schY={-15} />
    {wire("ETH_TOCAP", ".U_ETH > .TOCAP", ".C_ETH_TOCAP > .pin1")}
    {wire("ETH_TOCAP_GND", ".C_ETH_TOCAP > .pin2", "net.BOARD_GND")}
    <capacitor name="C_ETH_1V2" capacitance="10nF" maxVoltageRating={50} footprint="0402"
      maxDecouplingTraceLength={2}
      supplierPartNumbers={{jlcpcb:["C15195"]}} pcbX={-29.1} pcbY={-25} pcbRotation={270} schX={-26} schY={-15} />
    <trace name="ETH_1V2" from=".U_ETH > .pin22" to=".C_ETH_1V2 > .pin1"
      thickness={0.12} maxLength={2} />
    <trace name="ETH_1V2_GND" from=".C_ETH_1V2 > .pin2" to=".U_ETH > .pin23"
      thickness={0.12} maxLength={2} />
    {wire("ETH_RSVD1_GND", ".U_ETH > .pin23", "net.BOARD_GND")}

    <X322525MSB4SI name="Y_ETH" loadCapacitance="20pF" pcbX={-23.5} pcbY={-33} pcbRotation={270}
      schX={-21} schY={-15} />
    <capacitor name="C_ETH_XI" capacitance="22pF" maxVoltageRating={50} footprint="0402"
      manufacturerPartNumber="CL05C220JB5NNNC" supplierPartNumbers={{jlcpcb:["C70464"]}}
      pcbX={-27} pcbY={-33} pcbRotation={180} schX={-24} schY={-15} />
    <capacitor name="C_ETH_XO" capacitance="22pF" maxVoltageRating={50} footprint="0402"
      manufacturerPartNumber="CL05C220JB5NNNC" supplierPartNumbers={{jlcpcb:["C70464"]}}
      pcbX={-20} pcbY={-33} schX={-18} schY={-15} />
    <trace name="ETH_XI" from=".U_ETH > .pin30" to=".Y_ETH > .pin1"
      thickness={0.12}
      pcbPath={[".U_ETH > .pin30", {x:0.25,y:5.4}, {x:2,y:6.2}, {x:2,y:8.9}, ".Y_ETH > .pin1"]} />
    <trace name="ETH_XO" from=".U_ETH > .XO" to=".Y_ETH > .pin3"
      thickness={0.12} maxLength={10}
      pcbPath={[".U_ETH > .XO", {x:-0.25,y:5.4}, {x:-2,y:6.2}, {x:-2,y:11.1}, ".Y_ETH > .pin3"]} />
    {wire("ETH_CRYSTAL_GND2", ".Y_ETH > .pin2", "net.BOARD_GND")}
    {wire("ETH_CRYSTAL_GND4", ".Y_ETH > .pin4", "net.BOARD_GND")}
    <trace name="ETH_XI_CAP" from=".Y_ETH > .pin1" to=".C_ETH_XI > .pin1"
      thickness={0.12} maxLength={10} pcbStraightLine />
    {wire("ETH_XI_CAP_GND", ".C_ETH_XI > .pin2", "net.BOARD_GND")}
    <trace name="ETH_XO_CAP" from=".Y_ETH > .pin3" to=".C_ETH_XO > .pin1"
      thickness={0.12} maxLength={10} pcbStraightLine />
    {wire("ETH_XO_CAP_GND", ".C_ETH_XO > .pin2", "net.BOARD_GND")}

    {/* SPI1 and interrupt/reset lines are dedicated internal connections. */}
    {wire("ETH_CS", ".U_ETH > .SCSn", "net.ETH_CS")}
    {wire("ETH_MISO", ".U_ETH > .MISO", "net.ETH_MISO")}
    {wire("ETH_MOSI", ".U_ETH > .MOSI", "net.ETH_MOSI")}
    {wire("ETH_INT", ".U_ETH > .INTn", "net.ETH_INT")}
    {wire("ETH_RESET", ".U_ETH > .RSTn", "net.ETH_RST")}
    {resistor("R_ETH_RST", "10k", "C25744", -20, -14, 0, -13, -14)}
    {resistor("R_ETH_INT", "10k", "C25744", -17.5, -14, 0, -10, -14)}
    {wire("ETH_RST_PULLUP", ".R_ETH_RST > .pin1", "net.ETH_RST")}
    {wire("ETH_RST_PULLUP_VDD", ".R_ETH_RST > .pin2", "net.ETH_3V3")}
    {wire("ETH_INT_PULLUP", ".R_ETH_INT > .pin1", "net.ETH_INT")}
    {wire("ETH_INT_PULLUP_VDD", ".R_ETH_INT > .pin2", "net.ETH_3V3")}
    {[43,44,45].map(pin => wire(`ETH_PMODE_${pin}`, `.U_ETH > .pin${pin}`, "net.ETH_3V3"))}

    {/* WIZnet MDI termination. TX is direct-coupled and each transmitter pin is
        biased to the analog rail through 49.9 ohm. RX is AC-coupled and each
        receiver pin is terminated to the receive center-tap bias node. */}
    {[
      ["TXN",2,-17,-19,0,-17,-20], ["TXP",1,-17,-21,0,-17,-22], ["RXN",6,-20,-16.5,0,-17,-24], ["RXP",3,-23.5,-16.5,90,-17,-26],
    ].map(([name,pin,x,y,rotation,schX,schY]) => <group key={name as string} pcbX={0} pcbY={0} schX={0} schY={0}>
      {resistor(`R_ETH_${name}`, "49.9", "C25792", x as number, y as number, rotation as number, schX as number, schY as number)}
      {name === "TXN" || name === "TXP"
        ? wire(`ETH_${name}_CHIP`, `.U_ETH > .${name}`, `.J_ETH > .pin${pin}`, 0.2)
        : wire(`ETH_${name}_CHIP`, `.U_ETH > .${name}`, `.C_ETH_${name}_AC > .pin1`, 0.2)}
      {name === "TXN" || name === "TXP"
        ? wire(`ETH_${name}_JACK`, `.U_ETH > .${name}`, `.R_ETH_${name} > .pin1`, 0.2)
        : wire(`ETH_${name}_JACK`, `.C_ETH_${name}_AC > .pin2`, `.J_ETH > .pin${pin}`, 0.2)}
    </group>)}
    {wire("ETH_TCT", ".J_ETH > .pin4", ".R_ETH_TCT > .pin1", 0.3)}
    {wire("ETH_RCT", ".J_ETH > .pin5", "net.ETH_RX_BIAS", 0.3)}
    {wire("ETH_SHIELD1", ".J_ETH > .SH1", "net.BOARD_GND", 0.3)}
    {wire("ETH_SHIELD2", ".J_ETH > .SH2", "net.BOARD_GND", 0.3)}

    <silkscreentext text="ETHERNET 10/100" pcbX={-5.5} pcbY={-14.2} fontSize={0.75} />
  </group>
}