seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version: 0.0.9
License: unset
Stars: 0

validation/safe-candidate/status.json

{
  "status": "INCOMPLETE \u2014 NOT PUBLISHED",
  "shapeAudit": "PASS",
  "crossNetCopperAudit": "PASS",
  "nativeRoutingErrors": 4,
  "reason": "Length skew exceeds the unchanged bus/pair limits",
  "componentPlacementChanged": false,
  "signals": 47,
  "dogboneVias": 94,
  "signalRoutingVias": 0
}