seveibar/am3352-ram-dogbone-and-single-layer-route-test

AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.

Version
0.0.9
License
unset
Stars
0

validation/safe-candidate/native-errors.json

[
  {
    "type": "pcb_bus_length_skew_error",
    "pcb_bus_length_skew_error_id": "pcb_bus_length_skew_error_source_bus_0",
    "error_type": "pcb_bus_length_skew_error",
    "message": "PCB bus DDR_BYTE0 has 6.57mm length skew, exceeding the 0.635mm maximum",
    "source_bus_id": "source_bus_0",
    "source_trace_ids": [
      "source_trace_14",
      "source_trace_30",
      "source_trace_3",
      "source_trace_40",
      "source_trace_17",
      "source_trace_41",
      "source_trace_4",
      "source_trace_31",
      "source_trace_29",
      "source_trace_15",
      "source_trace_16"
    ],
    "pcb_trace_ids": [
      "signal_source_trace_14",
      "signal_source_trace_30",
      "signal_source_trace_3",
      "signal_source_trace_40",
      "signal_source_trace_17",
      "signal_source_trace_41",
      "signal_source_trace_4",
      "signal_source_trace_31",
      "signal_source_trace_29",
      "signal_source_trace_15",
      "signal_source_trace_16"
    ],
    "actual_length_skew": 6.568901740002431,
    "maximum_length_skew": 0.635,
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "pcb_bus_length_skew_error",
    "pcb_bus_length_skew_error_id": "pcb_bus_length_skew_error_source_bus_1",
    "error_type": "pcb_bus_length_skew_error",
    "message": "PCB bus DDR_BYTE1 has 4.88mm length skew, exceeding the 0.635mm maximum",
    "source_bus_id": "source_bus_1",
    "source_trace_ids": [
      "source_trace_28",
      "source_trace_12",
      "source_trace_39",
      "source_trace_2",
      "source_trace_25",
      "source_trace_1",
      "source_trace_38",
      "source_trace_11",
      "source_trace_13",
      "source_trace_27",
      "source_trace_26"
    ],
    "pcb_trace_ids": [
      "signal_source_trace_28",
      "signal_source_trace_12",
      "signal_source_trace_39",
      "signal_source_trace_2",
      "signal_source_trace_25",
      "signal_source_trace_1",
      "signal_source_trace_38",
      "signal_source_trace_11",
      "signal_source_trace_13",
      "signal_source_trace_27",
      "signal_source_trace_26"
    ],
    "actual_length_skew": 4.883310203991602,
    "maximum_length_skew": 0.635,
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "pcb_bus_length_skew_error",
    "pcb_bus_length_skew_error_id": "pcb_bus_length_skew_error_source_bus_2",
    "error_type": "pcb_bus_length_skew_error",
    "message": "PCB bus DDR_DQS_PAIR0 has 4.06mm length skew, exceeding the 0.127mm maximum",
    "source_bus_id": "source_bus_2",
    "source_trace_ids": [
      "source_trace_15",
      "source_trace_16"
    ],
    "pcb_trace_ids": [
      "signal_source_trace_15",
      "signal_source_trace_16"
    ],
    "actual_length_skew": 4.060926688733407,
    "maximum_length_skew": 0.127,
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "pcb_bus_length_skew_error",
    "pcb_bus_length_skew_error_id": "pcb_bus_length_skew_error_source_bus_3",
    "error_type": "pcb_bus_length_skew_error",
    "message": "PCB bus DDR_DQS_PAIR1 has 0.14mm length skew, exceeding the 0.127mm maximum",
    "source_bus_id": "source_bus_3",
    "source_trace_ids": [
      "source_trace_27",
      "source_trace_26"
    ],
    "pcb_trace_ids": [
      "signal_source_trace_27",
      "signal_source_trace_26"
    ],
    "actual_length_skew": 0.1429515944933577,
    "maximum_length_skew": 0.127,
    "subcircuit_id": "subcircuit_source_group_0"
  }
]