seveibar/am3352-ram-dogbone-and-single-layer-route-test
AM3352BZCZ100 processor connected to a W631GG6MB-12 DDR3 memory chip through a routed, length-matched 16-bit DDR interface with clock/data-strobe pairs and control/address signals.
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- 0.0.9
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- unset
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design/smoothing-criteria.md
# Fixed smoothing criteria
The criteria and weights are held constant for the before/after comparison. Lower penalty is better. This is a visual-routing heuristic, not an electrical-performance score.
## Hard acceptance gates
- Preserve all 47 nets, fixed endpoints, original dogbones, all 94 vias and signal layers.
- Introduce no routing vias, shorts, self-intersections or board-boundary violations.
- Retain 0.1 mm trace width and clearance.
- Change each signal's planar centerline length by at most 0.004 mm from its pre-smoothing length. Retest every byte-bus and differential-pair skew limit.
- Pass native DRC and the independent geometric connectivity/clearance audit.
No score improvement can compensate for failing a gate.
## Soft penalty
`bends + 2 × shortSegments + 20 × non45LengthMm + 2 × sharpBends + 3 × rapidReversals`
- **Bends:** heading changes greater than 5°. Fewer unnecessary corners are easier to inspect.
- **Short segments:** segments shorter than 0.3 mm (three trace widths). This discourages small notches and fragmented tuning.
- **Non-45° length:** length whose heading differs by more than 2° from a multiple of 45°. This favors conventional orthogonal/diagonal routing.
- **Sharp bends:** heading changes greater than approximately 45°. This favors chamfered turns over square or acute turns where practical.
- **Rapid reversals:** alternating turn directions separated by a segment shorter than 0.3 mm. This specifically penalizes the sawtooth pattern visible in the original routes.
Exact collinear subdivisions and duplicate vertices are removed before scoring, so merely reducing sampling density does not count as improvement. Collinear backtracking is retained and rejected as invalid geometry rather than silently removing length.
## Optimization
Consider overlapping windows of 2–128 vertices. Generate direct paths, orthogonal/45° alternatives, and equal-length tuning loops with 0–0.5 mm chamfers. Evaluate clearance against every other trace on the same layer and every through via. Check the replacement and its joins for self-intersections. Accept only strictly better scores within the original per-net length budget; make up to three passes.
A larger-chamfer refinement reduced the penalty from 6,085.63 to 6,020.63 using the same criteria: it traded 26 additional 45° bends for 40 fewer sharp turns, while maintaining the hard gates. Congested regions retain some irregularities because moving neighboring nets or changing the tuning target is outside this post-processing pass.