seveibar/am3352-ram-dogbone-and-single-layer-route-test

design/coupled-routing-criteria.md

# Compact routing acceptance criteria

Validity is a hard gate. A better visual or efficiency score cannot compensate for a failed gate.

1. Connect all 47 signals with exactly two local dogbone vias per signal. No signal-routing vias or signal-layer changes. Preserve the TSX bus/pair declarations and their skew tolerances.
2. Native DRC must report zero errors. Independently check physical pad, trace and through-via copper at 0.1 mm trace width and edge clearance, with 3 µm numerical tolerance.
3. No self contact or nonlocal centerline spacing below 0.1999 mm. Exclude only 0.3 mm of local arclength, clipping segment domains so resampling cannot hide defects.
4. Ordinary routing is horizontal, vertical or 45°. No heading jumps above 45.1°. Intentional curves have inferred radius ≥0.1195 mm. Main pair inner radii are planned at 0.13 mm. Curves are actual copper, not display effects.
5. Pair skew ≤0.127 mm and each byte's skew ≤0.635 mm, including both top stubs. Equal via counts/depths do not alter within-group skew.
6. Bidirectional pair-gap samples every ≤0.01 mm must have main-run edge gap 0.10–0.155 mm; nominal gap is 0.12 mm. Continuous copper clearance is audited independently.
7. Pin-escape exceptions are bounded to the first/last 6.2 mm. Report actual extents, full-route maximum gap and fraction inside the gap band for each member. The previous limit was 4.5 mm; the increase explicitly accommodates the new compact pin escapes and local skew corrections. It is not hidden by an average. Main paired-run gap limits remain unchanged.
8. Measure every planar trace against its straight pad-to-pad distance, including both top stubs. Worst detour ratio must be ≤3.5× and mean ratio ≤2.3×. Also report total copper length and excess millimetres so increasing chip separation cannot hide longer copper.

After all gates pass, minimize total/excess copper length, then ordinary direction changes and short jogs outside curved meanders. The turn-cleanup pass accepts only fewer-turn octilinear replacements with the same length (within 0.0000001 mm), while retaining all clearance and pair-gap gates. Count a short jog when a segment under 0.25 mm connects two ordinary turns. Arc tessellation and collinear points do not count. Preserve intentional curved meanders; do not simplify them into corners. Favor larger radii where a shape change is needed. The previous revision passed DRC but had a 15.22× worst detour and 3948.66 mm total copper. These efficiency gates reject that result.

## Geometry strategy and tradeoffs

RAM moves 8 mm farther from U1; the outline grows from 70 × 60 to 70 × 70 mm. This creates central tuning room and allows compact ordered lanes instead of the old wide external loops. Total copper is nevertheless 57% shorter. Both absolute lengths and placement changes are included in the comparison.

Each DQS pair uses a common centerline and analytic offsets. Rounded waves carry most length correction; small smooth bumps correct residual skew near the pins. Ordinary escapes are checked and repaired locally. Address/control signals are negotiated around the completed buses on any one available signal layer, with no added vias.

The active custom algorithm functions evaluate a board-specific guide/curve plan and verify timing. They do not rerun the offline routing search at build time. Placement, trace-width and outline guards reject stale plans; changed obstacles or topology require replanning and every audit.