muse/book-reading-clip-lamp

verify-rgb-status.py

"""Audit RGB electrical domains, channel polarity, current limits and shared bus."""
import json, math
from pathlib import Path
root=Path(__file__).resolve().parent
data=json.loads((root/'dist/index/circuit.json').read_text())
components={e['name']:e for e in data if e['type']=='source_component'}
ports={(e['source_component_id'],e.get('pin_number')):e for e in data if e['type']=='source_port'}
nets={e['source_net_id']:e['name'] for e in data if e['type']=='source_net'}
def pin(ref,number):return ports[(components[ref]['source_component_id'],number)]
def pin_net(ref,number):
    p=pin(ref,number)
    ns={nets[n] for e in data if e['type']=='source_trace' and p['source_port_id'] in e['connected_source_port_ids'] for n in e.get('connected_source_net_ids',[])}
    assert len(ns)==1,(ref,number,ns)
    return ns.pop()
expected={
'U19':{1:'RGB_R_SINK',2:'RGB_G_SINK',3:'RGB_B_SINK',5:'GND',6:'CAM_SCL',7:'CAM_SDA',8:'V3V3'},
'LED9':{1:'RGB_R_K',2:'V3V3',3:'RGB_G_K',4:'RGB_B_K'},
'R43':{1:'RGB_R_SINK',2:'RGB_R_K'},'R44':{1:'RGB_G_SINK',2:'RGB_G_K'},'R45':{1:'RGB_B_SINK',2:'RGB_B_K'},
'R46':{1:'CAM_SCL',2:'V3V3'},'R47':{1:'CAM_SDA',2:'V3V3'},'C45':{1:'V3V3',2:'GND'},
'U13':{1:'CAM_SCL',8:'CAM_SDA',4:'FPC_SCL',5:'FPC_SDA'},'U1':{32:'CAM_SCL',33:'CAM_SDA'},
}
for ref,mapping in expected.items():
    for n,net in mapping.items():assert pin_net(ref,n)==net,(ref,n,net)
assert components['U19']['supplier_part_numbers']['jlcpcb']==['C2802665']
assert components['LED9']['supplier_part_numbers']['jlcpcb']==['C965840']
assert not any(pin('U19',4)['source_port_id'] in e['connected_source_port_ids'] for e in data if e['type']=='source_trace'),'Unused LED3 output must remain NC'
for ref,ohms in [('R43',1000),('R44',330),('R45',330),('R46',4700),('R47',4700)]:
    assert math.isclose(components[ref]['resistance'],ohms),ref
    # Ignore forward drop for a conservative 3.3 V +5%, resistor -1% bound.
    if ref in ['R43','R44','R45']:assert 3.465/(ohms*.99)<.02,ref
assert math.isclose(components['C45']['capacitance'],1e-7)
# Verify corrected manufacturer pad numbering (catalog 3/4 were swapped).
pp={e['source_port_id']:e for e in data if e['type']=='pcb_port'}
coords={n:pp[pin('LED9',n)['source_port_id']] for n in range(1,5)}
assert coords[1]['x']>coords[3]['x'] and coords[2]['x']>coords[4]['x']
assert coords[1]['y']<coords[2]['y'] and coords[3]['y']<coords[4]['y']
# Both primary pin assignments and default power/charge lights are preserved.
assert pin_net('LED7',2)=='V3V3' and pin_net('LED7',1)=='STATUS_A'
assert pin_net('LED8',2)=='CHG_LED_A' and pin_net('LED8',1)=='CHG_N'
print('PASS: RGB pinout/current limits, decoupling, 3.3 V shared bus, pull-ups, corrected supplier pads and original power/charge indicators')
print('Hardware LED brightness, bus waveform and firmware execution remain bench tests.')