mohan-bee/four-gang-wifi-switch-layout

validation-summary.json

PCB

Schematic

{
  "engine": "@tscircuit/capacity-autorouter",
  "version": "0.0.1027",
  "solver": "AutoroutingPipelineSolver9_PreloadedTraceGraph",
  "whole_phase_routing": true,
  "relay_mains_policy": "Preserve default capacity high-density paths; skip faulty trace simplification; retain later checks.",
  "saved_copper_path_imports": 0,
  "manual_board_copper": 0,
  "all_connectors": "ordinary straight unshrouded male pin headers",
  "all_tht_factory_dnp": true,
  "prototype_electrical_rating_verified": false,
  "boards": {
    "controller": {
      "board_mm": [
        48,
        50
      ],
      "component_layers": [
        "top"
      ],
      "trace_count": 42,
      "via_count": 42,
      "actual_minimum_widths_mm": {
        "AC_N": 0.8,
        "AC_L_FUSED": 0.8,
        "AC_L": 0.8,
        "RX": 0.2,
        "TX": 0.2,
        "CH4": 0.2,
        "CH3": 0.2,
        "CH2": 0.2,
        "CH1": 0.2,
        "STRAP15": 0.2,
        "STRAP2": 0.2,
        "BOOT": 0.2,
        "RST": 0.2,
        "EN": 0.2,
        "V3V3": 0.2,
        "GND": 0.2,
        "V5": 0.25
      },
      "phase_minimum_widths_mm": {
        "AC_N": 0.8,
        "AC_L": 0.8,
        "AC_L_FUSED": 0.8,
        "V5": 0.2,
        "GND": 0.2,
        "V3V3": 0.2,
        "EN": 0.2,
        "RST": 0.2,
        "BOOT": 0.2,
        "STRAP2": 0.2,
        "STRAP15": 0.2,
        "CH1": 0.2,
        "CH2": 0.2,
        "CH3": 0.2,
        "CH4": 0.2,
        "TX": 0.2,
        "RX": 0.2
      },
      "native_routing_errors": 0,
      "native_routing_style_warnings": 1,
      "connected": true,
      "independent_copper_and_keepout_checks_passed": true,
      "via_drill_pad_overlaps": 0,
      "cli_build_geometry_matches_proof": true,
      "tht_dnp_refs": [
        "PS1",
        "J_AC",
        "F1",
        "RV1",
        "J_LINK",
        "J_PROG"
      ],
      "smt_populated_refs": [
        "U1",
        "U2",
        "C1",
        "C2",
        "C3",
        "C4",
        "C5",
        "R1",
        "R2",
        "R3",
        "R4",
        "R5"
      ],
      "eventual_hand_assembly_placement_errors": 0,
      "headers": {
        "J_AC": {
          "part": "C25170858",
          "pitch_mm": 5.08,
          "pins": 2,
          "minimum_adjacent_pad_gap_mm": 2.780004599999927,
          "factory_dnp": true
        },
        "J_LINK": {
          "part": "C6800644",
          "pitch_mm": 2.54,
          "pins": 6,
          "minimum_adjacent_pad_gap_mm": 0.8400033999999637,
          "factory_dnp": true
        },
        "J_PROG": {
          "part": "C6800644",
          "pitch_mm": 2.54,
          "pins": 6,
          "minimum_adjacent_pad_gap_mm": 0.8400033999999637,
          "factory_dnp": true
        }
      },
      "circuit_sha256": "3919ab963b7c7dd2da1ea1990fd7ff488af945680e93fa154d57a0d0cbc606a1"
    },
    "relay": {
      "board_mm": [
        48,
        50
      ],
      "component_layers": [
        "top"
      ],
      "trace_count": 31,
      "via_count": 13,
      "actual_minimum_widths_mm": {
        "AC_L": 2.1999956,
        "OUT4": 1.5,
        "OUT3": 1.5,
        "OUT2": 1.5,
        "OUT1": 1.5,
        "AC_N": 0.8,
        "GND": 0.4,
        "V5": 0.35,
        "CH4": 0.25,
        "CH3": 0.25,
        "CH2": 0.25,
        "CH1": 0.25,
        "COIL4": 0.25,
        "COIL3": 0.25,
        "COIL2": 0.25,
        "COIL1": 0.25
      },
      "phase_minimum_widths_mm": {
        "AC_L": 2.2,
        "OUT4": 1.5,
        "OUT3": 1.5,
        "OUT2": 1.5,
        "OUT1": 1.5,
        "AC_N": 0.8,
        "V5": 0.35,
        "GND": 0.35,
        "CH1": 0.25,
        "CH2": 0.25,
        "CH3": 0.25,
        "CH4": 0.25,
        "COIL1": 0.25,
        "COIL2": 0.25,
        "COIL3": 0.25,
        "COIL4": 0.25
      },
      "native_routing_errors": 0,
      "native_routing_style_warnings": 7,
      "connected": true,
      "independent_copper_and_keepout_checks_passed": true,
      "via_drill_pad_overlaps": 0,
      "cli_build_geometry_matches_proof": true,
      "tht_dnp_refs": [
        "K1",
        "K2",
        "K3",
        "K4",
        "J_LINK",
        "J_AC_IN",
        "J_AC_PWR",
        "J_OUT"
      ],
      "smt_populated_refs": [
        "U1",
        "C1",
        "C2"
      ],
      "eventual_hand_assembly_placement_errors": 0,
      "headers": {
        "J_LINK": {
          "part": "C6800644",
          "pitch_mm": 2.54,
          "pins": 6,
          "minimum_adjacent_pad_gap_mm": 0.8400033999999637,
          "factory_dnp": true
        },
        "J_AC_IN": {
          "part": "C25170858",
          "pitch_mm": 5.08,
          "pins": 2,
          "minimum_adjacent_pad_gap_mm": 2.780004599999927,
          "factory_dnp": true
        },
        "J_AC_PWR": {
          "part": "C25170858",
          "pitch_mm": 5.08,
          "pins": 2,
          "minimum_adjacent_pad_gap_mm": 2.780004599999927,
          "factory_dnp": true
        },
        "J_OUT": {
          "part": "C41355716",
          "pitch_mm": 5.08,
          "pins": 4,
          "minimum_adjacent_pad_gap_mm": 2.880004399999928,
          "factory_dnp": true
        }
      },
      "circuit_sha256": "b119973347232ad2b47d9bd9d843ec54a8892324bc4ec1ab5eb20b4c1510dcc6"
    }
  }
}