mohan-bee/fitness-band

validation/publish-main-routing-0p1.log

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
trace: `key` is not a prop. Trying to access it will result in `undefined` being returned. If you need to access the same value within the child component, you should pass it as a different prop. (https://react.dev/link/special-props)
Autorouting phase 1/1 has been running for 10.1s; enabling phase diagnostics. Re-run with --autorouter-debug for full autorouter logs from the start.
Autorouting <board#506 /> phase 1/1 long-running start: connections=22, obstacles=369, previous_traces=0, router=tscircuit, solver=AutoroutingPipelineSolver9_PreloadedTraceGraph, cache=miss, cache_id=12cad7cd/e44fa445
  connections: R7.pin1 to U2.PROG1, R8.pin1 to U2.PROG3, net.GND, net.V3V3, net.V1V8, net.VBAT, net.VSYS, net.CHG_5V, net.DOCK_5V, net.FUSED_5V, net.SDA, net.SCL, net.PPG_INT, net.MOTION_INT, net.CHG_INT, net.FG_INT, net.SWDIO, net.SWDCLK, net.RESET, net.BAT_NTC, net.SW1, net.SW2
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=pipeline9JointDrcRepairSolver steps=33 progress=85% iterations_per_second=4912 elapsed=10.1s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=pipeline9JointDrcRepairSolver steps=34 progress=85% iterations_per_second=5536 elapsed=10.4s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=pipeline9JointDrcRepairSolver steps=72 progress=87% iterations_per_second=4624 elapsed=20.6s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=powerTraceExpansionSolver steps=110 progress=97% iterations_per_second=350648 elapsed=30.7s
  phase 1/1 done: routed_traces=131, jumpers=0, errors=0, elapsed=37.4s
Could not save autorouting paths for subcircuit_source_group_0: Only port-anchored wire/via routes can be saved
Circuit JSON written to dist/index/circuit.json
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
<trace#1339(from:.R7 > .pin1 to:.U2 > .PROG1) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#1341(from:.R8 > .pin1 to:.U2 > .PROG3) /> is missing a name. Add a name prop to make the trace easier to identify.
Port VBUS on U1 is missing a trace
J_SWD has no pin with requires_power=true
J_SWD has no pin with requires_ground=true
All pins on J_SWD are underspecified (no pinAttributes set)
U2 has no pin with requires_power=true
U2 has no pin with requires_ground=true
All pins on U2 are underspecified (no pinAttributes set)
J_BAT has no pin with requires_power=true
J_BAT has no pin with requires_ground=true
All pins on J_BAT are underspecified (no pinAttributes set)
J_CHG has no pin with requires_power=true
J_CHG has no pin with requires_ground=true
All pins on J_CHG are underspecified (no pinAttributes set)
D1 has no pin with requires_power=true
D1 has no pin with requires_ground=true
All pins on D1 are underspecified (no pinAttributes set)
D2 has no pin with requires_power=true
D2 has no pin with requires_ground=true
All pins on D2 are underspecified (no pinAttributes set)
U6 has no pin with requires_power=true
J_FLEX has no pin with requires_power=true
J_FLEX has no pin with requires_ground=true
All pins on J_FLEX are underspecified (no pinAttributes set)
No <schematicsheet> was found. Add a <schematicsheet> to define the schematic drawing area.
J_FLEX has no courtyard
Trace [.U3 > .PGND to .U3 > .EP] is routed thinner than requested (requested: 0.35mm, actual: 0.10000000000000142mm).
Trace [.U3 > .GND to .U3 > .EP] is routed thinner than requested (requested: 0.2mm, actual: 0.10000000000000142mm).
Trace [.U3 > .FB to .C7 > .pin1] is routed thinner than requested (requested: 0.15mm, actual: 0.1mm).
Trace [.U3 > .VOUT to .C7 > .pin1] is routed thinner than requested (requested: 0.3mm, actual: 0.1mm).
Trace [.C7 > .pin1 to .C8 > .pin1] is routed thinner than requested (requested: 0.3mm, actual: 0.1mm).
PCB trace is 8.32mm long, exceeding the 5mm maximum
PCB trace .U1 > .P0_27 to net.SCL overlaps with pcb_via "unnamed via" (accidental contact)
PCB trace .U1 > .P0_27 to net.SCL overlaps with pcb_smtpad "U4.NC1" (accidental contact)
PCB trace .U4 > .SCX to net.SCL overlaps with pcb_smtpad "U4.NC1" (accidental contact)
PCB trace .U4 > .SCX to net.SCL is too close to .U1 > .P0_26 to net.SDA (gap: 0.091mm)
PCB trace .U4 > .SCX to net.SCL is too close to .U4 > .SDX to net.SDA (gap: 0.091mm)
PCB trace .U1 > .P0_26 to net.SDA overlaps with pcb_smtpad "U4.CSB" (accidental contact)
PCB trace .U1 > .P0_26 to net.SDA is too close to .U4 > .VDD to net.V3V3 (gap: 0.061mm)
PCB trace .U4 > .SDX to net.SDA is too close to .U4 > .VDD to net.V3V3 (gap: 0.067mm)
PCB trace .U4 > .SDX to net.SDA overlaps with pcb_smtpad "U4.CSB" (accidental contact)
PCB trace .U4 > .SDX to net.SDA is too close to .U4 > .CSB to net.V3V3 (gap: 0.047mm)
PCB trace .U2 > .BAT1 to net.VBAT overlaps with pcb_via "unnamed via" (accidental contact)
PCB trace .C7 > .pin1 to .C8 > .pin1 is too close to .U3 > .VINA to net.VSYS (gap: 0.071mm)
Pad U4.NC1 and trace .U1 > .P0_26 to net.SDA are too close (clearance: 0.046mm, minimum: 0.1mm)
Pad U4.GND and trace .U4 > .SDX to net.SDA are too close (clearance: 0.063mm, minimum: 0.1mm)
Pad U4.NC1 and trace .U4 > .SDX to net.SDA are too close (clearance: 0.064mm, minimum: 0.1mm)
Via unnamed via and trace .U1 > .P0_13 to net.CHG_INT are too close (clearance: 0.033mm, minimum: 0.1mm)
Via unnamed via and trace .U2 > .BAT1 to net.VBAT are too close (clearance: 0.01mm, minimum: 0.1mm)
Vias unnamed via and unnamed via are too close together (gap: -0.095mm)

Build complete
  Circuits  0 passed 1 failed
  Options   autorouter-timeout
  Output    dist

⚠ Build completed with errors
Build exiting with code 1: circuit build errors occurred