mohan-bee/compact-pir

validation/build-status.json

{
  "revision": "1.0.2",
  "status": "development_only_not_for_fabrication",
  "strict_build_exit_code": 1,
  "preview_build_exit_code": 0,
  "preview_uses_ignore_errors": true,
  "native_autorouter_enabled": true,
  "autorouter_preset": "auto-local",
  "autorouter_version": "beta_pipeline9",
  "solver": "AutoroutingPipelineSolver9_PreloadedTraceGraph",
  "capacity_autorouter_version": "0.0.999",
  "tscircuit": "0.0.3016",
  "core": "0.0.2203",
  "cli": "0.1.2408",
  "freerouting_used": false,
  "entrypoint": "index.circuit.tsx",
  "routing_snapshot_is_entrypoint": false,
  "board": {
    "type": "pcb_board",
    "pcb_board_id": "pcb_board_0",
    "source_board_id": "source_board_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "center": {
      "x": 0,
      "y": 0
    },
    "thickness": 1,
    "num_layers": 2,
    "width": 29,
    "height": 25,
    "material": "fr4",
    "is_via_in_pad_allowed": true,
    "solder_mask_color": "green",
    "min_trace_width": 0.15,
    "min_via_hole_diameter": 0.2,
    "min_via_pad_diameter": 0.4,
    "min_via_hole_edge_to_via_hole_edge_clearance": 0.1,
    "min_via_edge_to_pad_edge_clearance": 0.1,
    "min_trace_to_hole_edge_clearance": 0.2,
    "min_trace_to_pad_edge_clearance": 0.1,
    "min_pad_edge_to_pad_edge_clearance": 0.1,
    "min_plated_hole_drill_edge_to_drill_edge_clearance": 0.1,
    "min_board_edge_clearance": 0.3
  },
  "pcb_trace_count": 96,
  "pcb_via_count": 95,
  "manual_rf_clock_trace_count": 9,
  "build_errors": [
    {
      "type": "pcb_trace_error",
      "pcb_trace_error_id": "pcb_trace_error_0",
      "error_type": "pcb_trace_error",
      "message": "PCB trace .J2 > .pin4 to net.GPIO1 is too close to .J2 > .pin3 to net.GPIO0 (gap: 0.072mm)",
      "pcb_trace_id": "source_net_3_0",
      "source_trace_id": "",
      "pcb_component_ids": [],
      "center": {
        "x": -7.324467335248016,
        "y": -0.4615347779127832
      },
      "pcb_port_ids": [
        "pcb_port_13",
        "pcb_port_33",
        "pcb_port_12",
        "pcb_port_32"
      ]
    }
  ],
  "independent_native_drc": {
    "violations": {
      "shorting_items": 12,
      "clearance": 4,
      "silk_edge_clearance": 2,
      "hole_to_hole": 1,
      "text_height": 28,
      "silk_overlap": 13,
      "silk_over_copper": 7
    },
    "unconnected_items": 0
  },
  "blocker": "GPIO0 and GPIO1 overlap and violate copper clearance. Native KiCad confirms shorts on this pair. Additional native fabrication/silkscreen checks also fail.",
  "factory_exports_for_this_revision_included": false,
  "circuit_json_sha256": "1ded432df29e857f6469435fc41521319b4ae002b94b0f5bb7e04441018b1ff4",
  "pcb_placement_errors": 0,
  "pcb_placement_warnings": 0,
  "schematic_layout_advisory": "Decoupling capacitor bank max body gap3.601mm exceeds schematic readability recommendation1mm"
}