mohan-bee/RV1106G2
This code defines a detailed hardware schematic with schematic symbols, footprints, and 3D models for various electronic components including microcontrollers, voltage regulators, connectors, and passive parts, designed for PCB layout and routing.
- Version
- 1.0.23
- License
- unset
- Stars
- 0
index.circuit.tsx
PCB
Schematic
import { RV1106G2 } from "./imports/RV1106G2";
import { TYPE_C_31_M_12 } from "./imports/TYPE_C_31_M_12";
import { AP2112K_3_3TRG1 } from "./imports/AP2112K_3_3TRG1";
import { USBLC6_2SC6 } from "./imports/USBLC6_2SC6";
import { W25Q128JVSIQ } from "./imports/W25Q128JVSIQ";
import { HX_3x4x2_5_PA_4N_push_button_switch } from "./imports/HX_3x4x2_5_PA_4N_push_button_switch";
import { FH12_20S_0_5SH_55_ } from "./imports/FH12_20S_0_5SH_55_";
import { BLM18AG121SN1D } from "./imports/BLM18AG121SN1D";
import { HR911105A } from "./imports/HR911105A";
import { Fragment } from "react";
import {
AutoroutingPipelineSolver9_PreloadedTraceGraph,
AutoroutingPipelineSolver7_MultiGraph,
type SimpleRouteJson,
type SimplifiedPcbTrace,
type SimplifiedPcbTraces,
} from "@tscircuit/capacity-autorouter";
import { planeFanoutTraces } from "./plane-fanout-traces";
type Pipeline7AutorouterEvents = {
complete: { traces: SimplifiedPcbTraces };
error: { error: Error };
progress: { progress: number };
};
class Pipeline7PhaseAutorouter {
private readonly solver: AutoroutingPipelineSolver7_MultiGraph;
private readonly handlers: {
[EventName in keyof Pipeline7AutorouterEvents]: Array<
(event: Pipeline7AutorouterEvents[EventName]) => void
>;
} = { complete: [], error: [], progress: [] };
constructor(simpleRouteJson: SimpleRouteJson, effort: number) {
this.solver = new AutoroutingPipelineSolver7_MultiGraph(simpleRouteJson, {
effort,
});
}
on<EventName extends keyof Pipeline7AutorouterEvents>(
eventName: EventName,
handler: (event: Pipeline7AutorouterEvents[EventName]) => void,
) {
this.handlers[eventName].push(handler);
}
start() {
try {
this.solver.solve();
if (this.solver.failed || !this.solver.solved) {
throw new Error(
this.solver.error ?? "Pipeline7 did not complete the routing phase",
);
}
for (const handler of this.handlers.complete) {
handler({ traces: this.solver.getOutputSimplifiedPcbTraces() });
}
} catch (caughtError) {
const error =
caughtError instanceof Error
? caughtError
: new Error(String(caughtError));
for (const handler of this.handlers.error) handler({ error });
}
}
stop() {}
getOutputSimpleRouteJson() {
return this.solver.getOutputSimpleRouteJson();
}
}
const lowSpeedAutorouter = {
local: true,
groupMode: "subcircuit",
algorithmFn: async (simpleRouteJson: SimpleRouteJson) =>
new Pipeline7PhaseAutorouter(simpleRouteJson, 2),
} as const;
const materializeMissingTraceVias = (
traces: SimplifiedPcbTraces,
): SimplifiedPcbTraces =>
traces.map((trace) => {
const route: SimplifiedPcbTrace["route"] = [];
let activeLayer: string | undefined;
for (const routePoint of trace.route) {
if (routePoint.route_type === "wire") {
if (activeLayer && activeLayer !== routePoint.layer) {
route.push({
...routePoint,
layer: activeLayer,
});
route.push({
route_type: "via",
x: routePoint.x,
y: routePoint.y,
from_layer: activeLayer,
to_layer: routePoint.layer,
via_diameter: 0.45,
via_hole_diameter: 0.2,
});
}
route.push(routePoint);
activeLayer = routePoint.layer;
} else if (routePoint.route_type === "via") {
route.push(routePoint);
activeLayer = routePoint.to_layer;
} else if (routePoint.route_type === "through_obstacle") {
route.push(routePoint);
activeLayer = routePoint.to_layer;
} else {
route.push(routePoint);
}
}
return { ...trace, route };
});
class Pipeline9PhaseAutorouter {
private readonly solver: AutoroutingPipelineSolver9_PreloadedTraceGraph;
private readonly handlers: {
[EventName in keyof Pipeline7AutorouterEvents]: Array<
(event: Pipeline7AutorouterEvents[EventName]) => void
>;
} = { complete: [], error: [], progress: [] };
private outputTraces: SimplifiedPcbTraces = [];
constructor(private readonly input: SimpleRouteJson) {
this.solver = new AutoroutingPipelineSolver9_PreloadedTraceGraph(input, {
effort: 5,
});
}
on<EventName extends keyof Pipeline7AutorouterEvents>(
eventName: EventName,
handler: (event: Pipeline7AutorouterEvents[EventName]) => void,
) {
this.handlers[eventName].push(handler);
}
start() {
try {
this.solver.solve();
if (this.solver.failed || !this.solver.solved) {
throw new Error(
this.solver.error ?? "Pipeline9 did not complete the routing phase",
);
}
const preloadedTraceIds = new Set(
[
...this.solver.getUpdatedPreloadedTraces(),
...this.solver.getMutatedPreloadedTraces(),
].map((trace) => trace.pcb_trace_id),
);
this.outputTraces = materializeMissingTraceVias(
this.solver
.getNewTracesBeforePowerExpansion()
.filter((trace) => !preloadedTraceIds.has(trace.pcb_trace_id)),
);
for (const handler of this.handlers.complete) {
handler({ traces: this.outputTraces });
}
} catch (caughtError) {
const error =
caughtError instanceof Error
? caughtError
: new Error(String(caughtError));
for (const handler of this.handlers.error) handler({ error });
}
}
stop() {}
getOutputSimpleRouteJson() {
return { ...this.input, traces: this.outputTraces };
}
}
const pipeline9Autorouter = {
local: true,
groupMode: "subcircuit",
algorithmFn: async (simpleRouteJson: SimpleRouteJson) =>
new Pipeline9PhaseAutorouter(simpleRouteJson),
} as const;
class PlaneFanoutAutorouter {
private readonly handlers: {
[EventName in keyof Pipeline7AutorouterEvents]: Array<
(event: Pipeline7AutorouterEvents[EventName]) => void
>;
} = {
complete: [],
error: [],
progress: [],
};
private outputTraces: SimplifiedPcbTraces = [];
constructor(
private readonly input: SimpleRouteJson,
private readonly planeLayer: "inner1" | "inner2",
) {}
on<EventName extends keyof Pipeline7AutorouterEvents>(
eventName: EventName,
handler: (event: Pipeline7AutorouterEvents[EventName]) => void,
) {
this.handlers[eventName].push(handler);
}
start() {
try {
const connection = this.input.connections[0];
if (!connection)
throw new Error(`No connection found for ${this.planeLayer}`);
this.outputTraces = planeFanoutTraces
.filter((trace) => {
const endpoint = trace.route.at(-1);
return (
endpoint?.route_type === "wire" &&
endpoint.layer === this.planeLayer
);
})
.map((trace) => ({ ...trace, connection_name: connection.name }));
if (this.outputTraces.length !== connection.pointsToConnect.length) {
throw new Error(
`Stored ${this.planeLayer} fanout has ${this.outputTraces.length} traces for ${connection.pointsToConnect.length} points`,
);
}
for (const handler of this.handlers.complete) {
handler({ traces: this.outputTraces });
}
} catch (caughtError) {
const error =
caughtError instanceof Error
? caughtError
: new Error(String(caughtError));
for (const handler of this.handlers.error) handler({ error });
}
}
stop() {}
getOutputSimpleRouteJson() {
return { ...this.input, traces: this.outputTraces };
}
}
const createPlaneFanoutAutorouter = (planeLayer: "inner1" | "inner2") => ({
local: true,
groupMode: "subcircuit" as const,
algorithmFn: async (simpleRouteJson: SimpleRouteJson) =>
new PlaneFanoutAutorouter(simpleRouteJson, planeLayer),
});
const threeVoltThreePlaneAutorouter = createPlaneFanoutAutorouter("inner2");
const groundPlaneAutorouter = createPlaneFanoutAutorouter("inner1");
const routedNetGroups = [
{
phaseIndex: 7,
nets: [
"GPIO3_B0",
"GPIO3_B1",
"GPIO3_B2",
"GPIO3_B3",
"GPIO3_B4",
"GPIO3_B5",
"CAM_RESET_N",
"CAM_I2C_SCL",
"CAM_I2C_SDA",
],
},
{ phaseIndex: 4, nets: ["ETH_AVDD1V8"] },
{
phaseIndex: 3,
nets: ["VCC_1V8", "MIPI_AVDD_1V8", "OSC_AVDD1V8"],
},
{ phaseIndex: 7, nets: ["VBUS_5V", "VDD_0V9", "VDD_ARM", "VCC_DDR"] },
{ phaseIndex: 9, nets: ["PMIC_PGOOD", "RTC_AVDD3V3"] },
{
phaseIndex: 8,
nets: [
"USB_CC1",
"USB_CC2",
"USB_DM",
"USB_DP",
"USB_DM_SOC",
"USB_DP_SOC",
],
},
{ phaseIndex: 10, nets: ["XIN", "XOUT"] },
{
phaseIndex: 5,
nets: [
"FSPI_IO3",
"FSPI_IO0",
"FSPI_IO1",
"FSPI_IO2",
"FSPI_CS",
"FSPI_CLK_SOC",
"FSPI_CLK",
],
},
{ phaseIndex: 6, nets: ["GPIO0_A0", "ADC_IN0"] },
{
phaseIndex: 11,
nets: [
"GPIO4_C1",
"GPIO0_A1",
"GPIO0",
"GPIO1",
"I2C1_SCL",
"I2C1_SDA",
"UART2_TX",
"UART2_RX",
],
},
{ phaseIndex: 12, nets: ["RESET_N"] },
{ phaseIndex: 13, nets: ["POWER_LED"] },
{
phaseIndex: 2,
nets: [
"ETH_EXTR",
"ETH_TXP",
"ETH_TXN",
"ETH_RXP",
"ETH_RXN",
"ETH_TX_CT",
"ETH_RX_CT",
"ETH_SHIELD",
],
},
] as const;
const EDGE_PIN_PITCH_MM = 2.54;
const EDGE_HOLE_X_MM = 12.5;
const BOARD_WIDTH_MM = 32;
const EDGE_PIN_YS_MM = Array.from(
{ length: 14 },
(_, index) => (index - 6.5) * EDGE_PIN_PITCH_MM,
);
const leftEdgeConnections = [
"net.GND",
"net.VBUS_5V",
"net.UART2_RX",
"net.UART2_TX",
"net.I2C1_SDA",
"net.I2C1_SCL",
"net.GPIO1",
"net.GPIO0",
"net.GPIO0_A1",
"net.GPIO0_A0",
"net.GPIO4_C1",
"net.ADC_IN0",
"net.VCC_3V3",
"net.GND",
];
const rightEdgeConnections = [
"net.GND",
"net.VCC_1V8",
"net.GPIO3_B0",
"net.GPIO3_B1",
"net.GPIO3_B2",
"net.GPIO3_B3",
"net.GPIO3_B4",
"net.GPIO3_B5",
"net.CAM_RESET_N",
"net.CAM_I2C_SCL",
"net.CAM_I2C_SDA",
"net.RESET_N",
"net.VCC_3V3",
"net.GND",
];
const createBoardOutline = () => {
const halfWidth = BOARD_WIDTH_MM / 2;
const halfHeight = 40;
const cornerRadius = 1.25;
const cornerSegments = 8;
const outline: Array<{
x: number;
y: number;
}> = [];
const addCorner = (centerX: number, centerY: number, startAngle: number) => {
for (let index = 0; index <= cornerSegments; index++) {
const angle = startAngle + (Math.PI / 2) * (index / cornerSegments);
outline.push({
x: centerX + cornerRadius * Math.cos(angle),
y: centerY + cornerRadius * Math.sin(angle),
});
}
};
addCorner(halfWidth - cornerRadius, -halfHeight + cornerRadius, -Math.PI / 2);
addCorner(halfWidth - cornerRadius, halfHeight - cornerRadius, 0);
addCorner(-halfWidth + cornerRadius, halfHeight - cornerRadius, Math.PI / 2);
addCorner(-halfWidth + cornerRadius, -halfHeight + cornerRadius, Math.PI);
return outline;
};
const leftEdgePcbLabels = [
"G",
"5V",
"RX",
"TX",
"SDA",
"SCL",
"A3",
"A2",
"A1",
"A0",
"ADC1",
"ADC0",
"3V3",
"G",
];
const rightEdgePcbLabels = [
"G",
"1V8",
"B0",
"B1",
"B2",
"B3",
"B4",
"B5",
"CRST",
"CSCL",
"CSDA",
"RST",
"3V3",
"G",
];
/** RV1106G2 engineering review template. Rockchip guide pin assignments:
* UART2_M1 TX/RX = 79/80; USB2 DM/DP/VBUSDET = 26/27/25; SDMMC0 = 11–18;
* MIPI CSI0 D0/CLK/D1 = 127–128/125–126/123–124; FSPI = 39/41/42/44/47/48.
* Regulator/PMIC selection and its power-sequencing implementation still require
* validation against the selected production power IC before fabrication. */
export default () => (
<board
width={`${BOARD_WIDTH_MM}mm`}
height="80mm"
outline={createBoardOutline()}
layers={4}
material="fr4"
thickness="1.6mm"
autorouter={{
preset: "auto-local",
traceClearance: "0.18mm",
allowViaInPad: false,
}}
autorouterVersion="beta_pipeline9"
autorouterEffortLevel="5x"
schAutoLayoutEnabled
title="RV1106G2 Linux development board — review required"
>
<copperpour
name="GND_PLANE"
layer="inner1"
connectsTo="net.GND"
clearance="0.15mm"
boardEdgeMargin="0.3mm"
/>
<copperpour
name="VCC_3V3_PLANE"
layer="inner2"
connectsTo="net.VCC_3V3"
clearance="0.15mm"
boardEdgeMargin="0.3mm"
/>
<autoroutingphase
name="camera-high-speed"
phaseIndex={0}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="ethernet-high-speed"
phaseIndex={1}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="ground-plane"
phaseIndex={-2}
autorouter={groundPlaneAutorouter}
/>
<autoroutingphase
name="three-volt-three-plane"
phaseIndex={-1}
autorouter={threeVoltThreePlaneAutorouter}
/>
<autoroutingphase
name="ethernet-support"
phaseIndex={2}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="one-volt-eight"
phaseIndex={3}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="ethernet-analog-power"
phaseIndex={4}
autorouter={lowSpeedAutorouter}
/>
<autoroutingphase
name="flash"
phaseIndex={5}
autorouter={lowSpeedAutorouter}
/>
<autoroutingphase
name="left-gpio-critical-adc"
phaseIndex={6}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="processor-escape"
phaseIndex={7}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="usb"
phaseIndex={8}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="input-power"
phaseIndex={9}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="oscillator"
phaseIndex={10}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="left-gpio"
phaseIndex={11}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="reset-control"
phaseIndex={12}
autorouter={pipeline9Autorouter}
/>
<autoroutingphase
name="power-led"
phaseIndex={13}
autorouter={pipeline9Autorouter}
/>
{routedNetGroups.flatMap(({ phaseIndex, nets }) =>
nets.map((name) => (
<Fragment key={name}>
<net name={name} routingPhaseIndex={phaseIndex} />
</Fragment>
)),
)}
<net
name="VCC_3V3"
routingPhaseIndex={-1}
isPowerNet
nominalTraceWidth="0.16mm"
/>
<net
name="GND"
routingPhaseIndex={-2}
isGroundNet
nominalTraceWidth="0.16mm"
/>
{EDGE_PIN_YS_MM.map((y, index) => (
<Fragment key={`left-edge-hole-${index}`}>
<platedhole
name={`PH_LEFT_${index + 1}`}
shape="circle"
holeDiameter="1mm"
outerDiameter="1.8mm"
pcbX={-EDGE_HOLE_X_MM}
pcbY={y}
connectsTo={leftEdgeConnections[index]}
/>
</Fragment>
))}
{EDGE_PIN_YS_MM.map((y, index) => (
<Fragment key={`right-edge-hole-${index}`}>
<platedhole
name={`PH_RIGHT_${index + 1}`}
shape="circle"
holeDiameter="1mm"
outerDiameter="1.8mm"
pcbX={EDGE_HOLE_X_MM}
pcbY={y}
connectsTo={rightEdgeConnections[index]}
/>
</Fragment>
))}
<schematicsheet
name="power-usb"
displayName="Power Input & Regulation"
sheetIndex={0}
></schematicsheet>
<TYPE_C_31_M_12
name="J1"
pcbX={0}
pcbY={-36}
schSheetName="power-usb"
connections={{
A5: "net.USB_CC1",
B5: "net.USB_CC2",
B7: "net.USB_DM",
A7: "net.USB_DM",
A6: "net.USB_DP",
B6: "net.USB_DP",
A1B12: "net.GND",
B1A12: "net.GND",
B4A9: "net.VBUS_5V",
A4B9: "net.VBUS_5V",
EH1: "net.GND",
EH2: "net.GND",
EH3: "net.GND",
EH4: "net.GND",
}}
/>
<resistor
name="R1"
resistance="5.1k"
footprint="0603"
pcbX={-7}
pcbY={-32.5}
schSheetName="power-usb"
connections={{ pin1: "net.USB_CC1", pin2: "net.GND" }}
/>
<resistor
name="R2"
resistance="5.1k"
footprint="0603"
pcbX={-4}
pcbY={-31.5}
schSheetName="power-usb"
connections={{ pin1: "net.USB_CC2", pin2: "net.GND" }}
/>
<USBLC6_2SC6
name="D1"
pcbX={9.3}
pcbY={-30.5}
schSheetName="power-usb"
connections={{
pin1: "net.USB_DM",
pin6: "net.USB_DM_SOC",
pin3: "net.USB_DP",
pin4: "net.USB_DP_SOC",
pin2: "net.GND",
pin5: "net.VBUS_5V",
}}
/>
<AP2112K_3_3TRG1
name="U2"
pcbX={8.5}
pcbY={-23}
schHeight="0.6mm"
schSheetName="power-usb"
connections={{
VIN: "net.VBUS_5V",
EN: "net.PMIC_PGOOD",
GND: "net.GND",
VOUT: "net.VCC_3V3",
}}
/>
<capacitor
name="C1"
capacitance="10uF"
footprint="0603"
pcbX={7.5}
pcbY={-26}
schOrientation="vertical"
schSheetName="power-usb"
connections={{ pin1: "net.VBUS_5V", pin2: "net.GND" }}
/>
<capacitor
name="C2"
capacitance="10uF"
footprint="0603"
pcbX={9.5}
pcbY={-20}
schOrientation="vertical"
schSheetName="power-usb"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
{/* Logical multi-rail PMIC placeholder. The production part must guarantee
0V9/ARM -> 1V8/DDR -> 3V3 with >1 ms gaps and >100 us soft start. */}
<chip
name="U3"
footprint="soic8"
pcbX={8.3}
pcbY={15}
pinLabels={{
pin1: "VIN",
pin2: "GND",
pin3: "EN",
pin4: "VOUT_1V8",
pin5: "VOUT_0V9",
pin6: "VOUT_ARM",
pin7: "VOUT_DDR",
pin8: "PG",
}}
schSheetName="power-usb"
connections={{
VIN: "net.VBUS_5V",
GND: "net.GND",
EN: "net.VBUS_5V",
VOUT_1V8: "net.VCC_1V8",
VOUT_0V9: "net.VDD_0V9",
VOUT_ARM: "net.VDD_ARM",
VOUT_DDR: "net.VCC_DDR",
PG: "net.PMIC_PGOOD",
}}
/>
<schematicsheet
name="processor-core"
displayName="RV1106G2 Processor & Decoupling"
sheetIndex={1}
></schematicsheet>
<RV1106G2
name="U1"
pcbX={0}
pcbY={1}
schHeight="13mm"
schSheetName="processor-core"
connections={{
pin1: "net.MIPI_AVDD_1V8",
pin3: "net.CAM_RESET_N",
pin5: "net.CAM_I2C_SCL",
pin7: "net.CAM_I2C_SDA",
pin10: "net.VDD_0V9",
pin13: "net.VCC_3V3",
pin19: "net.RTC_AVDD3V3",
pin23: "net.ADC_IN0",
pin24: "net.VCC_1V8",
pin25: "net.VBUS_5V",
pin26: "net.USB_DM_SOC",
pin27: "net.USB_DP_SOC",
pin28: "net.VCC_3V3",
pin43: "net.VCC_3V3",
pin49: "net.VCC_DDR",
pin50: "net.VCC_DDR",
pin51: "net.VDD_0V9",
pin53: "net.VCC_1V8",
pin54: "net.VDD_0V9",
pin55: "net.VDD_0V9",
pin56: "net.VCC_DDR",
pin61: "net.VCC_3V3",
pin66: "net.RESET_N",
pin67: "net.VDD_0V9",
pin68: "net.XIN",
pin69: "net.XOUT",
pin70: "net.OSC_AVDD1V8",
pin71: "net.VDD_0V9",
pin81: "net.VCC_3V3",
pin82: "net.VDD_0V9",
pin88: "net.VCC_3V3",
pin96: "net.ETH_AVDD1V8",
pin101: "net.VCC_3V3",
pin102: "net.ETH_EXTR",
pin103: "net.VDD_0V9",
pin108: "net.VCC_3V3",
pin115: "net.VDD_ARM",
pin116: "net.VDD_0V9",
pin129: "net.GND",
pin22: "net.GPIO4_C1",
pin39: "net.FSPI_IO3",
pin41: "net.FSPI_IO0",
pin42: "net.FSPI_IO1",
pin44: "net.FSPI_IO2",
pin47: "net.FSPI_CS",
pin48: "net.FSPI_CLK_SOC",
pin58: "net.GPIO0_A0",
pin59: "net.GPIO0_A1",
pin60: "net.GPIO0",
pin62: "net.GPIO1",
pin64: "net.I2C1_SCL",
pin65: "net.I2C1_SDA",
pin79: "net.UART2_TX",
pin80: "net.UART2_RX",
pin117: "net.GPIO3_B0",
pin118: "net.GPIO3_B1",
pin119: "net.GPIO3_B2",
pin120: "net.GPIO3_B3",
pin121: "net.GPIO3_B4",
pin122: "net.GPIO3_B5",
}}
/>
{/* Rockchip-recommended processor power decoupling. These parts are kept
close to the processor while using top-side-only component placement. */}
<capacitor
name="C8"
capacitance="10uF"
footprint="0603"
pcbX={-5.5}
pcbY={9.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_ARM", pin2: "net.GND" }}
/>
<capacitor
name="C9"
capacitance="1uF"
footprint="0402"
pcbX={-2.9}
pcbY={8.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_ARM", pin2: "net.GND" }}
/>
<capacitor
name="C10"
capacitance="100nF"
footprint="0402"
pcbX={-1.5}
pcbY={10.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_ARM", pin2: "net.GND" }}
/>
<capacitor
name="C11"
capacitance="10uF"
footprint="0603"
pcbX={0.5}
pcbY={8.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C12"
capacitance="10uF"
footprint="0603"
pcbX={3.8}
pcbY={9.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C13"
capacitance="1uF"
footprint="0402"
pcbX={9.7}
pcbY={2.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C14"
capacitance="1uF"
footprint="0402"
pcbX={7.7}
pcbY={3.4}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C15"
capacitance="100nF"
footprint="0402"
pcbX={7.7}
pcbY={2.0}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C16"
capacitance="100nF"
footprint="0402"
pcbX={6.5}
pcbY={8.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C17"
capacitance="100nF"
footprint="0402"
pcbX={7.7}
pcbY={-0.8}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C18"
capacitance="100nF"
footprint="0402"
pcbX={7.7}
pcbY={0.2}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C19"
capacitance="100nF"
footprint="0402"
pcbX={8.2}
pcbY={-6.8}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C20"
capacitance="100nF"
footprint="0402"
pcbX={6.3}
pcbY={-6.8}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C21"
capacitance="100nF"
footprint="0402"
pcbX={3.8}
pcbY={-7.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C22"
capacitance="100nF"
footprint="0402"
pcbX={4}
pcbY={-11}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VDD_0V9", pin2: "net.GND" }}
/>
<capacitor
name="C23"
capacitance="10uF"
footprint="0603"
pcbX={1.2}
pcbY={-6.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_DDR", pin2: "net.GND" }}
/>
<capacitor
name="C24"
capacitance="1uF"
footprint="0603"
pcbX={-2}
pcbY={-7.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_DDR", pin2: "net.GND" }}
/>
<capacitor
name="C25"
capacitance="1uF"
footprint="0402"
pcbX={-4.5}
pcbY={-6.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_DDR", pin2: "net.GND" }}
/>
<capacitor
name="C26"
capacitance="100nF"
footprint="0402"
pcbX={-6.5}
pcbY={-7.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_DDR", pin2: "net.GND" }}
/>
<capacitor
name="C27"
capacitance="1uF"
footprint="0402"
pcbX={-8.5}
pcbY={-4.7}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_1V8", pin2: "net.GND" }}
/>
<capacitor
name="C28"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={-3.3}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_1V8", pin2: "net.GND" }}
/>
{/* One local 100 nF capacitor for every GPIO/analog power pin. */}
<capacitor
name="C29"
capacitance="100nF"
footprint="0402"
pcbX={-10.5}
pcbY={-1.9}
pcbRotation={90}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C30"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={-0.5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C31"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={0.9}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C32"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={2.3}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C33"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={3.7}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C34"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={5.1}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C35"
capacitance="100nF"
footprint="0402"
pcbX={-8.5}
pcbY={6.6}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C36"
capacitance="100nF"
footprint="0402"
pcbX={-5}
pcbY={12}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C37"
capacitance="100nF"
footprint="0402"
pcbX={-5}
pcbY={14}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<capacitor
name="C38"
capacitance="100nF"
footprint="0402"
pcbX={-1}
pcbY={-9.2}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.VCC_1V8", pin2: "net.GND" }}
/>
<schematicsheet
name="camera"
displayName="MIPI CSI Camera Interface"
sheetIndex={2}
></schematicsheet>
<FH12_20S_0_5SH_55_
name="J_CAM"
pcbX={-2.2}
pcbY={-27}
pcbRotation="180deg"
schSheetName="camera"
connections={{
GND_1: "net.GND",
GND_2: "net.GND",
GND_3: "net.GND",
GND_4: "net.GND",
GND_5: "net.GND",
GND_6: "net.GND",
GND_7: "net.GND",
GND_8: "net.GND",
SHIELD_1: "net.GND",
SHIELD_2: "net.GND",
I2C_SCL: "net.CAM_I2C_SCL",
I2C_SDA: "net.CAM_I2C_SDA",
RESET_N: "net.CAM_RESET_N",
VCC_3V3_1: "net.VCC_3V3",
VCC_3V3_2: "net.VCC_3V3",
}}
/>
<resistor
name="R10"
resistance="1"
footprint="0402"
pcbX={-8.5}
pcbY={8.5}
schSheetName="camera"
connections={{ pin1: "net.VCC_1V8", pin2: "net.MIPI_AVDD_1V8" }}
/>
<capacitor
name="C7"
capacitance="100nF"
footprint="0402"
pcbX={-8}
pcbY={10.5}
schOrientation="vertical"
schSheetName="camera"
connections={{ pin1: "net.MIPI_AVDD_1V8", pin2: "net.GND" }}
/>
<resistor
name="R7"
resistance="22"
footprint="0402"
pcbX={-10.4}
pcbY={5}
pcbRotation="180deg"
schSheetName="camera"
/>
<resistor
name="R8"
resistance="4.7k"
footprint="0402"
pcbX={-10.4}
pcbY={6.5}
schSheetName="camera"
connections={{ pin1: "net.VCC_1V8", pin2: "net.CAM_I2C_SCL" }}
/>
<resistor
name="R9"
resistance="4.7k"
footprint="0402"
pcbX={-10.4}
pcbY={3.7}
schSheetName="camera"
connections={{ pin1: "net.VCC_1V8", pin2: "net.CAM_I2C_SDA" }}
/>
<trace
name="CAM_MCLK_SRC"
from=".U1 > .MIPI_CLK0_OUT"
to=".R7 > .pin1"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CAM_MCLK"
from=".R7 > .pin2"
to=".J_CAM > .MCLK"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CSI_D0_P"
from=".U1 > .MIPI_CSI_RX_D0P"
to=".J_CAM > .CSI_D0_P"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CSI_D0_N"
from=".U1 > .MIPI_CSI_RX_D0N"
to=".J_CAM > .CSI_D0_N"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CSI_CLK_P"
from=".U1 > .MIPI_CSI_RX_CK0P"
to=".J_CAM > .CSI_CLK_P"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CSI_CLK_N"
from=".U1 > .MIPI_CSI_RX_CK0N"
to=".J_CAM > .CSI_CLK_N"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CSI_D1_P"
from=".U1 > .MIPI_CSI_RX_D1P"
to=".J_CAM > .CSI_D1_P"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<trace
name="CSI_D1_N"
from=".U1 > .MIPI_CSI_RX_D1N"
to=".J_CAM > .CSI_D1_N"
thickness="0.12mm"
maxLength="182.88mm"
routingPhaseIndex={0}
/>
<differentialpair
name="CSI_D0"
positiveConnection="CSI_D0_P"
negativeConnection="CSI_D0_N"
maxLengthSkew="0.6mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.15mm"
maxUncoupledLength="2mm"
/>
<differentialpair
name="CSI_CLK"
positiveConnection="CSI_CLK_P"
negativeConnection="CSI_CLK_N"
maxLengthSkew="0.6mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.15mm"
maxUncoupledLength="2mm"
/>
<differentialpair
name="CSI_D1"
positiveConnection="CSI_D1_P"
negativeConnection="CSI_D1_N"
maxLengthSkew="0.6mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.15mm"
maxUncoupledLength="2mm"
/>
<schematicsheet
name="ethernet"
displayName="100M Ethernet FEPHY"
sheetIndex={6}
></schematicsheet>
{/* Rockchip RV1106G hardware-guide FEPHY reference implementation:
integrated-magnetics RJ45, mandatory 0-ohm pair resistors, 6.04k 1%
EXTR reference resistor, pair TVS reservations, center-tap capacitors,
and a capacitively coupled chassis/shield net. */}
<HR911105A
name="J_ETH"
pcbX={0}
pcbY={27}
pcbRotation="180deg"
schSheetName="ethernet"
connections={{
TD_POS: "net.ETH_TXP",
TD_NEG: "net.ETH_TXN",
RD_POS: "net.ETH_RXP",
RD_NEG: "net.ETH_RXN",
pin4: "net.ETH_TX_CT",
pin5: "net.ETH_RX_CT",
pin8: "net.ETH_SHIELD",
SH1: "net.ETH_SHIELD",
SH2: "net.ETH_SHIELD",
}}
/>
<resistor
name="R14"
resistance="0"
footprint="0402"
pcbX={1.5}
pcbY={12}
schSheetName="ethernet"
connections={{ pin2: "net.ETH_TXP" }}
/>
<resistor
name="R15"
resistance="0"
footprint="0402"
pcbX={3.5}
pcbY={12}
schSheetName="ethernet"
connections={{ pin2: "net.ETH_TXN" }}
/>
<resistor
name="R16"
resistance="0"
footprint="0402"
pcbX={1.5}
pcbY={13.4}
schSheetName="ethernet"
connections={{ pin2: "net.ETH_RXP" }}
/>
<resistor
name="R17"
resistance="0"
footprint="0402"
pcbX={3.5}
pcbY={13.4}
schSheetName="ethernet"
connections={{ pin2: "net.ETH_RXN" }}
/>
<resistor
name="R18"
resistance="6.04k"
footprint="0402"
pcbX={6.5}
pcbY={10.5}
schSheetName="ethernet"
connections={{ pin1: "net.ETH_EXTR", pin2: "net.GND" }}
/>
<chip
name="D3"
manufacturerPartNumber="UDD32C03L01"
footprint="sod323"
pcbX={2.5}
pcbY={15}
pinLabels={{ pin1: "IO1", pin2: "IO2" }}
schSheetName="ethernet"
connections={{ IO1: "net.ETH_TXP", IO2: "net.ETH_TXN" }}
/>
<chip
name="D4"
manufacturerPartNumber="UDD32C03L01"
footprint="sod323"
pcbX={2.5}
pcbY={17}
pinLabels={{ pin1: "IO1", pin2: "IO2" }}
schSheetName="ethernet"
connections={{ IO1: "net.ETH_RXP", IO2: "net.ETH_RXN" }}
/>
<capacitor
name="C44"
capacitance="10nF"
footprint="0402"
pcbX={-1.5}
pcbY={17.2}
schSheetName="ethernet"
connections={{ pin1: "net.ETH_TX_CT", pin2: "net.GND" }}
/>
<capacitor
name="C45"
capacitance="10nF"
footprint="0402"
pcbX={-3.5}
pcbY={17.2}
schSheetName="ethernet"
connections={{ pin1: "net.ETH_RX_CT", pin2: "net.GND" }}
/>
{/* C46 is the guide's 1nF high-voltage shield coupling capacitor;
production selection must be rated for at least 2kV. */}
<capacitor
name="C46"
capacitance="1nF"
footprint="1206"
pcbX={-8.8}
pcbY={16}
schSheetName="ethernet"
connections={{ pin1: "net.ETH_SHIELD", pin2: "net.GND" }}
/>
<trace
name="ETH_TXP_SOC"
from=".U1 > .ETH_PHY_TXP"
to=".R14 > .pin1"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_TXN_SOC"
from=".U1 > .ETH_PHY_TXN"
to=".R15 > .pin1"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_RXP_SOC"
from=".U1 > .ETH_PHY_RXP"
to=".R16 > .pin1"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_RXN_SOC"
from=".U1 > .ETH_PHY_RXN"
to=".R17 > .pin1"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_TXP_LINE"
from=".R14 > .pin2"
to=".J_ETH > .TD_POS"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_TXN_LINE"
from=".R15 > .pin2"
to=".J_ETH > .TD_NEG"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_RXP_LINE"
from=".R16 > .pin2"
to=".J_ETH > .RD_POS"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<trace
name="ETH_RXN_LINE"
from=".R17 > .pin2"
to=".J_ETH > .RD_NEG"
thickness="0.15mm"
routingPhaseIndex={1}
/>
<differentialpair
name="ETH_TX_SOC_PAIR"
positiveConnection="ETH_TXP_SOC"
negativeConnection="ETH_TXN_SOC"
maxLengthSkew="0.762mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.2mm"
maxUncoupledLength="2mm"
/>
<differentialpair
name="ETH_RX_SOC_PAIR"
positiveConnection="ETH_RXP_SOC"
negativeConnection="ETH_RXN_SOC"
maxLengthSkew="0.762mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.2mm"
maxUncoupledLength="2mm"
/>
<differentialpair
name="ETH_TX_LINE_PAIR"
positiveConnection="ETH_TXP_LINE"
negativeConnection="ETH_TXN_LINE"
maxLengthSkew="0.762mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.2mm"
maxUncoupledLength="2mm"
/>
<differentialpair
name="ETH_RX_LINE_PAIR"
positiveConnection="ETH_RXP_LINE"
negativeConnection="ETH_RXN_LINE"
maxLengthSkew="0.762mm"
targetDifferentialImpedance="100ohm"
pcbTraceGap="0.2mm"
maxUncoupledLength="2mm"
/>
<schematicsheet
name="clock-controls"
displayName="Clock, Reset & Boot"
sheetIndex={3}
></schematicsheet>
<crystal
name="Y1"
frequency="24MHz"
loadCapacitance="12pF"
pcbX={8.7}
pcbY={-4.2}
pcbRotation="90deg"
schSheetName="clock-controls"
connections={{ pin1: "net.XIN", pin2: "net.XOUT" }}
footprint={
<footprint>
<smtpad
portHints={["pin1"]}
pcbX={-1.15}
pcbY={0}
width="1.2mm"
height="2.4mm"
shape="rect"
/>
<smtpad
portHints={["pin2"]}
pcbX={1.15}
pcbY={0}
width="1.2mm"
height="2.4mm"
shape="rect"
/>
<silkscreenrect pcbX={0} pcbY={0} width="3.4mm" height="2.7mm" />
<courtyardrect pcbX={0} pcbY={0} width="3.8mm" height="3.1mm" />
</footprint>
}
/>
<capacitor
name="C3"
capacitance="12pF"
footprint="0402"
pcbX={10.2}
pcbY={-6.8}
schOrientation="vertical"
schSheetName="clock-controls"
connections={{ pin1: "net.XIN", pin2: "net.GND" }}
/>
<capacitor
name="C4"
capacitance="12pF"
footprint="0402"
pcbX={10.2}
pcbY={-1.5}
schOrientation="vertical"
schSheetName="clock-controls"
connections={{ pin1: "net.XOUT", pin2: "net.GND" }}
/>
<BLM18AG121SN1D
name="FB2"
pcbX={9.8}
pcbY={-0.2}
schSheetName="clock-controls"
connections={{ pin1: "net.VCC_1V8", pin2: "net.OSC_AVDD1V8" }}
/>
<capacitor
name="C41"
capacitance="100nF"
footprint="0402"
pcbX={10.2}
pcbY={1.5}
schSheetName="clock-controls"
connections={{ pin1: "net.OSC_AVDD1V8", pin2: "net.GND" }}
/>
<BLM18AG121SN1D
name="FB3"
pcbX={9.8}
pcbY={3.5}
schSheetName="processor-core"
connections={{ pin1: "net.VCC_1V8", pin2: "net.ETH_AVDD1V8" }}
/>
<capacitor
name="C42"
capacitance="100nF"
footprint="0402"
pcbX={9.8}
pcbY={5}
schOrientation="vertical"
schSheetName="processor-core"
connections={{ pin1: "net.ETH_AVDD1V8", pin2: "net.GND" }}
/>
<trace
name="OSC_XIN"
from=".U1 > .OSC_XIN"
to=".Y1 > .pin1"
routingPhaseIndex={10}
pcbPathRelativeTo=".U1 > .OSC_XIN"
pcbPath={[
{ x: 7.05, y: -4.375 },
{ x: 7.55, y: -6.35 },
]}
/>
<trace
name="OSC_XOUT"
from=".U1 > .OSC_XOUT"
to=".Y1 > .pin2"
routingPhaseIndex={10}
pcbPathRelativeTo=".U1 > .OSC_XOUT"
pcbPath={[
{ x: 7.05, y: -4.025 },
{ x: 7.55, y: -4.05 },
]}
/>
<resistor
name="R3"
resistance="10k"
footprint="0603"
pcbX={2}
pcbY={-9}
schSheetName="clock-controls"
connections={{ pin1: "net.VCC_3V3", pin2: "net.RESET_N" }}
/>
<capacitor
name="C39"
capacitance="100nF"
footprint="0402"
pcbX={0}
pcbY={-11.5}
schOrientation="vertical"
schSheetName="clock-controls"
connections={{ pin1: "net.RESET_N", pin2: "net.GND" }}
/>
<HX_3x4x2_5_PA_4N_push_button_switch
name="SW1"
pcbX={8}
pcbY={-9.4}
symbol={undefined}
schSheetName="clock-controls"
connections={{
pin1: "net.RESET_N",
pin2: "net.RESET_N",
pin3: "net.GND",
pin4: "net.GND",
}}
/>
<resistor
name="R12"
resistance="10k"
footprint="0402"
pcbX={6.3}
pcbY={-12.3}
schSheetName="clock-controls"
connections={{ pin1: "net.VCC_1V8", pin2: "net.ADC_IN0" }}
/>
<capacitor
name="C40"
capacitance="1nF"
footprint="0402"
pcbX={4.4}
pcbY={-12.3}
schOrientation="vertical"
schSheetName="clock-controls"
connections={{ pin1: "net.ADC_IN0", pin2: "net.GND" }}
/>
<HX_3x4x2_5_PA_4N_push_button_switch
name="SW2"
pcbX={8}
pcbY={-15}
symbol={undefined}
schSheetName="clock-controls"
connections={{
pin1: "net.ADC_IN0",
pin2: "net.ADC_IN0",
pin3: "net.GND",
pin4: "net.GND",
}}
/>
<resistor
name="R11"
resistance="100"
footprint="0402"
pcbX={-6.5}
pcbY={-9}
schSheetName="power-usb"
connections={{ pin1: "net.VCC_3V3", pin2: "net.RTC_AVDD3V3" }}
/>
<capacitor
name="C43"
capacitance="1uF"
footprint="0402"
pcbX={-6.5}
pcbY={-10.5}
schOrientation="vertical"
schSheetName="power-usb"
connections={{ pin1: "net.RTC_AVDD3V3", pin2: "net.GND" }}
/>
<schematicsheet
name="peripherals"
displayName="Flash, Debug & Status"
sheetIndex={4}
></schematicsheet>
<W25Q128JVSIQ
name="U4"
pcbX={-8}
pcbY={-16.5}
schSheetName="peripherals"
connections={{
CS: "net.FSPI_CS",
DI: "net.FSPI_IO0",
DO: "net.FSPI_IO1",
IO2: "net.FSPI_IO2",
IO3: "net.FSPI_IO3",
CLK: "net.FSPI_CLK",
VCC: "net.VCC_3V3",
GND: "net.GND",
}}
/>
<resistor
name="R13"
resistance="22"
footprint="0402"
pcbX={8.5}
pcbY={9.5}
schSheetName="peripherals"
connections={{ pin1: "net.FSPI_CLK_SOC", pin2: "net.FSPI_CLK" }}
/>
<capacitor
name="C5"
capacitance="100nF"
footprint="0402"
pcbX={9.5}
pcbY={7}
schOrientation="vertical"
schSheetName="peripherals"
connections={{ pin1: "net.VCC_3V3", pin2: "net.GND" }}
/>
<led
name="D2"
color="green"
footprint="0603"
pcbX={-3}
pcbY={-12}
schSheetName="peripherals"
connections={{ anode: "net.VCC_3V3", cathode: "net.POWER_LED" }}
/>
<resistor
name="R6"
resistance="1k"
footprint="0603"
pcbX={-3}
pcbY={-14}
schSheetName="peripherals"
connections={{ pin1: "net.POWER_LED", pin2: "net.GND" }}
/>
<schematicsheet
name="gpio-expansion"
displayName="Castellated GPIO Expansion"
sheetIndex={5}
></schematicsheet>
<silkscreentext
text="RV1106G2 PICO"
pcbX={-5.5}
pcbY={12.8}
fontSize="0.8mm"
/>
<silkscreentext text="ETHERNET" pcbX={0} pcbY={15.5} fontSize="0.7mm" />
<silkscreentext text="USB-C" pcbX={0} pcbY={-32.4} fontSize="0.8mm" />
<silkscreentext text="RESET" pcbX={10} pcbY={-6.4} fontSize="0.75mm" />
<silkscreentext text="RECOVERY" pcbX={10} pcbY={-11.8} fontSize="0.65mm" />
<silkscreentext text="PWR" pcbX={9.5} pcbY={-6.5} fontSize="0.65mm" />
<silkscreentext
text="CAMERA 20P 0.5mm"
pcbX={-2.2}
pcbY={-25.5}
fontSize="0.65mm"
/>
<silkscreentext
text={leftEdgePcbLabels[0]!}
pcbX={-10.85}
pcbY={-16.51}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[1]!}
pcbX={-10.85}
pcbY={-13.97}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[2]!}
pcbX={-10.85}
pcbY={-11.43}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[3]!}
pcbX={-10.85}
pcbY={-8.89}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[4]!}
pcbX={-10.85}
pcbY={-6.35}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[5]!}
pcbX={-10.85}
pcbY={-3.81}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[6]!}
pcbX={-10.85}
pcbY={-1.27}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[7]!}
pcbX={-10.85}
pcbY={1.27}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[8]!}
pcbX={-10.85}
pcbY={3.81}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[9]!}
pcbX={-10.85}
pcbY={6.35}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[10]!}
pcbX={-10.85}
pcbY={8.89}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[11]!}
pcbX={-10.85}
pcbY={11.43}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[12]!}
pcbX={-10.85}
pcbY={13.97}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={leftEdgePcbLabels[13]!}
pcbX={-10.85}
pcbY={16.51}
anchorAlignment="center_left"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[0]!}
pcbX={10.85}
pcbY={-16.51}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[1]!}
pcbX={10.85}
pcbY={-13.97}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[2]!}
pcbX={10.85}
pcbY={-11.43}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[3]!}
pcbX={10.85}
pcbY={-8.89}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[4]!}
pcbX={10.85}
pcbY={-6.35}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[5]!}
pcbX={10.85}
pcbY={-3.81}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[6]!}
pcbX={10.85}
pcbY={-1.27}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[7]!}
pcbX={10.85}
pcbY={1.27}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[8]!}
pcbX={10.85}
pcbY={3.81}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[9]!}
pcbX={10.85}
pcbY={6.35}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[10]!}
pcbX={10.85}
pcbY={8.89}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[11]!}
pcbX={10.85}
pcbY={11.43}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[12]!}
pcbX={10.85}
pcbY={13.97}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
<silkscreentext
text={rightEdgePcbLabels[13]!}
pcbX={10.85}
pcbY={16.51}
anchorAlignment="center_right"
fontSize="0.5mm"
/>
</board>
);
