imrishabh18/corne-keyboard

scripts/test-copper-audit.py

import json,subprocess,sys,tempfile,unittest
from pathlib import Path

def fixture():
 j=[{'type':'source_net','source_net_id':'gnd','name':'GND','subcircuit_connectivity_map_key':'gnd'}, {'type':'source_trace','source_trace_id':'s','connected_source_port_ids':['s0','s1'],'connected_source_net_ids':['gnd'],'subcircuit_connectivity_map_key':'gnd'}]
 for i,x in enumerate([0,5]):
  j.extend([{'type':'source_component','source_component_id':f'c{i}','name':f'J{i}'},{'type':'source_port','source_port_id':f's{i}','source_component_id':f'c{i}','name':'GND'},{'type':'pcb_port','pcb_port_id':f'p{i}','source_port_id':f's{i}','x':x,'y':0},{'type':'pcb_smtpad','pcb_smtpad_id':f'pad{i}','pcb_port_id':f'p{i}','shape':'rect','width':1,'height':1,'x':x,'y':0,'layer':'bottom'}])
 return j
def pour(id,x0,x1,holes=[]):
 ring=lambda a,b:{'vertices':[{'x':a,'y':-1},{'x':b,'y':-1},{'x':b,'y':1},{'x':a,'y':1}]}
 return {'type':'pcb_copper_pour','pcb_copper_pour_id':id,'source_net_id':'gnd','layer':'bottom','shape':'brep','brep_shape':{'outer_ring':ring(x0,x1),'inner_rings':holes}}
def audit(j):
 with tempfile.TemporaryDirectory() as d:
  p=Path(d);(p/'in.json').write_text(json.dumps(j))
  subprocess.run([sys.executable,str(Path(__file__).with_name('audit-copper.py')),str(p/'in.json'),str(p/'out.json')],capture_output=True,text=True,check=True)
  return json.loads((p/'out.json').read_text())
class AuditTests(unittest.TestCase):
 def test_same_net_name_does_not_join_separate_pours(self):
  self.assertEqual(audit(fixture()+[pour('a',-1,1),pour('b',4,6)])['physical_ground_groups'],2)
 def test_continuous_pour_connects_without_traces(self):
  self.assertEqual(audit(fixture()+[pour('a',-1,6)])['physical_ground_groups'],1)
 def test_pad_inside_pour_hole_stays_isolated(self):
  hole={'vertices':[{'x':-0.7,'y':-0.7},{'x':.7,'y':-.7},{'x':.7,'y':.7},{'x':-.7,'y':.7}]}
  self.assertEqual(audit(fixture()+[pour('a',-1,6,[hole])])['physical_ground_groups'],2)
 def test_wrong_layer_trace_does_not_connect_bottom_pads(self):
  t={'type':'pcb_trace','pcb_trace_id':'t','source_trace_id':'s','route':[{'route_type':'wire','layer':'top','x':x,'y':0,'width':.15} for x in [0,5]]}
  self.assertEqual(audit(fixture()+[t])['physical_ground_groups'],2)
if __name__=='__main__':unittest.main()