hrithik18k/switch-pcb

A tscircuit package created by hrithik18k.

Version
1.2.0
License
unset
Stars
0

jlc-relay-placement-final.log

placement summary: no placement issues

board top-layer utilization:
- occupied: 15.651% (375.625mm^2 of 2400mm^2)
- empty spaces over 5% of board area:
  - 27.487% (659.695mm^2); bounds=(minX=-10.184mm, maxX=25mm, minY=-24mm, maxY=-5.25mm)
  - 22.468% (539.231mm^2); bounds=(minX=-11.946mm, maxX=25mm, minY=9.405mm, maxY=24mm)
  - 9.867% (236.818mm^2); bounds=(minX=-25mm, maxX=-20.066mm, minY=-24mm, maxY=24mm)

board-edge status:
- K1: 15.11mm inside left edge
- J1: 5.666mm inside left edge
- Q1: 7.5mm inside left edge
- D1: 6.715mm inside left edge
- R1: 6.434mm inside left edge
- R2: 11.434mm inside left edge
- J2: 5.9mm inside right edge

placement drc:
Errors: 0
Warnings: 0