hrithik18k/switch-pcb

jlc-esp-placement-final.log

Detected entrypoint: 'index.circuit.tsx'
placement summary: no placement issues

board top-layer utilization:
- occupied: 27.26% (654.23mm^2 of 2400mm^2)
- empty spaces over 5% of board area:
  - 10.761% (258.26mm^2); bounds=(minX=5.051mm, maxX=25mm, minY=11.054mm, maxY=24mm)
  - 10.09% (242.16mm^2); bounds=(minX=-25mm, maxX=-19.955mm, minY=-24mm, maxY=24mm)
  - 9.551% (229.226mm^2); bounds=(minX=-6.045mm, maxX=12.184mm, minY=-18.5mm, maxY=-5.925mm)

board-edge status:
- U1: 10.574mm inside top edge
- U2: 10.148mm inside bottom edge
- J1: 3.2mm inside bottom edge
- C1: 5.295mm inside left edge
- C2: 11.325mm inside bottom edge
- C3: 12.295mm inside left edge
- C4: 17.295mm inside left edge
- R1: 6.434mm inside left edge
- R2: 6.434mm inside left edge
- R3: 12.434mm inside right edge
- R4: 12.434mm inside right edge
- R5: 12.434mm inside right edge
- R6: 9.434mm inside right edge
- J2: 3.213mm inside bottom edge
- J3: 5.2mm inside right edge
- J4: 5.2mm inside right edge

placement drc:
Errors: 0
Warnings: 0