hrithik18k/switch-pcb

integrated-placement.log

Detected entrypoint: 'index.circuit.tsx'
placement summary: no placement issues

board top-layer utilization:
- occupied: 27.672% (664.123mm^2 of 2400mm^2)
- empty spaces over 5% of board area:
  - 10.64% (255.36mm^2); bounds=(minX=-25mm, maxX=-19.68mm, minY=-24mm, maxY=24mm)
  - 10.548% (253.148mm^2); bounds=(minX=5.051mm, maxX=25mm, minY=11.31mm, maxY=24mm)
  - 9.537% (228.899mm^2); bounds=(minX=-6.32mm, maxX=12.32mm, minY=-18.23mm, maxY=-5.95mm)

board-edge status:
- U1: 10.574mm inside top edge
- U2: 10.148mm inside bottom edge
- J1: 3.25mm inside bottom edge
- C1: 5.575mm inside left edge
- C2: 11.3mm inside bottom edge
- C3: 12.575mm inside left edge
- C4: 17.575mm inside left edge
- R1: 6.575mm inside left edge
- R2: 6.575mm inside left edge
- R3: 12.575mm inside right edge
- R4: 12.575mm inside right edge
- R5: 12.575mm inside right edge
- R6: 9.575mm inside right edge
- J2: 3.25mm inside bottom edge
- J3: 5.25mm inside right edge
- J4: 5.25mm inside right edge

placement drc:
Errors: 0
Warnings: 0