hrithik18k/switch-pcb
A tscircuit package created by hrithik18k.
- Version
- 1.2.0
- License
- unset
- Stars
- 0
debug/esp-jlc-pipeline9.input.simple-route.json
PCB
Schematic
{
"bounds": {
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"maxX": 25,
"minY": -24,
"maxY": 24
},
"obstacles": [
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_0",
"pcb_port_id": "pcb_port_15",
"source_port_name": "TXD0"
},
"componentId": "pcb_component_0",
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"source_trace_45",
"source_port_51",
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"source_net_10",
"pcb_port_15",
"pcb_plated_hole_6",
"pcb_port_51"
]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_14",
"source_port_name": "RXD0"
},
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"pcb_port_14",
"pcb_plated_hole_5",
"pcb_port_52"
]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_13",
"source_port_name": "GPIO5"
},
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]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_12",
"source_port_name": "GPIO4"
},
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{
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]
},
{
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"pcb_port_44"
]
},
{
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"pcb_port_46"
]
},
{
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"pcb_port_id": "pcb_port_8",
"source_port_name": "GND"
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"pcb_port_31",
"pcb_smtpad_29",
"pcb_port_33",
"pcb_smtpad_31",
"pcb_port_35",
"pcb_smtpad_33",
"pcb_port_37",
"pcb_smtpad_43",
"pcb_port_47",
"pcb_smtpad_45",
"pcb_port_49",
"pcb_plated_hole_7",
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},
{
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{
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{
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},
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{
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},
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{
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{
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{
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"pcb_port_34",
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"pcb_plated_hole_13",
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]
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{
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]
},
{
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]
},
{
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{
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},
{
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},
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]
},
{
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},
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{
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"source_port_name": "RST"
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"pcb_plated_hole_3",
"pcb_port_54"
]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_25",
"source_port_name": "NC"
},
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]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_26",
"source_port_name": "VOUT"
},
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"source_port_7",
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"source_net_2",
"pcb_smtpad_14",
"pcb_port_7",
"pcb_port_26",
"pcb_smtpad_30",
"pcb_port_32",
"pcb_smtpad_32",
"pcb_port_34",
"pcb_smtpad_34",
"pcb_port_36",
"pcb_smtpad_35",
"pcb_port_39",
"pcb_smtpad_37",
"pcb_port_41",
"pcb_smtpad_39",
"pcb_port_43",
"pcb_smtpad_41",
"pcb_port_45",
"pcb_plated_hole_13",
"pcb_port_58"
]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_22",
"source_port_name": "VIN"
},
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"source_port_30",
"source_trace_2",
"source_port_24",
"source_trace_1",
"source_port_22",
"source_trace_0",
"source_port_27",
"source_net_0",
"pcb_port_22",
"pcb_smtpad_26",
"pcb_port_24",
"pcb_plated_hole_2",
"pcb_port_27",
"pcb_smtpad_28",
"pcb_port_30",
"pcb_plated_hole_10",
"pcb_port_55"
]
},
{
"circuitJsonMetadata": {
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"pcb_port_id": "pcb_port_23",
"source_port_name": "GND"
},
"componentId": "pcb_component_1",
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"source_trace_14",
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"source_port_49",
"source_trace_12",
"source_port_47",
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"source_port_8",
"source_trace_10",
"source_port_37",
"source_trace_9",
"source_port_35",
"source_trace_8",
"source_port_33",
"source_trace_7",
"source_port_31",
"source_trace_6",
"source_port_23",
"source_trace_5",
"source_port_28",
"source_net_1",
"pcb_smtpad_7",
"pcb_port_8",
"pcb_port_23",
"pcb_plated_hole_1",
"pcb_port_28",
"pcb_smtpad_27",
"pcb_port_31",
"pcb_smtpad_29",
"pcb_port_33",
"pcb_smtpad_31",
"pcb_port_35",
"pcb_smtpad_33",
"pcb_port_37",
"pcb_smtpad_43",
"pcb_port_47",
"pcb_smtpad_45",
"pcb_port_49",
"pcb_plated_hole_7",
"pcb_port_50",
"pcb_plated_hole_9",
"pcb_port_56",
"pcb_plated_hole_12",
"pcb_port_59"
]
},
{
"circuitJsonMetadata": {
"pcb_smtpad_id": "pcb_smtpad_26",
"pcb_port_id": "pcb_port_24",
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"pcb_smtpad_32",
"pcb_port_34",
"pcb_smtpad_34",
"pcb_port_36",
"pcb_smtpad_35",
"pcb_port_39",
"pcb_smtpad_37",
"pcb_port_41",
"pcb_smtpad_39",
"pcb_port_43",
"pcb_smtpad_41",
"pcb_port_45",
"pcb_port_58"
]
},
{
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],
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},
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},
{
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],
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},
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},
{
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],
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},
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},
{
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],
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},
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},
{
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],
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},
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}
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}
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},
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},
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}
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{
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}
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{
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}
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{
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],
"layerCount": 2,
"allowBlindAndBuriedVias": false,
"allowViaInPad": false,
"minTraceWidth": 0.15,
"minViaDiameter": 0.3,
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"minViaHoleEdgeToViaHoleEdgeClearance": 0.1,
"minPlatedHoleDrillEdgeToDrillEdgeClearance": 0.15,
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