hrithik18k/switch-pcb

debug/esp-jlc-pipeline9-failed.log

PCB

Schematic

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
Wrote debug artifact: dist\esp-router\placement-unrouted.png
Autorouting <board#135 /> phase 1/1 start: connections=12, obstacles=66, previous_traces=0, router=tscircuit, solver=AutoroutingPipelineSolver9_PreloadedTraceGraph, effort=5x, cache=miss, cache_id=0f4f0038/f97652c1
  connections: net.V5, net.GND, net.V3V3, net.EN, net.RST, net.BOOT, net.STRAP2, net.STRAP15, net.RELAY, net.TOUCH, net.TXD, net.RXD
Wrote debug artifact: dist\esp-router\phase-0.input.simple-route.json
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=netToPointPairsSolver steps=1 progress=12% iterations_per_second=79 elapsed=1.8s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=portPointPathingSolver steps=9 progress=44% iterations_per_second=4 elapsed=31.8s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=portPointPathingSolver steps=39 progress=44% iterations_per_second=126772 elapsed=42.1s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=portPointPathingSolver steps=67 progress=44% iterations_per_second=80512 elapsed=52.1s
  phase 1/1 progress: solver=AutoroutingPipelineSolver9_PreloadedTraceGraph solver_phase=portPointPathingSolver steps=94 progress=44% iterations_per_second=528 elapsed=66.8s
  phase 1/1 error after 67.0s: DK ran out of iterations (capacity-autorouter@0.0.1018)
Wrote debug artifact: dist\esp-router\phase-0.input.simple-route.json
Wrote debug artifact: dist\esp-router\phase-0.error.json
Async effect error in PcbTraceRender "autorouting":
AutorouterError: DK ran out of iterations (capacity-autorouter@0.0.1018)
    at runCycleAndQueueNextCycle (C:\Users\Hrithik\Documents\Codex\2026-10-28\hey-x20-2\outputs\switch-pcb\node_modules\@tscircuit\core\dist\index.js:145236:24)
    at <anonymous> (C:\Users\Hrithik\Documents\Codex\2026-10-28\hey-x20-2\outputs\switch-pcb\node_modules\@tscircuit\core\dist\index.js:145271:27)
Wrote debug artifact: dist\esp-router\board.meta.json
Circuit JSON written to dist\index\circuit.json
DK ran out of iterations (capacity-autorouter@0.0.1018)
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
Port [J1.pin1] is not connected to net [V5] by a PCB trace.
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
The "J" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />
Port [U2.VIN] is not connected to net [V5] by a PCB trace.
J1 has no pin with requires_power=true
Port [U2.EN] is not connected to net [V5] by a PCB trace.
Port [C1.pin1] is not connected to net [V5] by a PCB trace.
Port [J3.pin1] is not connected to net [V5] by a PCB trace.
Port [J1.pin2] is not connected to net [GND] by a PCB trace.
Port [U2.GND] is not connected to net [GND] by a PCB trace.
Port [C1.pin2] is not connected to net [GND] by a PCB trace.
Port [C2.pin2] is not connected to net [GND] by a PCB trace.
Port [C3.pin2] is not connected to net [GND] by a PCB trace.
Port [C4.pin2] is not connected to net [GND] by a PCB trace.
Port [U1.GND] is not connected to net [GND] by a PCB trace.
Port [R5.pin2] is not connected to net [GND] by a PCB trace.
Port [R6.pin2] is not connected to net [GND] by a PCB trace.
Port [J2.pin1] is not connected to net [GND] by a PCB trace.
Port [J3.pin2] is not connected to net [GND] by a PCB trace.
J1 has no pin with requires_ground=true
All pins on J1 are underspecified (no pinAttributes set)
J2 has no pin with requires_power=true
J2 has no pin with requires_ground=true
All pins on J2 are underspecified (no pinAttributes set)
J3 has no pin with requires_power=true
J3 has no pin with requires_ground=true
All pins on J3 are underspecified (no pinAttributes set)
J4 has no pin with requires_power=true
J4 has no pin with requires_ground=true
All pins on J4 are underspecified (no pinAttributes set)
No <schematicsheet> was found. Add a <schematicsheet> to define the schematic drawing area.
Port [J4.pin2] is not connected to net [GND] by a PCB trace.
Port [U2.VOUT] is not connected to net [V3V3] by a PCB trace.
Port [U1.VCC] is not connected to net [V3V3] by a PCB trace.
Port [C2.pin1] is not connected to net [V3V3] by a PCB trace.
Port [C3.pin1] is not connected to net [V3V3] by a PCB trace.
Port [C4.pin1] is not connected to net [V3V3] by a PCB trace.
Port [R1.pin2] is not connected to net [V3V3] by a PCB trace.
Port [R2.pin2] is not connected to net [V3V3] by a PCB trace.
Port [R3.pin2] is not connected to net [V3V3] by a PCB trace.
Port [R4.pin2] is not connected to net [V3V3] by a PCB trace.
Port [J4.pin1] is not connected to net [V3V3] by a PCB trace.
Port [U1.EN] is not connected to net [EN] by a PCB trace.
Port [R1.pin1] is not connected to net [EN] by a PCB trace.
Port [U1.RST] is not connected to net [RST] by a PCB trace.
Port [R2.pin1] is not connected to net [RST] by a PCB trace.
Port [J2.pin5] is not connected to net [RST] by a PCB trace.
Port [U1.GPIO0] is not connected to net [BOOT] by a PCB trace.
J2 is inferred to face x+ from its cable insertion center because no explicit footprint insertionDirection is defined, but should face y- so the connector is accessible from the board edge. Set insertionDirection on the <footprint> to specify the actual direction in the footprint's unrotated orientation; for example, <footprint insertionDirection="from_above"> for a connector accessed from above the PCB (+Z).
Port [R3.pin1] is not connected to net [BOOT] by a PCB trace.
Port [J2.pin4] is not connected to net [BOOT] by a PCB trace.
Port [U1.GPIO2] is not connected to net [STRAP2] by a PCB trace.
Port [R4.pin1] is not connected to net [STRAP2] by a PCB trace.
Port [U1.GPIO15] is not connected to net [STRAP15] by a PCB trace.
Port [R5.pin1] is not connected to net [STRAP15] by a PCB trace.
Port [U1.GPIO12] is not connected to net [RELAY] by a PCB trace.
Port [J3.pin3] is not connected to net [RELAY] by a PCB trace.
Port [R6.pin1] is not connected to net [RELAY] by a PCB trace.
Port [U1.GPIO13] is not connected to net [TOUCH] by a PCB trace.
Port [J4.pin3] is not connected to net [TOUCH] by a PCB trace.
Port [U1.TXD0] is not connected to net [TXD] by a PCB trace.
Port [J2.pin2] is not connected to net [TXD] by a PCB trace.
Port [U1.RXD0] is not connected to net [RXD] by a PCB trace.
Port [J2.pin3] is not connected to net [RXD] by a PCB trace.
Generating preview images...
[index] Generating PCB PNG...
[index] Written pcb.png
[index] Generating schematic PNG...
[index] Written schematic.png

Build complete
  Circuits  0 passed 1 failed
  Options   pcb-png, schematic-png, autorouter-debug, autorouter-dump-srj
  Output    dist

⚠ Build completed with errors
Build exiting with code 1: circuit build errors occurred