hrithik18k/air-mouse

checks/check-shorts/pcb.svg

PCB

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class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="367.58490964526163" cy="223.79623266285813" r="1.2083159923485967" data-type="pcb_via" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="367.58490964526163" cy="223.79623266285813" r="0.8055439948990645" data-type="pcb_via" data-pcb-layer="drill"/></g><g data-type="pcb_via" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="341.0905676530314" cy="203.01319759446227" r="1.2083159923485967" data-type="pcb_via" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="341.0905676530314" cy="203.01319759446227" r="0.8055439948990645" data-type="pcb_via" data-pcb-layer="drill"/></g><g data-type="pcb_via" data-pcb-layer="through"><circle class="pcb-hole-outer" fill="rgb(200, 52, 52)" cx="348.2115765679391" cy="210.158372829217" r="1.2083159923485967" data-type="pcb_via" data-pcb-layer="top"/><circle class="pcb-hole-inner" fill="#FF26E2" cx="348.2115765679391" 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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 1: U4.NC6 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
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    <circle cx="391.40" cy="329.73" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 2: U4.REGOUT, C8.pin1, source_trace_70_0 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
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    <circle cx="408.31" cy="329.73" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 3: U4.NC3 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
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    <circle cx="410.49" cy="348.94" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 4: U4.NC7 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
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    <circle cx="389.40" cy="331.92" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 5: U4.RESV2 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
    <circle cx="389.40" cy="348.94" r="14" fill="none" stroke="#9b5cff" stroke-width="4"/>
    <circle cx="389.40" cy="348.94" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 6: U4.RESV3 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
    <circle cx="391.40" cy="350.96" r="14" fill="none" stroke="#9b5cff" stroke-width="4"/>
    <circle cx="391.40" cy="350.96" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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  <g data-type="short-debug" data-mode="gerber" data-layer="top">
    <title>SHORT 7: U4.NC2 &lt;-&gt; pcb_plated_hole_0, pcb_plated_hole_1, J1.A1B12, J1.B1A12, R1.pin2, R2.pin2, U2.VSS, R3.pin2, C1.pin2, C2.pin2, pcb_plated_hole_5, U3.GND, C3.pin2, C4.pin2, U1.GND1, U1.GND2, U1.GND3, U1.GND4, C5.pin2, C6.pin2, C7.pin2, SW2.pin2, SW3.pin2, pcb_plated_hole_7, U4.CLKIN, U4.AD0, U4.FSYNC, U4.GND, U4.EP, C8.pin2, C9.pin2, C10.pin2, SW4.pin2, SW5.pin2, source_net_1_mst0_0, source_net_1_mst1_0, source_net_1_mst2_0, source_net_1_mst3_0, source_net_1_mst4_0, source_net_1_mst5_0, source_net_1_mst6_0, source_net_1_mst7_0, source_net_1_mst8_0, source_net_1_mst9_0, source_net_1_mst10_0, source_net_1_mst11_0, source_net_1_mst12_0, source_net_1_mst13_0, source_net_1_mst14_0, source_net_1_mst15_0, source_net_1_mst16_0, source_net_1_mst17_0, source_net_1_mst18_0, source_net_1_mst19_0, source_net_1_mst20_0, source_net_1_mst21_0, source_net_1_mst22_0, source_net_1_mst23_0, source_net_1_mst24_0, source_net_1_mst25_0, source_net_1_mst26_0, source_net_1_mst27_0, source_net_1_mst28_0, source_net_1_mst29_0, source_net_1_mst30_0, source_net_1_mst31_0, source_net_1_mst32_0, pcb_via_3, pcb_via_4, pcb_via_5, pcb_via_6, pcb_via_7, pcb_via_8, pcb_via_9, pcb_via_10, pcb_via_11, pcb_via_12, pcb_via_13, pcb_via_14</title>
    <circle cx="408.31" cy="350.96" r="14" fill="none" stroke="#9b5cff" stroke-width="4"/>
    <circle cx="408.31" cy="350.96" r="6" fill="none" stroke="#9b5cff" stroke-width="3"/>
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