gokul/usb3-sd-hub
Engineering draft: four-layer, computer-powered USB 3 hub with one USB-C host socket, two USB-C and two USB-A accessory sockets, and a full-size SD slot. Board and three schematic previews are available. Routing and production checks are incomplete; not fabrication ready.
- Version
- 0.1.4
- License
- unset
- Stars
- 0
sheets/HubAndPorts.tsx
import { SchematicNote } from "../components/SchematicNote";
import { placementFor } from "../design/placement";
import { Electrolytic63, Vssop8 } from "../components/ComponentFootprints";
import { UsbCReceptacle } from "../imports/UsbCReceptacle";
import { UsbAReceptacle } from "../imports/UsbAReceptacle";
import { HD3SS3220RNHR } from "../imports/HD3SS3220RNHR";
import { TPS2553DBVR } from "../imports/TPS2553DBVR";
import { SN74LVC2G04DBVR } from "../imports/SN74LVC2G04DBVR";
import { usbCPinLabels, usbAPinLabels } from "../design/pinouts";
import { muxConnections, usbCConnections } from "../design/connections";
import { hubSignalPinLabels } from "../components/Controllers";
import { Passives, Indicator, type PassiveSpec } from "../components/Passives";
import { EsdBank } from "../components/EsdBank";
const ports = [
{ number: 1, pcbX: 25, pcbY: 0 },
{ number: 2, pcbX: 14, pcbY: 19 },
{ number: 3, pcbX: 30, pcbY: 19 },
{ number: 4, pcbX: 25, pcbY: -15 },
];
const parts: PassiveSpec[] = ports.flatMap((port) => [
{
name: `R_P${port.number}_ILIM`,
kind: "resistor",
rating: "169k",
pcbX: port.pcbX - 3,
pcbY: port.pcbY - 3,
from: `P${port.number}_ILIM`,
to: "GND",
},
{
name: `R_P${port.number}_CTRL`,
kind: "resistor",
rating: "10k",
pcbX: port.pcbX - 3,
pcbY: port.pcbY - 1.5,
from: "VDD33",
to: `PWR${port.number}`,
},
{
name: `C_P${port.number}_IN`,
kind: "capacitor",
rating: "1uF",
pcbX: port.pcbX - 3,
pcbY: port.pcbY,
from: "VBUS_HUB",
to: "GND",
},
{
name: `C_P${port.number}_OUT`,
kind: "capacitor",
rating: "150uF",
footprint: <Electrolytic63 />,
manufacturerPartNumber: "EEEFK1A151AP",
pcbX: port.pcbX + 3.5,
pcbY: port.pcbY - 3,
from: `P${port.number}_VBUS`,
to: "GND",
},
{
name: `C_D${port.number}_TXP`,
kind: "capacitor",
rating: "100nF",
pcbX: port.pcbX - 6,
pcbY: port.pcbY + 2,
from: `D${port.number}_TXP`,
to: `D${port.number}_TXP_AC`,
},
{
name: `C_D${port.number}_TXN`,
kind: "capacitor",
rating: "100nF",
pcbX: port.pcbX - 6,
pcbY: port.pcbY + 0.5,
from: `D${port.number}_TXN`,
to: `D${port.number}_TXN_AC`,
},
]);
export const HubAndPorts = () => (
<schematicsheet
name="Hub and USB Ports"
sheetIndex={1}
sheetWidth="841mm"
sheetHeight="594mm"
>
<group
pcbAnchorAlignment="center"
pcbX="0mm"
pcbY="0mm"
pcbLayout={{ layoutMode: "none" }}
schAutoLayoutEnabled
>
<schematicbox
name="HUB_PORTS"
chipRef=".U_HUB"
width={6}
height={4.8}
title="USB5816C: four external 5 Gbps ports, internal SD reader"
pinLabels={hubSignalPinLabels}
/>
<SchematicNote
chipName="HUB_PORTS"
text={"Six-port 5 Gbps hub\nFour accessory ports; internal SD reader"}
/>
<group
pcbAnchorAlignment="center"
pcbX="0mm"
pcbY="0mm"
pcbLayout={{ layoutMode: "none" }}
schTitle="Two USB-A accessory ports"
schGrid
gridCols={2}
gridGap={8}
>
{[
{ number: 2, pcbX: 10 },
{ number: 3, pcbX: 26 },
].map((port) => (
<UsbAReceptacle
key={port.number}
name={`J_A${port.number - 1}`}
manufacturerPartNumber="48393-0001"
pcbX={port.pcbX}
pcbY={21}
pcbRotation={180}
pinLabels={usbAPinLabels}
connections={{
VBUS: `net.P${port.number}_VBUS`,
DM: `net.D${port.number}_DM`,
DP: `net.D${port.number}_DP`,
GND: "net.GND",
GND_DRAIN: "net.GND",
SHIELD: "net.GND",
RXN: `net.D${port.number}_RXN`,
RXP: `net.D${port.number}_RXP`,
TXN: `net.D${port.number}_TXN_AC`,
TXP: `net.D${port.number}_TXP_AC`,
}}
/>
))}
</group>
<group
pcbAnchorAlignment="center"
pcbX="0mm"
pcbY="0mm"
pcbLayout={{ layoutMode: "none" }}
schTitle="Two reversible USB-C accessory ports; attachment-controlled VBUS"
schAutoLayoutEnabled
>
{[
{ number: 1, pcbY: 0 },
{ number: 4, pcbY: -15 },
].map((port) => (
<group
pcbAnchorAlignment="center"
pcbX="0mm"
pcbY="0mm"
pcbLayout={{ layoutMode: "none" }}
key={port.number}
>
<UsbCReceptacle
name={`J_C${port.number === 1 ? 1 : 2}`}
manufacturerPartNumber="12401548E4#2A"
pcbX={38}
pcbY={port.pcbY}
pcbRotation={90}
pinLabels={usbCPinLabels}
connections={usbCConnections({
prefix: `D${port.number}`,
vbus: `P${port.number}_VBUS`,
})}
/>
<HD3SS3220RNHR
name={`U_C${port.number}_MUX`}
pcbX={30}
pcbY={port.pcbY + 4}
connections={muxConnections({
prefix: `D${port.number}`,
source: `D${port.number}`,
upstream: false,
vbus: `P${port.number}_VBUS`,
})}
/>
<Passives
parts={[
{
name: `R_D${port.number}_SENSE`,
kind: "resistor",
rating: "887k",
pcbX: 32,
pcbY: port.pcbY - 4,
from: `P${port.number}_VBUS`,
to: `D${port.number}_VBUS_SENSE`,
},
{
name: `R_D${port.number}_ID`,
kind: "resistor",
rating: "200k",
pcbX: 30,
pcbY: port.pcbY - 4,
from: "VDD33",
to: `D${port.number}_ID`,
},
{
name: `R_D${port.number}_DIR`,
kind: "resistor",
rating: "200k",
pcbX: 28,
pcbY: port.pcbY - 4,
from: "VDD33",
to: `D${port.number}_DIR`,
},
{
name: `C_D${port.number}_33`,
kind: "capacitor",
rating: "100nF",
pcbX: 27,
pcbY: port.pcbY + 6,
from: "VDD33",
to: "GND",
},
{
name: `C_D${port.number}_5`,
kind: "capacitor",
rating: "100nF",
pcbX: 27,
pcbY: port.pcbY + 4.5,
from: "VBUS_HOST",
to: "GND",
},
]}
/>
<EsdBank
prefix={`C${port.number}`}
signals={[
`D${port.number}_DP`,
`D${port.number}_DM`,
`D${port.number}_TX1P`,
`D${port.number}_TX1N`,
`D${port.number}_RX1P`,
`D${port.number}_RX1N`,
`D${port.number}_TX2P`,
`D${port.number}_TX2N`,
`D${port.number}_RX2P`,
`D${port.number}_RX2N`,
`D${port.number}_CC1`,
`D${port.number}_CC2`,
]}
pcbX={26.5}
pcbY={port.pcbY}
vertical
/>
</group>
))}
</group>
<group
pcbAnchorAlignment="center"
pcbX="0mm"
pcbY="0mm"
pcbLayout={{ layoutMode: "none" }}
schTitle="Per-port current limiting and overcurrent feedback"
schGrid
gridCols={2}
gridGap={5}
>
{ports.map((port) => (
<TPS2553DBVR
key={port.number}
name={`U_P${port.number}_SW`}
pcbX={port.pcbX}
pcbY={port.pcbY}
connections={{
IN: "net.VBUS_HUB",
GND: "net.GND",
EN: `net.${port.number === 1 || port.number === 4 ? `P${port.number}_ENABLE` : `PWR${port.number}`}`,
FAULT: `net.PWR${port.number}`,
ILIM: `net.P${port.number}_ILIM`,
OUT: `net.P${port.number}_VBUS`,
}}
/>
))}
<SN74LVC2G04DBVR
name="U_ATTACH_INV"
pcbX={15}
pcbY={-2}
connections={{
pin1: "net.D1_ID",
pin2: "net.GND",
pin3: "net.D4_ID",
pin4: "net.D4_ATTACHED",
pin5: "net.VDD33",
pin6: "net.D1_ATTACHED",
}}
/>
<chip
name="U_ATTACH_AND"
manufacturerPartNumber="SN74LVC2G08DCUR"
pcbX={15}
pcbY={-7}
pinAttributes={{
pin4: { requiresGround: true },
pin8: {
requiresPower: true,
requiresVoltage: "3.3V",
requiredVoltageTolerance: "10%",
},
}}
pinLabels={{
pin1: "A1",
pin2: "B1",
pin3: "Y2",
pin4: "GND",
pin5: "A2",
pin6: "B2",
pin7: "Y1",
pin8: "VCC",
}}
{...placementFor("U_ATTACH_AND")}
footprint={<Vssop8 />}
connections={{
A1: "net.PWR1",
B1: "net.D1_ATTACHED",
Y1: "net.P1_ENABLE",
A2: "net.PWR4",
B2: "net.D4_ATTACHED",
Y2: "net.P4_ENABLE",
VCC: "net.VDD33",
GND: "net.GND",
}}
>
<SchematicNote
text={
"Dual attachment / power-enable AND\n1.65–5.5 V supply; 3.3 V here"
}
/>
</chip>
</group>
<Passives parts={parts} />
<Passives
parts={[
{
name: "C_ATTACH_INV",
kind: "capacitor",
rating: "100nF",
pcbX: 12,
pcbY: -2,
from: "VDD33",
to: "GND",
},
{
name: "C_ATTACH_AND",
kind: "capacitor",
rating: "100nF",
pcbX: 12,
pcbY: -7,
from: "VDD33",
to: "GND",
},
{
name: "C_FLASH",
kind: "capacitor",
rating: "100nF",
pcbX: 15,
pcbY: 9,
from: "VDD33",
to: "GND",
},
]}
/>
{[2, 3].map((number) => (
<EsdBank
key={number}
prefix={`A${number}`}
signals={[
`D${number}_DP`,
`D${number}_DM`,
`D${number}_TXP_AC`,
`D${number}_TXN_AC`,
`D${number}_RXP`,
`D${number}_RXN`,
]}
pcbX={number === 2 ? 5 : 21}
pcbY={17.2}
/>
))}
{ports.map((port) => (
<Indicator
key={port.number}
name={`LED_P${port.number}`}
net={`P${port.number}_VBUS`}
pcbX={port.pcbX - 1}
pcbY={port.pcbY - 5.5}
/>
))}
</group>
</schematicsheet>
);
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