gokul/usb3-sd-hub

README.md

# USB 3 hub with full-size SD — engineering draft

**NOT FOR FABRICATION. Routing, configuration and production qualification remain incomplete.**

A computer-powered hub with one female USB-C host socket, two downstream USB-C sockets, two downstream USB-A sockets and one full-size SD socket. The user chose computer power only and accepted that some peripheral combinations may exceed the available power. No extra charger input is included. The design has no intended host-charging function. No boards or components have been ordered.

## Public preview and editable source

The editable board is `index.circuit.tsx`. `index.tsx` forwards to it for compatibility with earlier downloads. Public builds select only the board entry, excluding verification reproductions from board discovery.

`bun run build:preview` generates the placed board and all three schematics with PCB routing disabled. This is a preview of the unfinished design. `bun run build:routing` uses the local router for the remaining routing work, with cloud routing disabled. `tsci build --ci` uses the preview command for public package rendering.

## Current design

- 86 × 68 mm, four copper layers, nominal 1.6 mm thickness; all 229 assembly components are on the top side. Every assembly component has an exact manufacturer part number. Selection is distinct from completed qualification or stock availability.
- Exactly three generated schematic sheets: Host and Power, Hub and USB Ports, and Full-size SD Reader. All 230 symbol representations and 724 schematic traces are generated; the drawings have no native error records or invalid Circuit JSON records. The source contains no authored `schX` or `schY` properties. Chip function and rating notes are included. Large 841 × 594 mm sheets keep the generated drawings inside their borders; functional layout still needs production review.
- tscircuit 0.0.2825, core 0.0.2129, capacity-autorouter 0.0.969, schematic-trace-solver 0.0.214 and circuit-json 0.0.526. Local routing is explicitly selected and cloud routing is disabled.
- Microchip USB5816C-I/KD hub, four external USB 3 ports with a 5 Gbps design target, and an internal USB 2.0 connection to the USB2642-I/ML SD reader. The disabled sixth port and unused reader ports require consistent configuration.
- Hirose DM1AA-SF-PEJ(82) full-size SD socket. Its custom land pattern follows manufacturer drawing EDC3-153736-02 revision 3. The card-detect switch closes on insertion; the write-protect switch closes when writes are enabled. The SD reader's USB 2.0 connection limits transfer speed independently of the four USB 3 ports.
- HD3SS3220 Type-C orientation / CC controllers; TPS2553 current-limited power switches; sequenced 1.2 V and 3.3 V supplies.
- Main power LED, four port-power LEDs, SD power LED and card-present LED. The port LEDs show powered VBUS, not USB traffic.

The selected fabrication profile is JLCPCB JLC04161H-3313, four layers, 1.6 mm nominal, with controlled impedance. The official calculator gave about 0.136 mm top-layer trace width and 0.150 mm pair gap for 90 Ω differential impedance. See `verification/JLCPCB-STACKUP.md`. Those dimensions are design inputs; completed routing and the fabricator's impedance coupon are still required.

## Remaining release work

1. Complete routing using the final component placement. The current native upstream TX candidate matches lengths but fails coupling: the pair follows separate paths for more than the permitted 2 mm. It is rejected and excluded from manufacturing exports. See `verification/routing-check.json` and `usb-pair-diagnostic.png`. Check every connection, clearances, USB pair lengths and coupling, USB 2.0 paths, ESD branches and return-current paths. A router stage finishing does not establish that its output satisfies the pair constraints. Published placement exports contain no routed PCB signal traces.
2. Review the three complete schematic drawings for functional grouping and production review. Automatic trace generation finishes and all elements are inside the sheet borders; long connections and three non-default-sheet styling warnings remain.
3. Produce verified hub and reader configuration / programming images. Blank flash and EEPROM parts are not validated configuration. Check bus-powered descriptors, the internal reader's non-removable status, unused ports, startup and overcurrent behavior. No validated programming image is included.
4. Validate the shared power budget, current before enumeration, suspend current, inrush, voltage drop, current-limit behavior and reverse-current behavior. Do not claim universal host compatibility or simultaneous full-power use of all four ports. See `verification/POWER-DECISION.md`.
5. Finish footprint and mechanical qualification, including connector mating access, exact QFN land patterns, SD contacts and assembly orientation. The SD footprint has an explicit bottom-edge insertion direction. Approximate 3D bodies do not establish mechanical fit.
6. Qualify effective capacitor values at operating voltage and confirm assembly rotations against the selected assembler's library. Exact part numbers alone do not establish these.
7. Review QFN stencil apertures and thermal vias. The exposed-pad paste aperture is a reduced solid rectangle. The design does not yet specify filled/capped via-in-pad manufacturing; bottom tenting alone is insufficient qualification.
8. Inspect final routed Gerbers and drill files with independent manufacturing checks. The current diagnostic manufacturing files have been independently parsed and rendered, but they contain no signal routing. Prototype USB interoperability, power, signal-integrity and EMC testing remains necessary for a production product.

## Verification files

`index.circuit.tsx` is the editable entry point. `components/`, `sheets/`, `design/` and `imports/` contain the source. The project uses scoped compatibility adapters for Circuit JSON display offsets and automatic schematic layout; these are disclosed in their source comments. Inner layers are intended as ground references. The pair router searches top/bottom copper and preserves through-via barrels across all four layers.

`verification/placement-only.circuit.json` contains the placed components. `verification/schematics.circuit.json`, the three schematic SVG / PNG files and `three-schematics.svg` include generated schematic traces. Neither snapshot includes completed PCB routing. The engineering BOM contains exact manufacturer numbers for all 229 assembly parts. Fiducials, markings and via primitives are not additional parts to buy.

`verification/NOT-FOR-FABRICATION-gerbers.zip` is a diagnostic export. It contains copper, mask, paste, silkscreen, outline, plated/non-plated drills, BOM and placement CSVs. `gerber-preview.png` shows independently parsed copper, top mask/paste, silkscreen and outline. All 12 Gerber layers pass PyGerber 2.4.3 parsing with errors set to raise; a rectangular aperture rotation probe passes. Both drill files are parsed separately with Gerbonara 1.6.3 and their SVG views are included. Export success is not fabrication approval. Do not send this ZIP to a fabricator.

The current build corrects both four-pad crystal pin variants, separates the SD socket's shell contacts into their physical ports, and moves the upstream TX AC capacitors to free routing space. It retains the original connector count and computer-only power arrangement.

`verification/VERIFICATION.md` and `validation-summary.json` record the current checks. `TOOL-ISSUES.md` collects confirmed tool problems and reproductions. Routing delays, this board's unfinished decisions and local setup errors are not classified as upstream bugs. No upstream issues or pull requests have been opened for this task.

## Reproduce

Install dependencies with Bun and run `bun x tsc --noEmit`. Build `index.circuit.tsx` with the tscircuit CLI. Keep `autorouter="auto-local"` and `useCloudAutorouter: false`. A full routing build is not yet a passing release check.

## References and attribution

Circuit references include [Microchip USB5816C, DS00003186C](https://www.microchip.com/en-us/product/usb5816c), [USB2642, DS00001578F](https://www.microchip.com/en-us/product/usb2642), [TI HD3SS3220](https://www.ti.com/product/HD3SS3220), TPS2553, TPS62160 and TI USB layout guide SLLA414. The full-size socket reference is [Hirose DM1AA-SF-PEJ(82)](https://www.hirose.com/en/product/p/CL0609-0004-8-82). Manufacturer drawings are references, not redistributed authored design material.

USB connector footprints were converted from KiCad library footprints. Original and normalized copies are retained in `footprints/`. The obsolete TE SD footprint there is historical reference and is not used by the current design. Legacy model `at` syntax was normalized to `offset`; an unsupported generated pill-hole `height` property was removed.

Authored project code is MIT licensed. Redistributed KiCad library material retains CC-BY-SA 4.0 with the KiCad library exception; see `footprints/LICENSE-KiCad.md` and [KiCad's license page](https://www.kicad.org/libraries/license/).