astra/f1c100s

The code defines the physical pin layout, labels, and footprint for the F1C100S system-on-chip (SoC) component used in electronic devices.

Version
0.9.2
License
unset
Stars
0

src/generated/native.trace-paths.json

PCBPCB preview for src/generated/native.trace-paths.json
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[
  {
    "connection": "U1.pin1",
    "route": [
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        "x": -4.99999,
        "y": 4.19989,
        "width": 0.12,
        "layer": "top"
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      },
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      },
      {
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        "from_layer": "top",
        "to_layer": "inner1",
        "via_diameter": 0.45,
        "via_hole_diameter": 0.2
      },
      {
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      {
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      {
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      {
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        "route_type": "wire",
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    ]
  },
  {
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        "route_type": "wire",
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      {
        "route_type": "wire",
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      {
        "route_type": "wire",
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        "route_type": "wire",
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      {
        "route_type": "wire",
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        "route_type": "wire",
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    ]
  },
  {
    "connection": "U1.pin4",
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    ]
  },
  {
    "connection": "C_D4.pin1",
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        "route_type": "wire",
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    ]
  },
  {
    "connection": "C_B_VCC_HP.pin1",
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  {
    "connection": "U1.pin5",
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      {
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        "route_type": "wire",
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        "via_hole_diameter": 0.2
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      {
        "route_type": "wire",
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    ]
  },
  {
    "connection": "U1.pin20",
    "route": [
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        "route_type": "wire",
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      {
        "route_type": "wire",
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        "route_type": "wire",
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      },
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        "via_hole_diameter": 0.2
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      {
        "route_type": "wire",
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