abse/smartwatch-flex-top-only

Three-panel flex smartwatch with two parallel R3.9 bends, all components flat-top, low-profile JST connector harnesses, split heartbeat optical windows and screw-retained PCB mounting. Modeled 39 × 50.5 × 14.5mm prototype; 100% routing, zero native DRC and shorts. Hardware qualification pending.

Version
0.2.20
License
unset
Stars
0

scripts/audit-pour-board-edge.py

from pathlib import Path
import hashlib,json,sys
from shapely.geometry import Polygon
from shapely import make_valid
source_file,output_file=sys.argv[1:]
raw=Path(source_file).read_bytes();c=json.loads(raw)
board=next(e for e in c if e['type']=='pcb_board')
allowed=Polygon([(p['x'],p['y']) for p in board['outline']]).buffer(-.3)
for hole in (e for e in c if e['type']=='pcb_cutout'):
 assert hole['shape']=='polygon'
 allowed=allowed.difference(Polygon([(p['x'],p['y']) for p in hole['points']]).buffer(.3))
failures=[];count=0
for e in (e for e in c if e['type']=='pcb_copper_pour'):
 b=e['brep_shape'];p=Polygon([(v['x'],v['y']) for v in b['outer_ring']['vertices']],holes=[[(v['x'],v['y']) for v in h['vertices']] for h in b['inner_rings']])
 copper=p if p.is_valid else make_valid(p)
 area=copper.difference(allowed.buffer(1e-6)).area
 if area>1e-8:failures.append({'pour':e['pcb_copper_pour_id'],'outsideAllowedCopperAreaMM2':area})
 count+=1
r={'status':'FAIL' if failures else 'PASS','sourceFile':source_file,'sourceSha256':hashlib.sha256(raw).hexdigest(),'minBoardAndCutoutEdgeMM':.3,'generatedPoursChecked':count,'failures':failures,'method':'Actual native BREP copper, with every hole, against the true board outline inset 0.3mm and every cutout expanded 0.3mm; 1um geometric tolerance.'}
Path(output_file).write_text(json.dumps(r,indent=2)+'\n');print(json.dumps(r,indent=2));assert not failures