abse/rp2350-mcu-board

RP2350_ROUTING_VERIFICATION_2026-09-04.md

# RP2350 complete-board routing verification

**Historical six-layer report.** The local main board is now an unpublished four-layer trial; see [its separate report](RP2350_FOUR_LAYER_VERIFICATION_2026-09-04.md). The six-layer source and output are preserved under [the backup directory](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-four-layer-20260904/six-layer-source/index.circuit.tsx). Published version 0.0.7 was not modified by the local four-layer work.

Verified 2026-09-04. **Routing target met. Not an assembly/fabrication release.** The GPIO-header supplier mismatch below still requires approval, and final manufacturer DFM/hardware validation remain separate.

This report concerns the complete `index.circuit.tsx` board in `/Users/abdolsalamallawlabi/rp2350-mcu-board`, not the standalone essentials entrypoint or an autorouter reproduction.

## Final measured results

| Check | Result |
| --- | --- |
| Typecheck | Pass |
| Explicit full `index.circuit.tsx` build/render | Pass |
| Generated DRC errors | **0** |
| All-layer Gerber short-circuit check | **0 shorts** |
| Independent physical copper connectivity | **58/58 required nets connected; 0 opens, 0 shorts, 0 unresolved pads** |
| Crystal signal paths | **0 vias; longest 9.489175 mm, within 10 mm** |
| Constrained two-port paths | 28/28 pass |
| Constrained fanouts to geometrically verified plane contacts | 18/18 pass |
| Required 0.12 mm connectivity | 37/37 nets pass |
| Required 0.3 mm connectivity | 3/3 nets pass |
| Via-hole spacing / drill-to-unrelated-track check | 0 / 0 violations |
| Published via-count, continuity, board-edge and via-in-pad checks | 0 findings |
| Original values, JLCPCB selections, source-net memberships, specified widths and limits | Preserved |
| Crystal and five edge-connector placements | Preserved |

The final build contains 51 components, 178 source traces, 183 PCB traces, 129 via records representing 127 unique via drills, and eight generated BREP copper-pour regions. It is a 48 × 64 mm, six-layer board. Via drill/pad sizes are 0.2/0.45 mm. Copper-clearance checks were not relaxed.

The final PCB geometry exactly matches the independently checked `c15-outward-escape` candidate. The final explicit index output was checked again, not accepted solely because the build command exited successfully.

## What changed

- The MCU essentials use ordinary placement groups within the full-board routing scope, not a separately routed internal subcircuit.
- Capacitors and the regulator/BOOTSEL area were repositioned to provide routing space and short local connections. C6 and C10 were aligned with their supply pins; C11, C14 and C16 were moved closer to their associated MCU pins.
- The four SWD test pads were moved together to the SWD-pin side of the MCU, preserving their 2.5 mm pitch. The actual edge connectors remained fixed.
- Normal fanout directions keep supply/ground escapes clear of the crystal corridor. C15 retains its own ground-plane escape.
- Explicit pours serve GND on inner1, 3.3 V on inner2, VBUS on inner3 and 1.1 V on inner4. The solver generated one GND region, two 3.3 V regions, two VBUS regions and three 1.1 V regions; physical connectivity was checked across the complete copper, including these regions.

The project uses published `tscircuit@0.0.2462`, still the latest registry version when checked, with Pipeline 9. No autorouter implementation, local dependency override, local tarball, patch, manual route, or hardcoded via was used. No router repository, PR or unrelated project was changed.

## Warnings retained — not hidden

The final circuit JSON contains **55 warnings**, not zero warnings:

- 25 missing-courtyard warnings.
- 14 supplier-footprint similarity warnings, including the real header mismatch below.
- 14 pin/power/ground specification warnings.
- Two full stored-route length warnings described below.

The separately invoked published width checker also emits 11 net-wide width warnings because the supply/ground nets contain both narrow local branches and wider specified paths. Independent required-width connectivity checks pass for the specified paths. This is not a certification of every copper-pour neck, thermal-spoke current capacity, or complete fabrication DFM.

### Stored-route length versus actual connection to a plane

These two generated routes continue after they have already reached their connected plane. The native warnings are retained. The additional check flood-fills the actual same-net pour and physical via copper; it does not trust `is_inside_copper_pour` labels. Whole-board physical connectivity also passes.

| Connection | Limit | Full stored route | First geometrically verified plane contact |
| --- | ---: | ---: | ---: |
| C11 supply-plane feed (`U1_DVDD1`) | 5.5 mm | 6.891038 mm | **5.406907 mm** |
| Regulator output-cap ground (`C_LDO_OUT_G`) | 2.5 mm | 2.548627 mm | **2.454096 mm** |

The plane-contact calculation conservatively includes 1.6 mm per traversed via, consistent with the native length checker. No source length limit was increased or removed. C15's formerly excessive ground escape now reaches its plane at **2.681474 mm**, within its unchanged 5.5 mm limit.

## Assembly blocker — approval required

The two GPIO connectors have **1×22 single-row footprints**, but their original selected supplier part **C492428 is 2×11 double-row**. The original alternative C2894972 is also double-row. A matching 1×22 candidate is **C22465881 / XFCN PZ254V-11-22P**.

No selection was changed because the original instructions required preserving JLCPCB parts. Approval is needed to correct the two header selections while preserving the existing footprint, pinout and edge locations.

- [Original C492428 specification](https://jlcpcb.com/partdetail/XFCN-PZ254V_1222P/C492428)
- [Matching 1×22 C22465881 specification](https://jlcpcb.com/partdetail/XFCN-PZ254V_1122P/C22465881)

Do not submit the current BOM for assembly. No PCB or assembly order has been made. Routing verification does not replace manufacturer DFM, signal/power integrity review or hardware validation.

## Publication — 2026-09-04

Published the complete-board source as `@tsci/abse.rp2350-mcu-board@0.0.7` to the [existing project](https://tscircuit.com/abse/rp2350-mcu-board). Release ID: `00d6da08-17fe-47c7-9a70-5a0b303d3a87`.

The 21 published files contain the source, imports, pinned dependency manifest/lockfile, configuration, a public README documenting the remaining issues, and the verified generated PCB JSON/PNG/SVG. Old experiments, local caches, check images and assembly export files were excluded. All 21 remote files were downloaded for SHA-256 comparison and matched the staged upload exactly. The CLI timed out after its archive was accepted, then its automatic file-by-file retry encountered duplicate-file errors; direct registry verification confirmed the complete release and avoided creating a duplicate version.

The registry marked this version latest and started its cloud build. Cloud build completion was still pending at publication verification; the local routing results above must not be read as a separate cloud-build result. Only the local package version and documentation changed for publication; verified circuit source and output hashes stayed unchanged.

## Outputs and evidence

- [Six-layer full-board PCB snapshot](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-four-layer-20260904/six-layer-output/pcb.png)
- [Six-layer full-board PCB SVG](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-four-layer-20260904/six-layer-output/pcb.svg)
- [Six-layer circuit JSON](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-four-layer-20260904/six-layer-output/circuit.json)
- [Review-only Gerbers](/Users/abdolsalamallawlabi/rp2350-mcu-board/dist/rp2350-mcu-board-review-gerbers.zip)
- [Final source/constraint audit](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-layout-20260904/final-audit.json)
- [Physical connectivity report](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-layout-20260904/final-connectivity.json)
- [Plane-contact report](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-layout-20260904/final-plane-contact.json)
- [Published checks, including warnings](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-layout-20260904/final-published-checks.json)
- [Gerber short-check log](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-layout-20260904/final-shorts.log)
- [Drill-clearance report](/Users/abdolsalamallawlabi/Documents/Codex/2026-08-27/work-on-the-complete-rp2350-mcu-2/board-layout-20260904/final-drill.json)

Physical connectivity was checked at 100 pixels/mm. Eleven connectivity-checker controls passed, including deliberately shorted, disconnected, undersized and missing-barrel cases. Geometry checks remain finite-resolution checks rather than guarantees of fabricated hardware behavior.

## Pre-publication verification hashes (SHA-256)

The package.json hash below records the locally verified 0.0.6 manifest before the publication version bump to 0.0.7. Circuit source, lockfile and generated-output hashes remain unchanged.

```text
index.circuit.tsx
c02de45c6cd195597465acf0e9837baa999ed2d8f4d87f2dfdf559c44b5b299f
RP2350A_Essential_KiCad_Reference.circuit.tsx
22e14752a8790370d2f49037d58c3407465422f512a1d4adbc66d93b5ae6179b
package.json
34a7050be2ff96b051a436b4ea0351bae6f020ec2e55a055f507d26dee9b910d
bun.lock
bf24cf170e31121a397a580758943ace45a78ab7df83fde6bb96e6a8da672183
dist/index/circuit.json
47757a2a9607102472ad0f5c92f320dc6643079eb627ebc8193722ad277f2255
dist/index/pcb.png
729b07430347052683c12bb97478b3fdfd7c56b7b4075cf0f669f93ea4f8ae29
```