abse/gameboy-advance

checks/seed-check.ts

PCB

Schematic

import * as checks from '@tscircuit/checks'
const c=await Bun.file('../planning.json').json();const traces=new Map(c.filter((e:any)=>e.type==='source_trace').map((e:any)=>[e.source_trace_id,e]));const nets=new Map(c.filter((e:any)=>e.type==='source_net').map((e:any)=>[e.subcircuit_connectivity_map_key,e.source_net_id]));const seen=new Set(c.filter((e:any)=>e.type==='pcb_via').map((e:any)=>`${e.x.toFixed(6)},${e.y.toFixed(6)}`));for(const t of c.filter((e:any)=>e.type==='pcb_trace'))for(const q of t.route){if(q.route_type!=='via')continue;const k=`${q.x.toFixed(6)},${q.y.toFixed(6)}`;if(seen.has(k))continue;seen.add(k);c.push({type:'pcb_via',pcb_via_id:'seed_via_'+seen.size,x:q.x,y:q.y,outer_diameter:.45,hole_diameter:.15,layers:['top','inner1','inner2','bottom'],from_layer:'top',to_layer:'bottom',source_net_id:nets.get((traces.get(t.source_trace_id) as any).subcircuit_connectivity_map_key),subcircuit_id:'subcircuit_source_group_0'})}
const result:any={};for(const n of ['checkEachPcbTraceNonOverlapping','checkPadTraceClearance','checkViaPadClearance','checkViaTraceClearance','checkDifferentNetViaSpacing','checkHoleTraceClearance']){result[n]=await(checks as any)[n](c);console.log(n,result[n].length)}await Bun.write('../seed-checks.json',JSON.stringify(result,null,2));