MustafaMulla29/rp2040-bldc-motor-controller-new
A tscircuit package created by MustafaMulla29.
- Version
- 0.3.101
- License
- unset
- Stars
- 0
manufacturing/replacement-qualification.json
{
"status": "APPLIED_TO_MAIN_FACTORY_PROCESS_REVIEW_PENDING",
"checkedAt": "2026-10-23T11:28:18.417660+00:00",
"pcbSha256": "8bfb53352924f8501809f89970724e3105159d94da5d94692854387dc11cfea3",
"replacements": [
{
"references": [
"Q1",
"Q2"
],
"from": "SI4427BDY-T1-E3 / C145008",
"to": "SI7111EDN-T1-GE3 / C5690133",
"packageChange": "SO-8 to PowerPAK 1212-8; new native footprint, CAD and local routing",
"pinout": "S=1/2/3, G=4, D=5/6/7/8 and exposed pad. EP shares port 5; supplier labels it 9.",
"ratings": {
"vds_V": 30,
"vgsAbsMax_V": 12,
"rdsMaxAt2_5V_25C_ohm": 0.016,
"previousRdsMaxAt2_5V_25C_ohm": 0.0195,
"rdsMaxAt4_5V_25C_ohm": 0.00855,
"maxQgAt4_5V_nC": 85,
"previousMaxQgAt4_5V_nC": 70
},
"dcGateCheck": 2.9025253637202106,
"gateCheckScope": "4.5 V at common sources, 0.5 V sink, divider tolerances and opposing 10 uA leakage from each PMOS. This is not a startup transient model.",
"lossExample": "At 2 A and 25 C, two fully enhanced devices at the 2.5 V RDS limit dissipate 0.128 W total, versus 0.156 W previously. Hot resistance, startup SOA and PCB temperature are not qualified by this calculation.",
"sources": [
"https://www.vishay.com/docs/67807/si7111edn.pdf",
"https://jlcpcb.com/partdetail/SI7111EDN-T1-GE3/C5690133"
],
"remaining": "Factory stencil/placement approval; bench startup, turn-off, voltage-drop and temperature verification."
},
{
"references": [
"U12"
],
"from": "LM74700QDBVRQ1 / C2941042",
"to": "LM74700QDBVTQ1 / C2653623",
"qualification": "Same LM74700-Q1 silicon, DBV six-pin package and electrical ratings. Reel quantity changes from 3000 to 250. Existing lands retained; new supplier numbered-pad datum used for CPL.",
"sources": [
"https://www.ti.com/lit/ds/symlink/lm74700-q1.pdf",
"https://jlcpcb.com/partdetail/LM74700QDBVTQ1/C2653623"
]
},
{
"references": [
"Q7"
],
"from": "DMT6007LFG-7 / C2802568",
"to": "DMT6009LFG-7 / C439728",
"offlineEvidence": {
"status": "OFFLINE_REPLACEMENT_CHECK_PASS",
"pcbSha256": "8bfb53352924f8501809f89970724e3105159d94da5d94692854387dc11cfea3",
"checkedAt": "2026-10-23T11:26:29.420576+00:00",
"replacement": {
"mpn": "DMT6009LFG-7",
"jlcpcb": "C439728"
},
"selection": {
"C6540300": "Rejected: exact library import unavailable",
"C6021921": "Rejected: exact library import unavailable despite stock",
"C3279409": "Rejected: only one in stock, need two"
},
"stock": {
"part": "C439728",
"mpn": "DMT6009LFG-7",
"designators": [
"Q7"
],
"perBoard": 1,
"requiredForTwoAssembled": 2,
"url": "https://jlcpcb.com/partdetail/DMT6009LFG-7/C439728",
"checkedAt": "2026-10-23T11:21:15.504956+00:00",
"pageSha256": "585562f2de0ebffde5ffc3481c7bf2199ab7e957c997522fc7128797f951e815",
"catalogMpn": "DMT6009LFG-7",
"schemaAvailability": "https://schema.org/InStock",
"assemblyMode": "smtWeld",
"fixtureFlag": false,
"needAuditFlag": false,
"componentLibraryType": "expand",
"componentSpecificationEn": "PowerDI3333-8",
"overseasStockCount": 22,
"leastPatchNumber": 0,
"lossNumber": 0,
"preMinPurchaseNum": 9,
"status": "CATALOG_STOCK_COVERS_POPULATION_ONLY"
},
"supplierImport": {
"status": "PASS",
"sourceSha256": "cddd4d21de90e9e7af1599abb56ac0e03fbc7816353f38099fd594bc41afdbca",
"file": "catalog-imports/imports/DMT6009LFG_7.tsx",
"publicPreview": "https://jlcpcb.com/user-center/lcsvg/svg.html?code=C439728&detail=1",
"previewVisuallyVerified": true,
"screenshotSha256": "c8a11dad9127021db609d158d0e3f804dfc58920aad7cb90b1b78e257b336e3a",
"identicalCopperLandCount": 5
},
"pinout": {
"source": [
1,
2,
3
],
"gate": 4,
"drain": "5 (continuous copper represents package terminals 5-8)"
},
"assemblyDatum": {
"designator": "Q7",
"mpn": "DMT6009LFG-7",
"supplier": "C439728",
"package": "PowerDI3333-8 (5 numbered pads)",
"layer": "top",
"rotation": 90,
"x": -14.7,
"y": 19.6,
"mount": "SMT",
"matchedNumberedPads": 5,
"maxPadResidualMm": 5.0242958677880805e-15,
"alternativeRmsMm": 1.8096511405744047,
"authoredCenter": {
"x": -14.638470850000001,
"y": 19.6
},
"originMethod": "PowerDI3333 numbered catalog-pad datum; polygon drain and stencil produce an asymmetric component-bounds center. Factory placement preview required.",
"reference": "Exact C439728 supplier import on 2026-10-23; pinout independently checked against Diodes DS37741 Rev 2-2 pp1,7"
},
"geometryComparison": {
"status": "PASS",
"identicalPcbGeometryRecords": 4823,
"electricalConnectivityUnchanged": true,
"sourceDifferences": [
[
"Q7",
"source_component"
]
],
"metadataDifference": "source filesystem hash changes with import identity",
"pcbSha256": "58a29ab261833cebdd61f110b103187994382911fee18d30585ad9962e60c728",
"baseline": "before-q7-change/dist/index/circuit.json"
},
"ratings": {
"VDS_V": 60,
"VGS_absMax_V": 16,
"priorVGS_absMax_V": 20,
"controllerRecommendedMinimumGateRating_V": 15,
"rdsMaxAt10V25C_ohm": 0.01,
"rdsMaxAt4_5V25C_ohm": 0.0117,
"priorRdsMaxAt4_5V25C_ohm": 0.0085,
"QgTypicalAt10V_nC": 33.5,
"VthMax_V": 2,
"bodyDiodeContinuous_A": 2.4,
"bodyDiodeRatingScope": "Manufacturer test-board thermal conditions; not an inrush qualification for this PCB."
},
"dcExamples": [
{
"current_A": 0.8,
"fullyEnhancedDropAt4_5VGate25C_V": 0.00936,
"fullyEnhancedLossAt4_5VGate25C_W": 0.007488000000000002
},
{
"current_A": 0.9,
"fullyEnhancedDropAt4_5VGate25C_V": 0.010530000000000001,
"fullyEnhancedLossAt4_5VGate25C_W": 0.009477000000000001
},
{
"current_A": 1.23,
"fullyEnhancedDropAt4_5VGate25C_V": 0.014391000000000001,
"fullyEnhancedLossAt4_5VGate25C_W": 0.01770093
},
{
"current_A": 2,
"fullyEnhancedDropAt4_5VGate25C_V": 0.0234,
"fullyEnhancedLossAt4_5VGate25C_W": 0.0468
}
],
"dcScope": "Fully enhanced RDS calculations at 25 C only. LM74700 regulates approximately 20 mV, so actual drop is not always I*RDS. Hot resistance, startup, dynamic reverse blocking and PCB temperature require hardware tests. 2 A is an input-budget comparison, not a motor phase-current rating.",
"controllerCompatibility": "The +/-16 V gate limit exceeds TI minimum 15 V recommendation. The 60 V drain rating is retained; 2 V maximum threshold meets TI guidance. Lower typical gate charge does not establish measured turnoff performance.",
"chargePump": {
"C145Nominal_F": 1e-06,
"minimumNominalFromTiGuideline_F": 1e-07,
"note": "Effective capacitance under bias and startup must be checked on hardware."
},
"limits": [
"No factory approval or physical tests obtained",
"Does not resolve existing 5 V operating-margin limitation",
"Existing U1/U5/U7 stencil-process findings unchanged",
"Stock is a timestamped public listing, not reserved inventory"
],
"sources": [
{
"url": "https://www.diodes.com/datasheet/download/DMT6009LFG.pdf",
"sha256": "aad2cccd2af790a794c24f7dd64a7c452307bb2244898df41873d8b443b82c80",
"pages": [
1,
2,
3,
7
]
},
{
"url": "https://www.ti.com/lit/ds/symlink/lm74700-q1.pdf",
"sha256": "e16b3a8c0023201fafa5825436f5f2dd6f885b92b84e65602b3f50d741c58b6f",
"pages": [
4,
5,
17
]
}
],
"appliedToMainAt": "2026-10-23T11:35:27.440538+00:00",
"mainVerification": {
"status": "PASS",
"checkedAt": "2026-10-23T11:35:27.440538+00:00",
"mainPcbSha256": "8bfb53352924f8501809f89970724e3105159d94da5d94692854387dc11cfea3",
"trialPcbSha256": "58a29ab261833cebdd61f110b103187994382911fee18d30585ad9962e60c728",
"identicalNonMetadataRecords": 8299,
"identicalPcbGeometryRecords": 4823,
"comparisonScope": "Every record including warnings, except source_project_metadata (project filesystem hash); circuit/import/firmware files also match byte-for-byte.",
"partsApplied": {
"Q1": {
"mpn": "SI7111EDN-T1-GE3",
"jlcpcb": "C5690133"
},
"Q2": {
"mpn": "SI7111EDN-T1-GE3",
"jlcpcb": "C5690133"
},
"U12": {
"mpn": "LM74700QDBVTQ1",
"jlcpcb": "C2653623"
},
"Q7": {
"mpn": "DMT6009LFG-7",
"jlcpcb": "C439728"
},
"D4": {
"mpn": "SMBJ22A",
"jlcpcb": "C3720133"
},
"C71": {
"mpn": "C3225X7R1H106KT000E",
"jlcpcb": "C432929"
}
},
"schematicAdvisories": 13,
"electricalConnectivityUnchangedFromTrial": true
}
},
"qualification": "Same PowerDI3333-8 pinout and exactly matching supplier copper lands; 60 V VDS, +/-16 V gate, 10 mOhm at 10 V and 11.7 mOhm at 4.5 V gate. Gate rating exceeds TI's 15 V minimum recommendation. See q7-replacement-review.json for scoped calculations. Existing lands and native stencil retained.",
"sources": [
"https://www.diodes.com/datasheet/download/DMT6009LFG.pdf",
"https://www.diodes.com/assets/Datasheets/DMT6007LFG.pdf",
"https://jlcpcb.com/partdetail/DMT6009LFG-7/C439728"
],
"remaining": "Exact C439728 supplier import and public footprint preview pass; exported CPL matches its numbered-pad datum. Order-specific factory approval and physical startup/reverse-blocking/temperature tests remain."
},
{
"references": [
"D4"
],
"from": "SMBJ22A / C224015",
"to": "Bourns SMBJ22A / C3720133",
"qualification": "22 V unidirectional, 600 W (10/1000 us), 24.4-26.9 V breakdown and 35.5 V maximum clamp at 16.9 A. Existing SMB lands meet the Bourns drawing; polarity preserved.",
"sources": [
"https://www.bourns.com/docs/product-datasheets/smbj.pdf",
"https://jlcpcb.com/partdetail/SMBJ22A/C3720133"
],
"remaining": "Transient/regen and factory orientation qualification remain required; TVS is not a continuous braking load."
},
{
"references": [
"C71"
],
"from": "C3225X7R1H106K250AC / C2181731",
"to": "C3225X7R1H106KT000E / C432929",
"qualification": "TDK ordering-code replacement for the same 10 uF +/-10%, 50 V, X7R, 1210 capacitor. Same land positions; no placement/routing change.",
"sources": [
"https://www.mouser.com/PCN/TDK_TDK_C1_LEAD_TIME.pdf",
"https://jlcpcb.com/partdetail/C3225X7R1H106KT000E/C432929"
]
}
],
"designChecks": {
"status": "PASS",
"identicalElectricalConnectivity": true,
"netGroups": 103,
"changedSourceComponents": [
"Q1",
"Q2",
"U12",
"Q7",
"D4",
"C71"
],
"newNativeWarnings": {
"schematic_sheet_styling_warning": 1,
"source_refdes_convention_warning": 5,
"source_no_power_pin_defined_warning": 5,
"source_no_ground_pin_defined_warning": 3,
"pcb_trace_style_warning": 49
},
"baselineNativeWarnings": {
"schematic_sheet_styling_warning": 1,
"source_refdes_convention_warning": 5,
"source_no_power_pin_defined_warning": 5,
"source_no_ground_pin_defined_warning": 3,
"pcb_trace_style_warning": 49
},
"pcbSha256": "8bfb53352924f8501809f89970724e3105159d94da5d94692854387dc11cfea3",
"q7RevisionEvidence": {
"status": "PASS",
"identicalPcbGeometryRecords": 4823,
"electricalConnectivityUnchanged": true,
"sourceDifferences": [
[
"Q7",
"source_component"
]
],
"metadataDifference": "source filesystem hash changes with import identity",
"pcbSha256": "58a29ab261833cebdd61f110b103187994382911fee18d30585ad9962e60c728",
"baseline": "before-q7-change/dist/index/circuit.json"
}
},
"schematicComparison": {
"baselineCount": 13,
"trialCount": 13,
"unchanged": true,
"new": [],
"removed": [],
"baseline": "/Users/mustafamulla/Documents/Codex/2026-09-29/i-w/work/order-package-20261023/schematic-placement.log",
"trial": "/Users/mustafamulla/Documents/Codex/2026-09-29/i-w/work/stocked-replacements-20261023/q7-schematic-placement.log"
},
"constraints": [
"No generated circuit/Gerber geometry edited, no checker suppression or threshold relaxation, no dependency patches added.",
"Local digital checks do not qualify physical PD/motor/USB operation, thermals or factory processes.",
"The existing 5 V motor limitation and uncommissioned motor profile remain.",
"All 61 public stock lines cover two-board population only, before factory minimums/attrition; no reservation made."
],
"stencilProcessFollowup": {
"status": "PROCESS_REVIEW_FINDINGS_FACTORY_APPROVAL_NOT_OBTAINED",
"report": "manufacturing/stencil-process-screen.json",
"findings": [
{
"component": "U1",
"apertures": 24,
"dimensionsMm": [
[
0.19600672,
0.48999902
]
],
"minimumAreaRatio": 0.5834953577094639,
"minimumAspectRatio": 1.56805376,
"nativeGerberVerified": true
},
{
"component": "U5",
"apertures": 56,
"dimensionsMm": [
[
0.13999972,
0.5950076999999999
]
],
"minimumAreaRatio": 0.45333371680979223,
"minimumAspectRatio": 1.11999776,
"nativeGerberVerified": true
},
{
"component": "U7",
"apertures": 36,
"dimensionsMm": [
[
0.13999972,
0.48999902
]
],
"minimumAreaRatio": 0.43555468444444445,
"minimumAspectRatio": 1.11999776,
"nativeGerberVerified": true
}
]
},
"appliedToMainAt": "2026-10-23T11:35:27.440538+00:00",
"userApproval": "User instructed: apply the changes to main",
"mainVerification": {
"status": "PASS",
"checkedAt": "2026-10-23T11:35:27.440538+00:00",
"mainPcbSha256": "8bfb53352924f8501809f89970724e3105159d94da5d94692854387dc11cfea3",
"trialPcbSha256": "58a29ab261833cebdd61f110b103187994382911fee18d30585ad9962e60c728",
"identicalNonMetadataRecords": 8299,
"identicalPcbGeometryRecords": 4823,
"comparisonScope": "Every record including warnings, except source_project_metadata (project filesystem hash); circuit/import/firmware files also match byte-for-byte.",
"partsApplied": {
"Q1": {
"mpn": "SI7111EDN-T1-GE3",
"jlcpcb": "C5690133"
},
"Q2": {
"mpn": "SI7111EDN-T1-GE3",
"jlcpcb": "C5690133"
},
"U12": {
"mpn": "LM74700QDBVTQ1",
"jlcpcb": "C2653623"
},
"Q7": {
"mpn": "DMT6009LFG-7",
"jlcpcb": "C439728"
},
"D4": {
"mpn": "SMBJ22A",
"jlcpcb": "C3720133"
},
"C71": {
"mpn": "C3225X7R1H106KT000E",
"jlcpcb": "C432929"
}
},
"schematicAdvisories": 13,
"electricalConnectivityUnchangedFromTrial": true
},
"cadRegistrationApplicability": {
"checkedAt": "2026-10-23T12:07:53.359974+00:00",
"previousPcbSha256": "8bfb53352924f8501809f89970724e3105159d94da5d94692854387dc11cfea3",
"appliesToPcbSha256": "1ca490a5a0406c9eb23e07d8cc6e17e092046133d1b0acf5909c8dcf034e8fbb",
"pcbSchematicConnectivityUnchanged": true,
"bomAndCplByteIdentical": true,
"nativeManufacturingFilesCompared": 14,
"manufacturingComparison": "Identical apart from native exporter creation timestamps; exports were not edited.",
"scope": "Only J1/J19 CAD origins changed; cable CAD follows the corrected front face. Prior stock check times and factory/physical limitations are unchanged."
}
}
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