AnasSarkiz/muse-voice-remote

manufacturing/FABRICATION-NOTES.md

# Muse Voice Remote — prototype manufacturing profile

Use the checked Gerbers, separate PTH/NPTH drill files, BOM and CPL from the
same versioned manufacturing ZIP. Upload the included `MuseVoiceRemote-Gerbers-JLCPCB-v1.3.1.zip` for PCB fabrication and the separate `BOM-JLCPCB.csv` / `CPL-JLCPCB.csv` for TOP assembly. Apply the stackup, impedance and filled-via requirements below to the fabrication quote. The factory reference map connects its
standard designators to the descriptive names in the tscircuit source.

## PCB and assembly

- 66 × 48 mm rectangular PCB, nominal 1.0 mm thickness, four copper layers.
- All populated components on TOP; no bottom-side assembly.
- ENIG finish, black solder mask and white top silkscreen. Keep the fine-pitch
  mask openings and the original supplier copper land patterns.
- Minimum track/clearance 0.15/0.15 mm, copper-to-edge 0.5 mm,
  via drill 0.30 mm, via pad 0.45 mm minimum, annular ring 0.075 mm minimum, hole-to-foreign-copper 0.15 mm.
- Four Ø1.8 mm mounting holes. The factory derivative enlarges the two imported Ø0.40 mm microphone acoustic
  NPTH ports to Ø0.50 mm for JLCPCB’s published drilling minimum. Keep these ports open; original supplier libraries remain intact.
- The USB-C shell uses plated slots; retain the supplied slot geometry.
- All parts import original JLCPCB/EasyEDA geometry and retain their supplier
  CAD references. No alternate electronic land patterns are substituted.

## Stackup and impedance

Specify **JLC04101H-3313**, the JLCPCB 1.0 mm four-layer stackup recorded in
`docs/research/jlc-1mm-stackup-selection.json`:

| Layer | Material / nominal thickness |
| --- | --- |
| L1 | Top copper, 0.035 mm |
| Dielectric | 3313 RC57%, 0.0994 mm, Er 4.1 |
| L2 | Ground copper, 0.0152 mm |
| Core | FR-4, 0.7 mm, Er 4.53 |
| L3 | Copper, 0.0152 mm |
| Dielectric | 3313 RC57%, 0.0994 mm, Er 4.1 |
| L4 | Bottom copper, 0.035 mm |

The copper/dielectric sum is 0.9992 mm before mask. The board is specified as
1.0 mm nominal with the fabricator's published thickness tolerance.

L2 is the continuous ground reference. L3 carries the 3.3 V supply with cleared signal paths; additional checked supply bridges reconnect its islands. The bridge widths and connectivity checks are retained in `docs/supply-plane-bridges.json`. The native filled copper is also retained
in circuit.json as BRep outlines with clearance holes. Specify controlled
impedance **50 Ω RF** and **90 Ω USB differential**, ±10%, for this stackup.
The USB main paths are paired on top; a short bridge joins duplicate receptacle
D− contacts on the back. Nominal geometry estimates and actual route metrics
are recorded separately. Analytical screening in `docs/research/impedance-screening.json` gives approximately 49.2 Ω for the 0.18 mm RF line and 96.0 Ω differential for the 0.15/0.15 mm USB pair. The simple model omits mask, etch shape, adjacent copper and launches; no measured impedance coupon is claimed. Obtain the
fabricator's normal impedance confirmation/coupon as part of this process.

## Thermal holes and stencil

Use resin-filled, copper-capped via-in-pad processing for the exposed-pad thermal
holes: the nine original ESP32 ground-pad holes and the added charger,
buck-boost and amplifier thermal vias. These are ground-connected through holes;
they are not component lead holes. Keep connector slots and microphone NPTH
ports open. Ordinary routing vias can use the fabricator's standard tenting.

The factory copy has segmented thermal-pad paste artwork at 60% area coverage for MCU, charger and amplifier; the TPS63001 custom ground land uses 80% per TI DRC0010J.
The imported electrical copper, plated-hole geometry, pad positions and supplier
CAD references remain unchanged. Only the two microphone acoustic NPTH diameters
are enlarged in the factory copy; their centres stay fixed. The verification report
records both original and factory diameters. Use a 0.10 mm laser-cut top stencil suitable
for the 0.4 mm QFN pitch and 0402 parts. The reference map records the aperture
counts and dimensions.

## Bring-up and external assembly

The manufacturing BOM covers the PCB components. Fit the exact external
ER-TFT028A2-4 no-touch panel, a protected 4.2 V 1S pack with adequate discharge
current and matched 10 kΩ temperature sensing, the external speaker, motor and
50 Ω antenna/harness separately. The retained mechanical PDF supplies allocation
dimensions; the revised placement and external harness need physical assembly
verification. The JST PA header uses the standard PAP-03V-S mating housing;
its mated height is 6.2 mm according to the manufacturer drawing.

Power the first board from a current-limited supply, verify every rail and
hardware microphone privacy, then program the ESP32-S3R8 through USB with the
power switch ON. Keep VDD_SPI at 3.3 V; never select/program the 1.8 V memory
configuration. The external 0 Ω supply link uses the manufacturer's externally
driven VDD_SPI option. Firmware must implement the USB100/configured-USB500/
suspend policy, safe backlight power sequencing, battery limits and speaker
volume limits before full-load testing. The 46.4 kΩ amplifier control series resistor prevents boosted GPIO voltage exceeding SYS-referenced SD_MODE limits, selects the left I2S word when enabled, and retains hardware default shutdown. GAIN is grounded (12 dB); start with mono data in the left word and sample peaks capped at −9 dBFS, then verify speaker power. Test RF, oscillator, audio, thermal,
charging and enclosure behavior on the prototype. MUSE runs on the connected
service; its integration remains unverified.

The minimum routing-via drill is **0.30 mm** and the minimum copper pad is
**0.45 mm** on every copper layer, including the added thermal vias. The
0.075 mm nominal radial annulus follows JLCPCB’s preferred 0.15 mm pad-minus-hole
diameter rule; see `docs/research/via-030-capability.json`. The native via-size
audits check all routing vias and the nine original MCU thermal holes.