0hmX/simplified-am62l-computer

This code defines components and scripts for physically representing and routing high-speed DDR memory signals, power lines, and ground planes on an 8-layer PCB with detailed pin assignments, copper pours, and precise via and trace layouts based on TI EVM reference data.

Version
1.0.16
License
unset
Stars
0

repros/am62l-lpddr4-breakout-repro/RESULTS.md

# Routing results

## Baseline and source review

- Review date: 2026-08-15 (Asia/Kolkata)
- Fetched Core ref: `origin/main`
- Core commit: `5ef2b914d1065733b06b3e1171eac3f66d0a319e`
- Core package / npm `gitHead`: `0.0.1685` / the same commit
- Pinned `tscircuit`: `0.0.2332`
- Pinned TI component: `@tsci/tscircuit.ti@1.0.100`
- Pinned RAM component: `@tsci/0hmX.mt53e1g16d1zw-footprint@1.0.2`

The required Core breakout implementation and architectural tests were reviewed
from the fetched commit before this fixture was written. The public tscircuit
pages for the reference project and the RAM package were also inspected. The
existing `simplified-am62l-computer` checkout was treated as read-only.

## Attempt 1 — requested starting geometry

- Board: 45 mm × 25 mm, 8 layers
- SoC: (-10, 0), 180°
- RAM: (10.116917, -0.050917), 90°
- SoC padding: top 5 mm, right 2 mm, bottom 5 mm, left 1 mm
- RAM padding: top 5 mm, right 1 mm, bottom 5 mm, left 2 mm
- Fanout layers: top, inner1–inner6, bottom
- Bus directions: requested right-facing SoC and left-facing RAM arrangement
- Effort: `10x`
- Routing timeout: 10 minutes per phase for the single diagnostic PCB-image
  build

Status: failed before the first autorouting phase started.

Core threw while converting the cross-boundary connections into Simple Route
JSON for the first declared differential pair:

```text
Subcircuit connectivity map key
"AM62L_LPDDR4_BREAKOUT_REPRO_connectivity_net18" matches multiple SRJ
connections for differential pair "DQS0_PAIR"
```

This happened in `getDifferentialPairSrjConnectionNameOrThrow`, called by
`getDifferentialPairsForSimpleRouteJson` and then
`getSimpleRouteJsonFromCircuitJson`. The CLI was run with `--ignore-errors` so
it could preserve Circuit JSON and PCB images; therefore its process exit code
was 0 even though the async autorouting effect failed.

## Adjustments

No adjustments have been made. Per the user instruction, if the initial
automatic-routing attempt fails or times out, the failure will be preserved and
no alternate autorouter or high-level routing iteration will be attempted.

The snapshot command was not run after this failure because it would start a
second routing attempt, contrary to that instruction.

## Verification

- Installed `@tscircuit/core`: `0.0.1685` (no nested older Core)
- Core git / npm `gitHead`:
  `5ef2b914d1065733b06b3e1171eac3f66d0a319e`
- Source traces: 33 exactly
- Source breakout groups: 2 exactly
- Breakout PCB groups: 2 exactly
- Automatic breakout points: 66 exactly (33 SoC + 33 RAM)
- Automatic PCB traces: 0
- Automatic PCB vias: 0
- Autorouting phase inputs captured: 0
- Breakout/fanout stages run: no
- Final global stage run: no
- `pcb_autorouting_error`: 0 records
- `pcb_trace_error`: 0 records
- `pcb_pad_trace_clearance_error`: 0 records
- `pcb_via_clearance_error`: 0 records
- Forbidden source-level routing constructs: none
- Wall-clock build/routing attempt: 13.992406458 seconds

The four Circuit JSON error tables are empty because the exception occurred
while preparing the first routing input, before Core emitted an autorouting
error record or any copper.

## Final artifacts

- Circuit JSON: `dist/index/circuit.json`
- PCB SVG: `dist/index/pcb.svg`
- PCB PNG: `dist/index/pcb.png`
- Machine-readable verification: `dist/verification-report.json`
- Timing record: `dist/routing-timing.json`

The generated PCB image contains the two placed BGA footprints and no routed
copper, consistent with the pre-phase failure. Generated artifacts are ignored
by Git but remain in the local repository working directory and can be
regenerated with `bun run build`.