0hmX/simplified-am62l-computer

ddr-only.circuit.tsx

PCB

Schematic

import { AM62L32 } from "@tsci/tscircuit.ti"
import {
  MT53E1G16D1ZW,
  ballMap,
} from "@tsci/0hmX.mt53e1g16d1zw-footprint"
import { Fragment } from "react"
import {
  DDR_ONLY_CONNECTIONS,
  DDR_ONLY_SOC_PINS,
} from "./ddr-only-connections"
import { createFixedTargetBgaFanoutAutorouter } from "./routing/fixed-target-bga-fanout-autorouter"
import { TI_AM62L_EVM_MEMORY_OFFSET } from "./routing/ti-am62l-evm-ddr-routes"

const usedSocPins = new Set<number>(DDR_ONLY_SOC_PINS)
const socNoConnect = Array.from({ length: 373 }, (_, index) => index + 1)
  .filter((pin) => !usedSocPins.has(pin))
  .map((pin) => `pin${pin}`)

const usedMemorySignals = new Set<string>(
  DDR_ONLY_CONNECTIONS.map(([, memorySignal]) => memorySignal),
)
const memoryNoConnect = ballMap
  .map(({ signal }, index) => ({ signal, selector: `pin${index + 1}` }))
  .filter(({ signal }) => !usedMemorySignals.has(signal))
  .map(({ selector }) => selector)

const U1_POSITION = { x: -10, y: 0 }
const ddrFanoutLayers = ["inner2", "inner5", "bottom"] as const
const fixedTargetBgaBreakoutAutorouter = {
  local: true,
  groupMode: "subcircuit" as const,
  algorithmFn: createFixedTargetBgaFanoutAutorouter,
}

const ddrByte0Connections = [
  ...Array.from({ length: 8 }, (_, bit) => `DDR0_DQ${bit}`),
  "DDR0_DM0",
  "DDR0_DQS0",
  "DDR0_DQS0_n",
]
const ddrByte1Connections = [
  ...Array.from({ length: 8 }, (_, bit) => `DDR0_DQ${bit + 8}`),
  "DDR0_DM1",
  "DDR0_DQS1",
  "DDR0_DQS1_n",
]
const ddrCommandConnections = [
  ...Array.from({ length: 6 }, (_, bit) => `DDR0_A${bit}`),
  "DDR0_CS0_n",
  "DDR0_CKE0",
  "DDR0_CK0",
  "DDR0_CK0_n",
  "DDR_LINK_RESET0_n",
]

export default () => (
  <board
    width="45mm"
    height="25mm"
    layers={8}
    defaultTraceWidth="0.08128mm"
    minTraceWidth="0.08128mm"
    minTraceToPadEdgeClearance="0.05mm"
    minViaEdgeToPadEdgeClearance="0.08128mm"
    minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
    minViaHoleDiameter="0.2032mm"
    minViaPadDiameter="0.4572mm"
    pcbStyle={{ viaHoleDiameter: "0.2032mm", viaPadDiameter: "0.4572mm" }}
  >
    <autoroutingphase
      name="fixed-target-bga-ddr"
      phaseIndex={1}
      autorouter="default"
    />

    <bus
      name="DDR_BYTE0"
      connections={ddrByte0Connections}
      routingPhaseIndex={1}
      pcbTraceWidth="0.08128mm"
      pcbAllowedLayers={["inner2"]}
      preferredLayer="inner2"
    />
    <bus
      name="DDR_BYTE1"
      connections={ddrByte1Connections}
      routingPhaseIndex={1}
      pcbTraceWidth="0.08128mm"
      pcbAllowedLayers={["bottom"]}
      preferredLayer="bottom"
    />
    <bus
      name="DDR_COMMAND"
      connections={ddrCommandConnections}
      routingPhaseIndex={1}
      pcbTraceWidth="0.09398mm"
      pcbAllowedLayers={["inner5"]}
      preferredLayer="inner5"
    />

    <breakout
      name="SOC_BREAKOUT"
      pcbX={U1_POSITION.x}
      pcbY={U1_POSITION.y}
      autorouter={fixedTargetBgaBreakoutAutorouter}
      fanoutBoundaryPadding={{
        top: "5mm",
        right: "2mm",
        bottom: "5mm",
        left: "1mm",
      }}
      fanoutRoutingLayers={[...ddrFanoutLayers]}
      busFanoutDirections={{
        DDR_BYTE1: "top_right",
        DDR_COMMAND: "center_right",
        DDR_BYTE0: "bottom_right",
      }}
    >
      <AM62L32
        name="U1"
        footprintVariant="fccsp_373_anb"
        pcbX={0}
        pcbY={0}
        pcbRotation={180}
        noSchematicRepresentation
        noConnect={socNoConnect as any}
        pinAttributes={{
          pin1: { requiresGround: true },
          pin142: { requiresPower: true },
        } as any}
      />
    </breakout>
    <breakout
      name="RAM_BREAKOUT"
      pcbX={U1_POSITION.x + TI_AM62L_EVM_MEMORY_OFFSET.x}
      pcbY={U1_POSITION.y + TI_AM62L_EVM_MEMORY_OFFSET.y}
      autorouter={fixedTargetBgaBreakoutAutorouter}
      fanoutBoundaryPadding={{
        top: "5mm",
        right: "1mm",
        bottom: "5mm",
        left: "2mm",
      }}
      fanoutRoutingLayers={[...ddrFanoutLayers]}
      busFanoutDirections={{
        DDR_BYTE1: "top_left",
        DDR_COMMAND: "center_left",
        DDR_BYTE0: "bottom_left",
      }}
    >
      <MT53E1G16D1ZW
        name="U2"
        pcbX={0}
        pcbY={0}
        pcbRotation={90}
        noSchematicRepresentation
        noConnect={memoryNoConnect as any}
      />
    </breakout>

    {DDR_ONLY_CONNECTIONS.map(([socSignal, memorySignal]) => (
      <Fragment key={socSignal}>
        <trace
          name={
            socSignal === "DDR0_RESET0_n"
              ? "DDR_LINK_RESET0_n"
              : socSignal
          }
          from={`U1.${socSignal}`}
          to={`U2.${memorySignal}`}
          routingPhaseIndex={1}
        />
      </Fragment>
    ))}

    <silkscreentext
      text="AM62L + 2GB LPDDR4 / 33 DIRECT SIGNALS ONLY"
      pcbX={0}
      pcbY={-10.5}
      fontSize={0.65}
    />
  </board>
)