0hmX/mt53e1g16d1zw-footprint

This code defines the physical pin layout and 200-ball footprint of the Micron MT53E1G16D1ZW DDR4 SDRAM chip, including pad positions, signal assignments, and qualification of pin attributes for PCB integration.

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1.0.2
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docs/pinout.md

# MT53E1G16D1ZW ball map

This table transcribes the x16, single-channel assignment in Figure 8 of the
[Micron z42n Rev. D datasheet](https://docs.rs-online.com/ad5d/A700000015750558.pdf),
page 30. It is a top view with the balls facing down. Figure 14 on page 39 defines the ZW package:
200-ball TFBGA, 10.00 x 14.50 x 1.05 mm, 0.80 mm X pitch, 0.65 mm Y pitch,
and 0.40 mm SMD ball pads. Columns 6/7 and rows L/M are absent.

| Row | 1 | 2 | 3 | 4 | 5 | 8 | 9 | 10 | 11 | 12 |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| A | DNU | DNU | VSS | VDD2 | ZQ | NC | VDD2 | VSS | DNU | DNU |
| B | DNU | DQ0 | VDDQ | DQ7 | VDDQ | VDDQ | DQ15 | VDDQ | DQ8 | DNU |
| C | VSS | DQ1 | DMI0 | DQ6 | VSS | VSS | DQ14 | DMI1 | DQ9 | VSS |
| D | VDDQ | VSS | DQS0_t | VSS | VDDQ | VDDQ | VSS | DQS1_t | VSS | VDDQ |
| E | VSS | DQ2 | DQS0_c | DQ5 | VSS | VSS | DQ13 | DQS1_c | DQ10 | VSS |
| F | VDD1 | DQ3 | VDDQ | DQ4 | VDD2 | VDD2 | DQ12 | VDDQ | DQ11 | VDD1 |
| G | VSS | ODT_CA | VSS | VDD1 | VSS | VSS | VDD1 | VSS | NC | VSS |
| H | VDD2 | CA0 | NC | CS | VDD2 | VDD2 | CA2 | CA3 | CA4 | VDD2 |
| J | VSS | CA1 | VSS | CKE | NC | CK_t | CK_c | VSS | CA5 | VSS |
| K | VDD2 | VSS | VDD2 | VSS | NC | NC | VSS | VDD2 | VSS | VDD2 |
| N | VDD2 | VSS | VDD2 | VSS | NC | NC | VSS | VDD2 | VSS | VDD2 |
| P | VSS | NC | VSS | NC | NC | NC | NC | VSS | NC | VSS |
| R | VDD2 | NC | NC | NC | VDD2 | VDD2 | NC | NC | NC | VDD2 |
| T | VSS | NC | VSS | VDD1 | VSS | VSS | VDD1 | VSS | RESET_n | VSS |
| U | VDD1 | NC | VDDQ | NC | VDD2 | VDD2 | NC | VDDQ | NC | VDD1 |
| V | VSS | NC | NC | NC | VSS | VSS | NC | NC | NC | VSS |
| W | VDDQ | VSS | NC | VSS | VDDQ | VDDQ | VSS | NC | VSS | VDDQ |
| Y | VSS | NC | NC | NC | VSS | VSS | NC | NC | NC | VSS |
| AA | DNU | NC | VDDQ | NC | VDDQ | VDDQ | NC | VDDQ | NC | DNU |
| AB | DNU | DNU | VSS | VDD2 | VSS | VSS | VDD2 | VSS | DNU | DNU |

## Pin selectors and attributes

- Every ball has its coordinate as an alias: `.U1 > .B2` selects `DQ0`.
- Unique functional names are aliases: `.U1 > .DQ0` also selects ball B2.
- Repeated rails use coordinate-qualified aliases such as `.U1 > .VDDQ_B3`.
- `VSS`: `requiresGround`.
- `VDD1`: `requiresPower`, `requiresVoltage="1.8V"`, decoupling requested.
- `VDD2`: `requiresPower`, `requiresVoltage="1.1V"`, decoupling requested.
- `VDDQ`: `requiresPower`, decoupling requested. Its voltage is mode-dependent.
- `DNU`: `doNotConnect`; these balls must not be used.
- `NC`: excluded from generated board pinouts and kept distinct from DNU.

The `datasheetUrl` property on the component points to the same document. The
[Micron exact-part page](https://www.micron.com/products/memory/lpddr-components/lpddr4/part-catalog/part-detail/mt53e1g16d1zw-046-wt-c)
and [DigiKey listing](https://www.digikey.com/en/products/detail/micron-technology-inc/MT53E1G16D1ZW-046-WT-C/22041509)
independently identify the exact target as a 16 Gb, x16, 200-ball TFBGA device.
The pin metadata fields follow tscircuit's
[`PinAttributeMap`](https://github.com/tscircuit/props/blob/main/lib/common/pinAttributeMap.ts)
and [`chip` props schema](https://github.com/tscircuit/props/blob/main/lib/components/chip.ts).