tscircuit/ti

ti tscircuit library
Version: 1.0.85
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lib/chips/spice-models/TPSM82823-spice-model.json

{
  "source": "*$\r\n* TPSM82823\r\n*****************************************************************************\r\n* (C) Copyright 2021 Texas Instruments Incorporated. All rights reserved.                                            \r\n*****************************************************************************\r\n** This model is designed as an aid for customers of Texas Instruments.\r\n** TI and its licensors and suppliers make no warranties, either expressed\r\n** or implied, with respect to this model, including the warranties of \r\n** merchantability or fitness for a particular purpose.  The model is\r\n** provided solely on an \"as is\" basis.  The entire risk as to its quality\r\n** and performance is with the customer\r\n*****************************************************************************\r\n*\r\n* This model is subject to change without notice. Texas Instruments\r\n* Incorporated is not responsible for updating this model.\r\n*\r\n*****************************************************************************\r\n*\r\n** Released by: Texas Instruments Inc.\r\n* Part: TPSM82823\r\n* Date: 19APR2021\r\n* Model Type: TRANSIENT\r\n* Simulator: PSPICE \r\n* Simulator Version: 17.4-2019 S016\r\n* EVM Order Number: TPSM82823EVM-080\r\n* EVM Users Guide: SLVUBR5C – AUGUST 2019 – REVISED MARCH 2021\r\n* Datasheet: SLVSEP0D – AUGUST 2019 – REVISED MARCH 2021\r\n* Topologies Supported: Buck\r\n*\r\n* Model Version: Final 1.00\r\n*\r\n*****************************************************************************\r\n*\r\n* Updates:\r\n*\r\n* Final 1.00\r\n* Release to Web.\r\n*\r\n*****************************************************************************************\r\n*\t\r\n* Model Usage Notes:\r\n* A. Features have been modelled\r\n*   1. PWM and PSM Operation\r\n*   2. Low Dropout Operation (100% Duty Cycle)\r\n*   3. Soft Start-up\r\n*   4. Switch Current Limit and Hiccup Short Circuit Protection\r\n*   5. Undervoltage Lockout\r\n*   6. Output Discharge\r\n*   7. Power good output       \r\n*\r\n* B. Features have not been modelled\r\n*   1. Leakage current\r\n*   2. Overtemperature protection or Thermal Shutdown\r\n* \r\n* C. Application Notes\r\n*   1. The parameter STEADY_STATE has been used to reach the steady state faster.\r\n* \t   Keep STEADY_STATE = 0 to observe startup behaviour \r\n*      keep STEADY_STATE = 1 for faster Steady state.\r\n*********************************************************************************************\r\n.SUBCKT TPSM82823_TRANS EN FB GND_0 GND_1 PG VIN_0 VIN_1 VOUT_0 VOUT_1 VOUT_2 \r\n+ PARAMS: STEADY_STATE=1  \r\nX_SoftStart_U9         SDWN_N SoftStart_SDWN INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nC_SoftStart_C7         SS_TR 0  7.5n IC={STEADY_STATE*0.6} \r\nX_SoftStart_S1    SoftStart_N234157 0 SS_TR 0 SoftStart_SoftStart_S1 \r\nE_SoftStart_ABM2         SoftStart_N222011 0 VALUE { {(LIMIT(V(SS_TR), 0,\r\n+  1)*0.6)}    }\r\nX_SoftStart_U10         SoftStart_SDWN HICCUP SoftStart_N234157 OR2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nE_SoftStart_ABM1         SoftStart_N220347 0 VALUE { IF(V(SDWN_N) < 0.5,0,1)   \r\n+  }\r\nC_SoftStart_C5         0 INT_VREF  1n  \r\nC_SoftStart_C4         SoftStart_N220353 0  1n  \r\nV_SoftStart_V1         SoftStart_N221204 0 1.2\r\nG_SoftStart_ABMII1         SoftStart_N221204 SS_TR VALUE {\r\n+  V(SoftStart_N220353)*7.5u    }\r\nR_SoftStart_R10         SoftStart_N222011 INT_VREF  1  \r\nX_SoftStart_U8         SS_TR SoftStart_N221204 D_Dmod\r\nR_SoftStart_R9         SoftStart_N220353 SoftStart_N220347  1  \r\nG_G1         N16771131 0 TABLE { V(N16771131, 0) } \r\n+ ( (-1,0)(0,0)(0.1,0.4)(10,0.4) )\r\nC_C2         0 N16777411  1n  \r\nX_L1         SW VOUT_0 LDCR PARAMS: L=0.24u DCR=24m\r\nC_Enable_C1         0 Enable_N14548799  1n  \r\nR_Enable_R5         Enable_N14557215 Enable_N14559249  1k  \r\nE_Enable_ABM1         Enable_N06376 0 VALUE { (V(UVLO_OUT) * -160m)    }\r\nC_Enable_C3         0 Enable_N03743  1n  \r\nR_Enable_R2         Enable_N06376 Enable_N06443  1  \r\nE_Enable_ABM4         Enable_N14556103 0 VALUE { (V(EN_LOGIC) * -200m)    }\r\nE_Enable_ABM3         Enable_N14548793 0 VALUE { (V(Enable_N14548787) + 0.9)   \r\n+  }\r\nR_Enable_R4         Enable_N14556103 Enable_N14548787  1  \r\nX_Enable_U12         EN Enable_N14548799 Enable_EN_CHECK COMP_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=0.5\r\nC_Enable_C2         0 Enable_N06443  1n  \r\nX_Enable_U10         HICCUP Enable_N56049 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nC_Enable_C5         0 Enable_N14559249  362.5n IC=0 \r\nE_Enable_ABM5         Enable_N14557215 0 VALUE { If(V(Enable_EN_CHECK) >\r\n+  0.5,1,0)    }\r\nC_Enable_C4         0 Enable_N14548787  1n  \r\nX_Enable_U11         Enable_N56049 UVLO_OUT EN_LOGIC SDWN_N AND3_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nE_Enable_ABM6         Enable_N14559448 0 VALUE { IF(V(Enable_N14559249) >\r\n+  0.5,1,0)    }\r\nX_Enable_U13         VIN_0 Enable_N03743 UVLO_OUT COMP_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5\r\nR_Enable_R1         Enable_N14548793 Enable_N14548799  1  \r\nE_Enable_ABM2         Enable_N14550394 0 VALUE { (V(Enable_N06443) + 2.36)    }\r\nR_Enable_R3         Enable_N14550394 Enable_N03743  1  \r\nE_Enable_ABM8         EN_LOGIC 0 VALUE { IF(V(Enable_N14564528) > 0.5,1,0)    }\r\nE_Enable_ABM7         Enable_N14564528 0 VALUE { If(STEADY_STATE>\r\n+  0.5,1,V(Enable_N14559448))    }\r\nE_U2_ABM8         U2_N351837 0 VALUE { IF(V(U2_N352334)>0.04,V(U2_N352334),\r\n+  0.04)    }\r\nR_U2_R4         U2_N3516351 U2_N3515931  64k  \r\nX_U2_U3         U2_N13275 MIN_TON INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_U2_U9         U2_N351837 U2_N10820 U2_N13275 COMP_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5\r\nR_U2_R5         U2_N3516751 U2_N3516351  64k  \r\nX_U2_S1    U2_N12733 0 U2_N10820 0 Minton_U2_S1 \r\nR_U2_R6         U2_N3517151 U2_N3516751  64k  \r\nR_U2_R7         U2_N352334 U2_N3517151  64k  \r\nC_U2_C2         0 U2_N10820  2.48p  \r\nR_U2_R8         0 U2_N352334  64k  \r\nR_U2_R1         U2_N10820 VIN_0  600k  \r\nE_U2_E4         U2_N353755 0 VOUT_EQ 0 1\r\nR_U2_R3         U2_N3515931 U2_N353755  64k  \r\nX_U2_U11         HS_ON U2_N12733 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_U8         SDWN_N SDWN INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U629         PWM_NEW_N146576020 PWM_NEW_LS1 INV_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U36         PWM_NEW_N14656252 EN PWM_NEW_RESET NAND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U6         PWM_NEW_RESET PWM_NEW_RESETZ INV_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U26         PWM_NEW_SZ_HS HS_ON PWM_NEW_SZ_LS LS_ON PWM_NEW_N14656686\r\n+  AND4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U630         PWM_NEW_LS1 PWM_NEW_N14657690 INV_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U16         FB_COMP PWM_NEW_RESETZ PWM_NEW_HS_TURN_ON_ALLOWED\r\n+  PWM_NEW_SZ_HS NAND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R19         0 PWM_NEW_N14657746  1e12  \r\nX_PWM_NEW_U33         PWM_NEW_N14656918 PWM_NEW_RESETZ PWM_NEW_N14656804\r\n+  PWM_NEW_SZ_LS NAND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U631         PWM_NEW_N14657690 PWM_NEW_LS2 INV_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U9         PWM_NEW_HS PWM_NEW_HS PWM_NEW_HS PWM_NEW_RZ_PAUSE\r\n+  NAND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R25         0 PWM_NEW_N14657764  1e12  \r\nX_PWM_NEW_U624         RUNAWAY PWM_NEW_ILIM_LATCH_PRE INCREASE_TOFF\r\n+  OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R20         0 PWM_NEW_N14657770  1e12  \r\nX_PWM_NEW_U37         CAPRIO LS PWM_NEW_N14656344 AND2_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U17         MIN_TON PWM_NEW_N14656506 PWM_NEW_BLOCK_HSILIMZ\r\n+  NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U10         PWM_NEW_SZ_PAUSE PWM_NEW_N14656414 PAUSE NAND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R21         0 PWM_NEW_N14657740  1e12  \r\nV_PWM_NEW_V1         PWM_NEW_GATE_LSZ_DELAY 0 1\r\nX_PWM_NEW_U20         PWM_NEW_RESETZ PWM_NEW_N14656548 INV_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U29         PWM_NEW_HS PWM_NEW_GATE_LSZ_DELAY PWM_NEW_N14656810\r\n+  NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U34         PWM_NEW_SZ_LS PWM_NEW_N14657084 LS NAND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U11         PAUSE PWM_NEW_RZ_PAUSE PWM_NEW_N14656414 NAND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R22         0 PWM_NEW_N14657776  1e12  \r\nX_PWM_NEW_U18         PWM_NEW_N14656554 PWM_NEW_BLOCK_HSILIMZ PWM_NEW_N14656918\r\n+  NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R26         0 PWM_NEW_N14657758  1e12  \r\nR_PWM_NEW_R23         0 PWM_NEW_N14657752  1e12  \r\nX_PWM_NEW_U12         MIN_TOFF LS PWM_NEW_N14656444 NAND2_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U30         PWM_NEW_N14656810 PWM_NEW_N14656804 INV_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U35         LS PWM_NEW_RZ_LS PWM_NEW_N14657084 NAND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U626         PWM_NEW_ILIM_LATCH_PRE PWM_NEW_ILIM_LATCH1\r\n+  PWM_NEW_ILIM_LATC2 PWM_NEW_N14657560 NAND3_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_PWM_NEW_U19         CLIMIT_HS PWM_NEW_N14656548 PWM_NEW_N14656554\r\n+  NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R24         0 PWM_NEW_N14657728  1e12  \r\nX_PWM_NEW_U40         PWM_NEW_ILIM_LATCH_PRE PWM_NEW_N14657728 PWM_NEW_LS2\r\n+  CLIMIT_HS PWM_NEW_N14657740 PWM_NEW_N14657734 DFFSR_RHPBASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U23         LS PWM_NEW_N14656650 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_PWM_NEW_U627         PWM_NEW_N14657560 LS LS_ON AND2_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nE_PWM_NEW_E4         HS_ON 0 PWM_NEW_N14656804 0 1\r\nX_PWM_NEW_U13         PWM_NEW_N14656444 PWM_NEW_N14656430\r\n+  PWM_NEW_HS_TURN_ON_ALLOWED NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U24         PWM_NEW_N14656650 PWM_NEW_SZ_LS PWM_NEW_N14656664\r\n+  NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U27         PWM_NEW_SZ_HS PWM_NEW_N14657842 PWM_NEW_HS\r\n+  NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U31         PWM_NEW_N14656810 PWM_NEW_SZ_HS PWM_NEW_N14656854\r\n+  NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U1         SDWN PWM_NEW_N14656252 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_PWM_NEW_U41         PWM_NEW_ILIM_LATCH1 PWM_NEW_N14657752 PWM_NEW_LS1\r\n+  PWM_NEW_ILIM_LATCH_PRE PWM_NEW_N14657746 PWM_NEW_N14657758 DFFSR_RHPBASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U14         PAUSE PWM_NEW_N14656430 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_PWM_NEW_U25         PWM_NEW_RESET PWM_NEW_N14656664 PWM_NEW_N14656686\r\n+  PWM_NEW_RZ_HS NOR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U28         PWM_NEW_HS PWM_NEW_RZ_HS PWM_NEW_N14657842\r\n+  NAND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U3         PWM_NEW_HS LS LS PWM_NEW_N14656338 NOR3_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U32         PWM_NEW_RESET PWM_NEW_N14656854 PAUSE PWM_NEW_RZ_LS\r\n+  NOR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U628         LS PWM_NEW_N146576020 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_PWM_NEW_U42         PWM_NEW_ILIM_LATC2 PWM_NEW_N14657776 LS\r\n+  PWM_NEW_ILIM_LATCH1 PWM_NEW_N14657770 PWM_NEW_N14657764 DFFSR_RHPBASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWM_NEW_R27         PWM_NEW_N14657734 0  1e12  \r\nX_PWM_NEW_U15         FB_COMP PWM_NEW_N14656506 INV_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nX_PWM_NEW_U5         PWM_NEW_RESET PWM_NEW_N14656338 PWM_NEW_N14656344\r\n+  PWM_NEW_SZ_PAUSE NOR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_PWR_G_U11         FB PWR_G_N234900 PWR_G_N234798 COMP_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5\r\nR_PWR_G_R1         PWR_G_N216712 PWR_G_N00497  14.4k  \r\nC_PWR_G_C1         0 PWR_G_N00497  1n  \r\nX_PWR_G_U10         PWR_G_N00497 EN_LOGIC UVLO_OUT PWR_G_N225619\r\n+  NAND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nR_PWR_G_R4         PWR_G_N230586 PWR_G_N222445  1  \r\nE_PWR_G_ABM7         PWR_G_N222172 0 VALUE { (V(PWR_G_N221839)+  \r\n+ +V(PWR_G_N222445))   }\r\nX_PWR_G_U12         PWR_G_N234856 PWR_G_N234798 PWR_G_N234821 PWR_G_N234806\r\n+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nE_PWR_G_ABM4         PWR_G_N230586 0 VALUE { MAX(V(INT_VREF)*0.96,0.576)    }\r\nC_PWR_G_C6         0 PWR_G_N221839  1n  \r\nX_PWR_G_U7         PWR_G_N00497 PWR_G_N216712 D_Dmod\r\nX_PWR_G_U13         PWR_G_N234856 PWR_G_N234821 PWR_G_N216712 AND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nE_PWR_G_E6         PWR_G_N16773777 0 INT_VREF 0 0.5\r\nX_PWR_G_U9         PWR_G_N00497 PWR_G_OUT2 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=0.5\r\nC_PWR_G_C4         0 PWR_G_N222445  1n  \r\nE_PWR_G_ABM8         PWR_G_N234900 0 VALUE { IF(V(PWR_G_N234806)>0.5, 0.63,\r\n+  0.66)    }\r\nR_PWR_G_R3         PWR_G_N222172 PWR_G_N222282  1  \r\nX_PWR_G_U14         PWR_G_N16773777 FB RUNAWAY COMP_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5\r\nX_PWR_G_S1    PWR_G_N225619 0 PG 0 PG_SGND_PWR_G_S1 \r\nE_PWR_G_ABM6         PWR_G_N230669 0 VALUE { (V(INT_VREF)*-0.04*  \r\n+ V(PWR_G_OUT2))   }\r\nR_PWR_G_R6         PWR_G_N230669 PWR_G_N221839  1  \r\nX_PWR_G_U5         FB PWR_G_N222282 PWR_G_N234856 COMP_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5\r\nC_PWR_G_C3         0 PWR_G_N222282  1n  \r\nG_U_G1         U_VERR 0 INT_VREF U_FB_FLT -1.5u\r\nC_U_C8         0 U_SLOW  10p  \r\nE_U_E2         U_N00201 0 U_N03309 0 1\r\nE_U_E6         U_V_0P63 0 INT_VREF 0 1.05\r\nC_U_C9         U_FAST 0  0.9p  \r\nX_U_S4    SDWN 0 U_VERR 0 ErrorAmp_U_S4 \r\nC_U_C5         FB U_VERR  150f  \r\nR_U_R2         SW U_SLOW  2.6meg  \r\nC_U_C7         U_VERR 0  150f  \r\nC_U_C1         U_N00126 0  1p  \r\nR_U_R4         U_FAST SW  2.6meg  \r\nC_U_C6         FB 0  150f  \r\nC_U_C3         U_AC_SLOW 0  50f  \r\nC_U_C4         U_AC_FAST 0  50f  \r\nR_U_R5         U_N06466 U_AC_SLOW  5meg  \r\nR_U_R1         U_N04173 U_N00126  25k  \r\nR_U_R19         0 U_VERR  1e12  \r\nR_U_R6         U_AC_FAST U_N06466  5meg  \r\nC_U_C13         0 U_FB_FLT  0.25p  \r\nX_U_U1         U_N00126 0 FB_COMP COMP_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=0.5\r\nE_U_E7         U_V0P577 0 INT_VREF 0 0.952\r\nC_U_C16         FB_COMP U_AC_SLOW  20f  \r\nR_U_R20         U_SLOW VOUT_EQ  1m  \r\nG_U_G2         U_VERR 0 INT_VREF U_VERR {-1.5u/10}\r\nC_U_C10         U_FAST U_AC_FAST  4p  \r\nE_U_E4         U_N02097 0 U_AC_SLOW U_AC_FAST 0.333\r\nE_U_E5         U_N03309 0 U_VERR FB 1\r\nC_U_C12         0 U_VERR  4p  \r\nC_U_C11         U_SLOW U_AC_SLOW  4p  \r\nC_U_C2         U_AC_FAST U_AC_SLOW  50f  \r\nE_U_E1         U_N04173 U_N00201 U_N02097 0 1\r\nR_U_R7         FB U_FB_FLT  400k  \r\nV_U_V1         U_N06466 0 0.6\r\nX_U13_U624         U13_N16815087 U13_N16812330 BUF_DELAY_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=0.5 DELAY=1n\r\nX_U13_H1    VIN_0 U13_N16766927 ISENSE_HS 0 Driver_U13_H1 \r\nD_U13_D11         SW U13_N16766927 D_D1 \r\nE_U13_E1         U13_N16817291 0 TABLE { V(VIN_0, 0) } \r\n+ (\r\n+  (2.5,0.7307)(3,0.7484)(3.5,0.7561)(4,0.7665)(4.5,0.7739)(5,0.7853)(5.5,0.8) )\r\nX_U13_U621         U13_N16812551 U13_N16815087 INV_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nR_U13_R4         U13_N16817291 U13_N16817260  1  \r\nC_U13_C2         0 U13_N16817260  1n  \r\nX_U13_S3    U13_N16816932 0 U13_N16766927 SW Driver_U13_S3 \r\nX_U13_U625         U13_N16814911 U13_N16812362 BUF_DELAY_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=0.5 DELAY=1n\r\nX_U13_U11         U13_N16812551 DRVH_PRE BUF_DELAY_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5 DELAY=2n\r\nX_U13_U623         U13_N16768053 U13_N16814911 INV_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=500E-3\r\nX_U13_U7         0 U13_N16817425 DRVL_PRE U13_N167665690 MUX2_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=0.5\r\nX_U13_U617         HS_ON U13_N16812362 U13_N16812551 AND2_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_U13_H2    U13_N16766531 0 0 ISENSE_LS Driver_U13_H2 \r\nD_U13_D12         U13_N16766531 SW D_D1 \r\nX_U13_U12         U13_N16768053 DRVL_PRE BUF_DELAY_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5 DELAY=2n\r\nX_U13_U618         U13_N16812330 LS_ON U13_N16768053 AND2_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=500E-3\r\nX_U13_U626         0 U13_N16817260 DRVH_PRE U13_N16816932 MUX2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nE_U13_E6         U13_N16817456 0 TABLE { V(VIN_0, 0) } \r\n+ (\r\n+  (2.5,0.7351)(3,0.7499)(3.5,0.7605)(4,0.7696)(4.5,0.7762)(5,0.7893)(5.5,0.8) )\r\nX_U13_S4    U13_N167665690 0 SW U13_N16766531 Driver_U13_S4 \r\nR_U13_R5         U13_N16817456 U13_N16817425  1  \r\nC_U13_C3         0 U13_N16817425  1n  \r\nX_S3    SDWN 0 SW N16771131 TPSM82823_TRANS_S3 \r\nX_Curr_Limit_S5    Curr_Limit_N16803351 0 Curr_Limit_N16803282 0\r\n+  Current_Limit_Curr_Limit_S5 \r\nR_Curr_Limit_R12         Curr_Limit_RS_8_CYCLE Curr_Limit_N16807543  150  \r\nC_Curr_Limit_C6         0 Curr_Limit_N16807543  1n IC=0 \r\nX_Curr_Limit_U625         CLIMIT_HS Curr_Limit_N16807543 Curr_Limit_N16803351\r\n+  OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_Curr_Limit_U619         Curr_Limit_N16803282 Curr_Limit_N16803299\r\n+  Curr_Limit_N16803181 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nD_Curr_Limit_D11         Curr_Limit_N16774792 Curr_Limit_N16774858 D_D1 \r\nX_Curr_Limit_U613         Curr_Limit_MIN_TOFF_CL Curr_Limit_N16774898\r\n+  Curr_Limit_N16774934 MONOPOS_PS PARAMS: PW=20n\r\nV_Curr_Limit_V10         Curr_Limit_N16868343 0 4.3\r\nV_Curr_Limit_V9         Curr_Limit_N16803299 0 1.5\r\nX_Curr_Limit_U3         ISENSE_HS Curr_Limit_N16868343 Curr_Limit_N16849425\r\n+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nX_Curr_Limit_S3    Curr_Limit_HICCUP_RESET 0 Curr_Limit_N16774792 0\r\n+  Current_Limit_Curr_Limit_S3 \r\nX_Curr_Limit_U4         Curr_Limit_N16849425 DRVH_PRE Curr_Limit_N16849411\r\n+  AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nD_Curr_Limit_D13         Curr_Limit_N16803282 Curr_Limit_N16803326 D_D1 \r\nG_Curr_Limit_ABMII1         0 Curr_Limit_N16774792 VALUE {\r\n+  V(Curr_Limit_N16774898)    }\r\nR_Curr_Limit_R3         HICCUP Curr_Limit_N16774450  1  \r\nR_Curr_Limit_R14         0 Curr_Limit_N16882685  1e8  \r\nC_Curr_Limit_C8         0 Curr_Limit_N16849417  1n  \r\nD_Curr_Limit_D14         Curr_Limit_RS_8_CYCLE Curr_Limit_N16807543 D_D1 \r\nC_Curr_Limit_C4         0 HICCUP  1n  \r\nR_Curr_Limit_R9         Curr_Limit_N16849411 Curr_Limit_N16849417  20  \r\nC_Curr_Limit_C9         0 Curr_Limit_N16803282  20n IC=0 \r\nX_Curr_Limit_U12         Curr_Limit_N16849417 Curr_Limit_N16849411 D_Dmod\r\nC_Curr_Limit_C5         0 Curr_Limit_N16805640  1n IC=0 \r\nC_Curr_Limit_C3         0 Curr_Limit_N16774792  5n IC=0 \r\nX_Curr_Limit_U23         Curr_Limit_N16882718 MIN_TOFF Curr_Limit_MIN_TOFF_CL\r\n+  Curr_Limit_N16882685 SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nR_Curr_Limit_R7         0 Curr_Limit_N16774934  1e8  \r\nX_Curr_Limit_U618         DRVH_PRE Curr_Limit_N16803342 Curr_Limit_N16803354\r\n+  MONOPOS_PS PARAMS: PW=20n\r\nX_Curr_Limit_U13         Curr_Limit_N16849417 CLIMIT_HS BUF_BASIC_GEN PARAMS:\r\n+  VDD=1 VSS=0 VTHRESH=0.5\r\nR_Curr_Limit_R5         Curr_Limit_RS_8_CYCLE Curr_Limit_N16803181  1  \r\nX_Curr_Limit_U626         CLIMIT_HS Curr_Limit_N16882718 Curr_Limit_N16882725\r\n+  MONOPOS_PS PARAMS: PW=20n\r\nC_Curr_Limit_C7         0 Curr_Limit_RS_8_CYCLE  1n  \r\nX_Curr_Limit_U612         Curr_Limit_N16774792 Curr_Limit_N16774804\r\n+  Curr_Limit_N16774450 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nR_Curr_Limit_R11         0 Curr_Limit_N16803354  1e8  \r\nD_Curr_Limit_D12         Curr_Limit_N16805640 HICCUP D_D1 \r\nV_Curr_Limit_V3         Curr_Limit_N16774858 0 33\r\nR_Curr_Limit_R13         0 Curr_Limit_N16882725  1e8  \r\nV_Curr_Limit_V8         Curr_Limit_N16803326 0 5\r\nV_Curr_Limit_V4         Curr_Limit_N16774804 0 31.5\r\nG_Curr_Limit_ABMII2         0 Curr_Limit_N16803282 VALUE {\r\n+  V(Curr_Limit_N16803342)    }\r\nR_Curr_Limit_R8         HICCUP Curr_Limit_N16805640  184.704k  \r\nX_Curr_Limit_U622         Curr_Limit_RS_8_CYCLE Curr_Limit_N16805640\r\n+  Curr_Limit_HICCUP_RESET OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_Caprio_U12         Caprio_N23722 ISENSE_LS Caprio_N34587 COMP_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nX_Caprio_U14         Caprio_N15145 DRVH_PRE CAPRIO N20512 SRLATCHRHP_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nX_Caprio_U15         Caprio_N34511 DRVL_PRE D_Dmod\r\nX_Caprio_U16         Caprio_N34511 Caprio_N34543 BUF_BASIC_GEN PARAMS: VDD=1\r\n+  VSS=0 VTHRESH=0.5\r\nV_Caprio_V1         Caprio_N23722 0 15m\r\nR_Caprio_R9         DRVL_PRE Caprio_N34511  5  \r\nX_Caprio_U13         Caprio_N34543 Caprio_N34587 Caprio_N15145 AND2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nC_Caprio_C8         0 Caprio_N34511  1n  \r\nX_Min_Toff_S5    Min_Toff_N16816452 0 Min_Toff_N16813727 Min_Toff_N16816620\r\n+  Mintoff_Modified_Min_Toff_S5 \r\nR_Min_Toff_R1         Min_Toff_N16816620 Min_Toff_N16813727  1.56meg  \r\nC_Min_Toff_C4         0 Min_Toff_N16813993  300f  \r\nV_Min_Toff_V5         Min_Toff_N16813727 0 1.8\r\nR_Min_Toff_R2         Min_Toff_N16813845 Min_Toff_N16816620  51k  \r\nX_Min_Toff_U10         Min_Toff_N16813845 Min_Toff_N16813727 D_Dmod\r\nX_Min_Toff_S4    RUNAWAY 0 Min_Toff_N16813845 Min_Toff_N16813993\r\n+  Mintoff_Modified_Min_Toff_S4 \r\nX_Min_Toff_S1    Min_Toff_N16813865 0 Min_Toff_N16813845 0\r\n+  Mintoff_Modified_Min_Toff_S1 \r\nX_Min_Toff_U11         LS Min_Toff_N16813865 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+  VTHRESH=500E-3\r\nX_Min_Toff_U9         Min_Toff_N16813845 Min_Toff_N16813732 MIN_TOFF\r\n+  COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nX_Min_Toff_U623         Min_Toff_N16816484 Min_Toff_N16816452 INV_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nV_Min_Toff_V4         Min_Toff_N16813732 0 0.9\r\nC_Min_Toff_C2         0 Min_Toff_N16813845  600f  \r\nX_Min_Toff_U625         INCREASE_TOFF RUNAWAY Min_Toff_N16816484 OR2_BASIC_GEN\r\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\r\nX_U19         N16777411 N16777406 D_Dmod\r\nX_U26         N16777411 P100 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nE_GAIN1         N16777406 0 VALUE {1 * V(HS_ON)}\r\nR_R6         0 N16771131  1e6  \r\nR_R3         N16777406 N16777411  4k  \r\n.IC         V(SS_TR )={STEADY_STATE*0.6}\r\n.IC         V(U_VERR )=0\r\n.ENDS TPSM82823_TRANS\r\n*$\r\n.subckt SoftStart_SoftStart_S1 1 2 3 4  \r\nS_SoftStart_S1         3 4 1 2 _SoftStart_S1\r\nRS_SoftStart_S1         1 2 1G\r\n.MODEL         _SoftStart_S1 VSWITCH Roff=1e9 Ron=100 Voff=0.2 Von=0.8\r\n.ends SoftStart_SoftStart_S1\r\n*$\r\n.subckt Minton_U2_S1 1 2 3 4  \r\nS_U2_S1         3 4 1 2 _U2_S1\r\nRS_U2_S1         1 2 1G\r\n.MODEL         _U2_S1 VSWITCH Roff=100e6 Ron=1 Voff=0.2 Von=0.8\r\n.ends Minton_U2_S1\r\n*$\r\n.subckt PG_SGND_PWR_G_S1 1 2 3 4  \r\nS_PWR_G_S1         3 4 1 2 _PWR_G_S1\r\nRS_PWR_G_S1         1 2 1G\r\n.MODEL         _PWR_G_S1 VSWITCH Roff=100e6 Ron=150 Voff=0.2V Von=0.8\r\n.ends PG_SGND_PWR_G_S1\r\n*$\r\n.subckt ErrorAmp_U_S4 1 2 3 4  \r\nS_U_S4         3 4 1 2 _U_S4\r\nRS_U_S4         1 2 1G\r\n.MODEL         _U_S4 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8\r\n.ends ErrorAmp_U_S4\r\n*$\r\n.subckt Driver_U13_H1 1 2 3 4  \r\nH_U13_H1         3 4 VH_U13_H1 1\r\nVH_U13_H1         1 2 0V\r\n.ends Driver_U13_H1\r\n*$\r\n.subckt Driver_U13_S3 1 2 3 4  \r\nS_U13_S3         3 4 1 2 _U13_S3\r\nRS_U13_S3         1 2 1G\r\n.MODEL         _U13_S3 VSWITCH Roff=10e6 Ron=26m Voff=0.2 Von=0.8\r\n.ends Driver_U13_S3\r\n*$\r\n.subckt Driver_U13_H2 1 2 3 4  \r\nH_U13_H2         3 4 VH_U13_H2 1\r\nVH_U13_H2         1 2 0V\r\n.ends Driver_U13_H2\r\n*$\r\n.subckt Driver_U13_S4 1 2 3 4  \r\nS_U13_S4         3 4 1 2 _U13_S4\r\nRS_U13_S4         1 2 1G\r\n.MODEL         _U13_S4 VSWITCH Roff=10e6 Ron=26m Voff=0.2 Von=0.8\r\n.ends Driver_U13_S4\r\n*$\r\n.subckt TPSM82823_TRANS_S3 1 2 3 4  \r\nS_S3         3 4 1 2 _S3\r\nRS_S3         1 2 1G\r\n.MODEL         _S3 VSWITCH Roff=1e6 Ron=1m Voff=0.2 Von=0.8\r\n.ends TPSM82823_TRANS_S3\r\n*$\r\n.subckt Current_Limit_Curr_Limit_S5 1 2 3 4  \r\nS_Curr_Limit_S5         3 4 1 2 _Curr_Limit_S5\r\nRS_Curr_Limit_S5         1 2 1G\r\n.MODEL         _Curr_Limit_S5 VSWITCH Roff=1e6 Ron=1m Voff=0.25 Von=0.75\r\n.ends Current_Limit_Curr_Limit_S5\r\n*$\r\n.subckt Current_Limit_Curr_Limit_S3 1 2 3 4  \r\nS_Curr_Limit_S3         3 4 1 2 _Curr_Limit_S3\r\nRS_Curr_Limit_S3         1 2 1G\r\n.MODEL         _Curr_Limit_S3 VSWITCH Roff=100e6 Ron=1u Voff=0.1 Von=0.9\r\n.ends Current_Limit_Curr_Limit_S3\r\n*$\r\n.subckt Mintoff_Modified_Min_Toff_S5 1 2 3 4  \r\nS_Min_Toff_S5         3 4 1 2 _Min_Toff_S5\r\nRS_Min_Toff_S5         1 2 1G\r\n.MODEL         _Min_Toff_S5 VSWITCH Roff=10e6 Ron=1.0 Voff=0.2 Von=0.8\r\n.ends Mintoff_Modified_Min_Toff_S5\r\n*$\r\n.subckt Mintoff_Modified_Min_Toff_S4 1 2 3 4  \r\nS_Min_Toff_S4         3 4 1 2 _Min_Toff_S4\r\nRS_Min_Toff_S4         1 2 1G\r\n.MODEL         _Min_Toff_S4 VSWITCH Roff=100e6 Ron=1.0 Voff=0.2 Von=0.8\r\n.ends Mintoff_Modified_Min_Toff_S4\r\n*$\r\n.subckt Mintoff_Modified_Min_Toff_S1 1 2 3 4  \r\nS_Min_Toff_S1         3 4 1 2 _Min_Toff_S1\r\nRS_Min_Toff_S1         1 2 1G\r\n.MODEL         _Min_Toff_S1 VSWITCH Roff=10e6 Ron=1.0 Voff=0.2 Von=0.8\r\n.ends Mintoff_Modified_Min_Toff_S1\r\n*$\r\n.subckt d_dmod 1 2\r\nd1 1 2 d_d1\r\n.ends d_dmod\r\n*$\r\n.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.01 N=.1  )\r\n*$\r\n.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\r\nE_ABM Yint 0 VALUE {IF (V(INP) > \r\n+ V(INM), {VDD},{VSS})}\r\nR1 Yint Y 1\r\nC1 Y 0 250p\r\n.ENDS COMP_BASIC_GEN\r\n*$\r\n.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\r\nEIN INP1 INM1 INP INM 1 \r\nEHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }\r\nEOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }\r\nR1 OUT 1 1\r\nC1 1 0 500p\r\nRINP1 INP1 0 1K\r\n.ENDS COMPHYS_BASIC_GEN\r\n*$\r\n.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\r\n+ T=10\r\nEIN INP1 INM1 INP INM 1 \r\nEHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }\r\nEOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) }\r\nR1 OUT 1 1\r\nC1 1 0 {T*1e-10}\r\nRINP1 INP1 0 10K\r\nRINM2 INM2 0 10K\r\n.ENDS COMPHYS2_BASIC_GEN\r\n*$\r\n.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \r\n+ V(B) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS AND2_BASIC_GEN\r\n*$\r\n.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \r\n+ V(B) > {VTHRESH} &\r\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS AND3_BASIC_GEN\r\n*$\r\n.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \r\n+ V(B) > {VTHRESH} &\r\n+ V(C) > {VTHRESH} &\r\n+ V(D) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS AND4_BASIC_GEN\r\n*$\r\n.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \r\n+ V(B) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NAND2_BASIC_GEN\r\n*$\r\n.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \r\n+ V(B) > {VTHRESH} &\r\n+ V(C) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NAND3_BASIC_GEN\r\n*$\r\n.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \r\n+ V(B) > {VTHRESH} &\r\n+ V(C) > {VTHRESH} &\r\n+ V(D) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NAND4_BASIC_GEN\r\n*$\r\n.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS OR2_BASIC_GEN\r\n*$\r\n.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH} |\r\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS OR3_BASIC_GEN\r\n*$\r\n.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH} |\r\n+ V(C) > {VTHRESH} |\r\n+ V(D) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS OR4_BASIC_GEN\r\n*$\r\n.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NOR2_BASIC_GEN\r\n*$\r\n.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH} |\r\n+ V(C) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NOR3_BASIC_GEN\r\n*$\r\n.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH} |\r\n+ V(C) > {VTHRESH} |\r\n+ V(D) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NOR4_BASIC_GEN\r\n*$\r\n.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH} |\r\n+ V(C) > {VTHRESH} |\r\n+ V(D) > {VTHRESH} |\r\n+ V(E) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NOR5_BASIC_GEN\r\n*$\r\n.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \r\n+ V(B) > {VTHRESH} |\r\n+ V(C) > {VTHRESH} |\r\n+ V(D) > {VTHRESH} |\r\n+ V(E) > {VTHRESH} |\r\n+ V(F) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS NOR6_BASIC_GEN\r\n*$\r\n.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS INV_BASIC_GEN\r\n*$\r\n.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  \r\n+ V(B) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS XOR2_BASIC_GEN\r\n*$\r\n.SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  \r\n+ V(B) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS XNOR2_BASIC_GEN\r\n*$\r\n.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE  YINT 0 VALUE {{IF(V(S) > {VTHRESH},  \r\n+ V(B),V(A))}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS MUX2_BASIC_GEN\r\n*$\r\n.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \r\nE_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT YINT1 YINT2 1\r\nCINT YINT2 0 {DELAY*1.3}\r\nE_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \r\n+ {VSS},{VDD})}}\r\nRINT2 YINT3 Y 1\r\nCINT2 Y 0 250p\r\n.ENDS INV_DELAY_BASIC_GEN\r\n*$\r\n.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \r\nE_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT YINT1 YINT2 1\r\nCINT YINT2 0 {DELAY*1.3}\r\nE_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT2 YINT3 Y 1\r\nCINT2 Y 0 250p\r\n.ENDS BUF_DELAY_BASIC_GEN\r\n*$\r\n.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 250p\r\n.ENDS BUF_BASIC_GEN\r\n*$\r\n.SUBCKT SRLATCHSHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nGQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R)>{VTHRESH},-5, 0))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr QB 1 \r\nCdummy1 Q 0 250p \r\nCdummy2 QB 0 250p \r\n.IC V(Qint) {VSS}\r\n.ENDS SRLATCHSHP_BASIC_GEN\r\n*$\r\n.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nGQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr QB 1 \r\nCdummy1 Q 0 250p \r\nCdummy2 QB 0 250p\r\n.IC V(Qint) {VSS}\r\n.ENDS SRLATCHRHP_BASIC_GEN\r\n*$\r\n.SUBCKT SBRBLATCHRHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nGQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB) < {VTHRESH},5, 0))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr QB 1 \r\n.IC V(Qint) {VSS}\r\n.ENDS SBRBLATCHRHP_BASIC_GEN\r\n*$\r\n.SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nGQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB) < {VTHRESH},-5, 0))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr QB 1 \r\n.IC V(Qint) {VSS}\r\n.ENDS SBRBLATCHSHP_BASIC_GEN\r\n*$\r\n.SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n\r\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\r\nGQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, \r\n+ IF(V(D)> {VTHRESH},5,-5),0)))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr Qb 1 \r\nCdummy1 Q 0 250pF \r\nCdummy2 QB 0 250pF \r\n.IC V(Qint) {VSS}\r\n.ENDS DFFSBRB_SHPBASIC_GEN\r\n*$\r\n.SUBCKT DFFSR_SHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n\r\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} \r\nGQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, \r\n+ IF(V(D)> {VTHRESH},5,-5),0)))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 20n\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr Qb 1 \r\nCdummy1 Q 0 250pF \r\nCdummy2 QB 0 250pF \r\n.IC V(Qint) {VSS}\r\n.ENDS DFFSR_SHPBASIC_GEN\r\n*$\r\n.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n\r\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} \r\nGQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, \r\n+ IF(V(D)> {VTHRESH},5,-5),0)))}\r\nCQint Qint 0 250p\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 5\r\nD_D11 0 Qint D_D1 \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr Qb 1 \r\nCdummy1 Q 0 250pF \r\nCdummy2 QB 0 250pF \r\n.IC V(Qint) {VSS}\r\n.ENDS DFFSBRB_RHPBASIC_GEN\r\n*$\r\n.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 2n\r\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}  \r\nGQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, \r\n+ IF(V(D)> {VTHRESH},5,-5),0)))}\r\nCQint Qint 0 1n\r\nRQint Qint 0 1000MEG\r\nD_D10 Qint MY5 D_D1\r\nV1 MY5 0 {VDD}\r\nD_D11 MYVSS Qint D_D1\r\nV2 MYVSS 0 {VSS} \r\nEQ Qqq 0 Qint 0 1\r\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n\r\nRQq Qqqd1 Q 1\r\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\r\nRQb Qbr Qb 1 \r\nCdummy1 Q 0 1nF \r\nCdummy2 QB 0 1nF \r\n.IC V(Qint) {VSS}\r\n.ENDS DFFSR_RHPBASIC_GEN\r\n*$\r\n.SUBCKT MONOPOS_PS in Q Qn PARAMS: PW=1u \r\nVS VSUP 0 DC 1\r\nGIN VSUP YA VALUE={IF(V(IN)>0.5, V(VSUP)/1000K, 0)}\r\nGDIS YA 0 VALUE={IF(V(IN)>0.5,0, V(YA)/1m)}\r\nCIN YA 0 250p IC=0\r\nRIN YA 0 1e11\r\nEABM1 YTD 0 VALUE={IF(V(YA)> {PW*1000}, 1, 0)}\r\nRYTD YTD 0 1e11\r\nEXOR P 0 VALUE={IF(V(YTD) > 0.5 ^ V(IN) > .5, 1, 0)}\r\nROUTpp2 P 0 1e11\r\nEAND1 Q1 0 VALUE={ IF(V(P)>0.5 & V(IN)>0.5, 1, 0)}\r\nRo1 Q1 Q 1m\r\nCo1 Q 0 1p\r\nROUT2 Q 0 1e11\r\nEAND2 Qn1 0 VALUE={ IF(V(Q)>0.5, 0, 1)}\r\nRo2 Qn1 Qn 1m\r\nCo2 Qn 0 1p\r\nROUT4 Qn 0 1e11\r\n.ENDS MONOPOS_PS\r\n*$\r\n.SUBCKT LDCR 1 2 PARAMS: L=1u DCR=20m IC=0\r\nL1 1 INT1 {L} IC={IC}\r\nR1 INT1 2 {DCR}\r\n.ENDS LDCR\r\n*$\r\n.SUBCKT CESR IN OUT\r\n+ PARAMS:  C=100u ESR=0.01 X=1 IC=0\r\nC\tIN 1  {C*X} IC={IC}\r\nRESR\t1 OUT {ESR/X}\r\n.ENDS CESR\r\n*quot;
}