tscircuit/ti
ti tscircuit library
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lib/chips/spice-models/TPS62933P-spice-model.json
{
"source": "*$\r\n* TPS62933P\r\n*****************************************************************************\r\n* (C) Copyright 2022 Texas Instruments Incorporated. All rights reserved. \r\n*****************************************************************************\r\n** This model is designed as an aid for customers of Texas Instruments.\r\n** TI and its licensors and suppliers make no warranties, either expressed\r\n** or implied, with respect to this model, including the warranties of \r\n** merchantability or fitness for a particular purpose. The model is\r\n** provided solely on an \"as is\" basis. The entire risk as to its quality\r\n** and performance is with the customer\r\n*****************************************************************************\r\n*\r\n* This model is subject to change without notice. Texas Instruments\r\n* Incorporated is not responsible for updating this model.\r\n*\r\n*****************************************************************************\r\n*\r\n** Released by: Texas Instruments Inc.\r\n* Part: TPS62933P\r\n* Date: 24MAY2022\r\n* Model Type: TRANSIENT\r\n* Simulator: PSPICE\r\n* Simulator Version: 17.4-2019 S024\r\n* EVM Order Number: NA\r\n* EVM Users Guide: NA\r\n* Datasheet: SLUSEA4B – JUNE 2021 – REVISED FEBRUARY 2022\r\n* Topologies Supported: Buck\r\n*\r\n* Model Version: Final 1.00\r\n*\r\n*****************************************************************************\r\n*\r\n* Updates:\r\n*\r\n* Final 1.00\r\n* Release to Web.\r\n*\r\n*****************************************************************************\r\n*\r\n* Model Usage Notes:\r\n* A. Features have been modelled\r\n*\t1. \tOutput Voltage Setting\r\n*\t2. \tExternal Adjustable Soft-start\r\n* 3. Adjustable UVLO\r\n*\t4. \tFrequency Selection\r\n*\t5. \tLow-side FET Zero-Crossing\r\n*\t6. \tCurrent Sense and Positive Overcurrent Protection(OCP)\r\n*\t7. \tOver Voltage Protection(OVP)\r\n*\t8. Under Voltage Protection(UVP)\r\n*\t9. UVLO Protection\r\n*\t10. BOOT functionality\r\n* 11. PGOOD functionality\r\n*\r\n* B. Features have not been modelled\r\n*\t1. Operating Quiescent Current\r\n* 2. Shutdown Current \r\n* 3. Temperature dependent characteristics\r\n*\r\n* C. Application Notes\r\n*\t1. The parameter STEADY_STATE has been used to reach the steady state faster. \r\n* Keep STEADY_STATE = 0 to observe startup behaviour. \r\n* Keep STEADY_STATE = 1 and appropriate IC on Inductor and capacitor to observe for faster Steady state.\r\n* 2. The parameter EN_FSS has been used to Enable/Disable FSS behaviour. \r\n*\t Keep EN_FSS = 0 to disable Frequency Spread Spectrum \r\n*\t Keep EN_FSS = 1 to observe Frequency Spread Spectrum after 1.5*Tss. +\r\n* 3. Ground Pins have been tied to 0V internally and hence model does not support Inverting \r\n* topologies.\r\n*\r\n*****************************************************************************\r\n.SUBCKT TPS62933P_TRANS BST EN FB GND PG RT SW VIN PARAMS: STEADY_STATE=0\r\n+ EN_FSS=0\r\nV_V23 N16612714 0 {0.9*0.8}\r\nC_C6 0 VREF_FSS2 1.443n TC=0,0 \r\nV_V20 N16612994 0 2\r\nX_U709 N16612728 N16612734 asymmetric_delay PARAMS:\r\n+ RISING_EDGE_DELAY=1n VTHRESH=0.5 FALLING_EDGE_DELAY=18u VDD=1 VSS=0\r\nX_U832 N16612994 VIN VIN_PGD_VALID COMP_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+ VTHRESH=0.5\r\nX_U5_U18 LSG_ON U5_N16552314 U5_N16554198 AND2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nG_U5_ABM2I1 U5_N16552136 U5_N16552132 VALUE { LIMIT(({(V(SS_INT)\r\n+ -V(U5_N16551946))*NOC}),{NOC},-1u) }\r\nV_U5_V7 U5_N165517613 0 2m\r\nX_U5_U22 U5_N16554198 U5_LON_DLY ZC_NOC AND2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nX_U5_U20 NOC_LATCH N16553397 ZC_NOC V5V U5_N16552422 0\r\n+ dffsr_rhpbasic_gen PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nV_U5_V6 U5_N16550975 0 2m\r\nX_U5_U16 U5_N16552024 U5_N16552314 INV_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=5n\r\nR_U5_R1 U5_N16552136 0 1 TC=0,0 \r\nX_U5_U12 LSG_ON U5_LON_DLY asymmetric_delay PARAMS:\r\n+ RISING_EDGE_DELAY=140n VTHRESH=2.5 FALLING_EDGE_DELAY=1n VDD=5 VSS=0\r\nR_U5_R2 0 U5_N16552132 1 TC=0,0 \r\nX_U5_U23 HSG_ON U5_N16552422 BUF_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nV_U5_VREF U5_N16551946 0 0.8\r\nX_U5_U40 VALLEY_OC NOC_LATCH CONT OR2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U5_U14 U5_N16551556 U5_N16551560 INV_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=5n\r\nX_U5_U13 U5_N16551560 U5_LON_DLY VALLEY_OC AND2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nX_U5_U8 ISAMPLE IVALLEY U5_N16550975 U5_N16551556 COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U5_U15 ISAMPLE U5_N16551775 U5_N165517613 U5_N16552024\r\n+ COMPHYS_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nE_U5_ABM1 U5_DCM 0 VALUE { (V(NOC_LATCH) ) }\r\nV_U5_V8 U5_N16551775 U5_N16552136 250m\r\nE_E1 FB_INT 0 FB GND 1\r\nX_U833 N16613349 FB N16613397 N16613565 COMPHYS_BASIC_GEN PARAMS: VDD=1\r\n+ VSS=0 VTHRESH=0.5\r\nC_U10_C1 0 U10_7_CYCLE_OVER 1.443n TC=0,0 \r\nV_U10_V8 U10_N16777177 0 {0.8*0.65}\r\nR_U10_R2 HICCUP_RST U10_N16781285 1k TC=0,0 \r\nV_U10_VHYS U10_HYS 0 1m\r\nX_U10_U28 U10_N16781285 SS_UNDER_0V U10_N16781533 AND2_BASIC_GEN\r\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nX_U10_U11 FB_INT U10_N16777177 U10_HYS U10_UVP_HIGH_N COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nC_U10_C2 0 U10_N16781285 1.443n TC=0,0 \r\nX_U10_U9 U10_N16781533 U10_N16780624 one_shot PARAMS: T=50 \r\nX_U10_U859 U10_N16780624 U10_COUNT N16780635 0 0 U10_RESET COUNTER\r\n+ PARAMS: MIN_PW=50n COUNT_RST=9\r\nE_U10_ABM1 U10_N16779738 0 VALUE { IF(V(U10_UVP_HIGH_N)<0.5 &\r\n+ V(SS_OVER_0P8)>0.5,1,0) }\r\nX_U10_U12 U10_N16779738 U10_N16779741 asymmetric_delay PARAMS:\r\n+ RISING_EDGE_DELAY=256u VTHRESH=0.5 FALLING_EDGE_DELAY=1u VDD=1 VSS=0\r\nE_U10_ABM3 U10_N16781051 0 VALUE { if(V(U10_COUNT)>7.9,1,0) }\r\nX_U10_U860 U10_N16779741 U10_7_CYCLE_OVER HICCUP_RST N16777321\r\n+ srlatchrhp_basic_gen PARAMS: VDD=5 VSS=0 VTHRESH=0.5\r\nR_U10_R1 U10_N16781051 U10_7_CYCLE_OVER 500 TC=0,0 \r\nG_U9_G3 IPRESET 0 U9_N16555324 0 40u\r\nX_U9_U2 N16556472 U9_N16556377 RAMP_OK_LATCH TOFF_B SS_OVER_0P8\r\n+ U9_N16556364 dffsbrb_rhpbasic_gen PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nR_U9_R1 U9_N16555250 0 25k TC=0,0 \r\nX_U9_F1 V5V U9_N16555082 V5V U9_N16555324 SLOPE_COMP_U9_F1 \r\nX_U9_S5 U9_SW2 0 U9_N16555232 U9_N16555236 SLOPE_COMP_U9_S5 \r\nX_U9_U6 U9_N16556812 HSG_ON U9_SW2 NOR2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U9_S7 U9_N16556185 0 U9_N16555324 0 SLOPE_COMP_U9_S7 \r\nR_U9_R2 U9_N16555139 0 25k TC=0,0 \r\nX_U9_U10 U9_N16556701 U9_N16556826 U9_SW3 NOR2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nR_U9_R3 U9_N16555324 0 25k TC=0,0 \r\nG_U9_G1 U9_N16555082 U9_N16555139 CLK_RAMP U9_N16555139 1\r\nG_U9_G2 U9_N16555324 U9_N16555250 U9_N16555236 U9_N16555250 1\r\nX_U9_S4 U9_SW1 0 U9_N16555228 U9_N16555232 SLOPE_COMP_U9_S4 \r\nX_U9_U7 U9_N16556826 U9_N16556812 BUF_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=2n\r\nX_U9_U3 U9_N16556377 HSG_ON U9_N16556185 NAND2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nX_U9_U11 U9_N16556964 0 U9_SW1 NOR2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nC_U9_C1 U9_N16555236 0 5p IC=0 TC=0,0 \r\nX_U9_U9 U9_N16556826 U9_N16556964 INV_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=2p\r\nX_U9_U4 HSG_ON U9_N16556701 INV_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nC_U9_C2 U9_N16555232 0 100f IC=0 TC=0,0 \r\nX_U9_S6 U9_SW3 0 U9_N16555232 0 SLOPE_COMP_U9_S6 \r\nE_U9_ABM1 U9_N16555228 0 VALUE { LIMIT(V(U9_N16555139),5,0) }\r\nV_U9_V4 U9_N16556364 0 5\r\nX_U9_U5 U9_N16556701 U9_N16556777 U9_N16556826 NOR2_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nX_U9_U8 U9_SW2 U9_N16556777 BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=2n\r\nV_U6_V7 U6_N165558043 0 1m\r\nX_U6_U22 HSG_ON U6_N16556123 asymmetric_delay PARAMS:\r\n+ RISING_EDGE_DELAY=70n VTHRESH=2.5 FALLING_EDGE_DELAY=1n VDD=5 VSS=0\r\nX_U6_U23 HSG_ON U6_N16556137 asymmetric_delay PARAMS:\r\n+ RISING_EDGE_DELAY=7u VTHRESH=2.5 FALLING_EDGE_DELAY=1n VDD=5 VSS=0\r\nX_U6_U20 U6_N16556263 U6_N16556027 HRESET_B AND2_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nX_U6_U25 U6_N16559383 U6_HS_COMP_OUT BUF_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=5n\r\nX_U6_U18 ISAMPLE ISET U6_N165558043 U6_N16559383 COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U6_U24 U6_N16556137 U6_N16556263 INV_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=1n\r\nX_U6_U21 U6_N16556123 U6_HS_COMP_OUT U6_N16556027 NAND2_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U7_H1 U7_N16558691 SW ISAMPLE 0 DRIVER_U7_H1 \r\nD_U7_D5 GND U7_N16558691 D_Body \r\nX_U7_U21 HRESET_B U7_N16552666 INV_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=1n\r\nX_U7_U720 U7_N16563264 U7_N16563374 U7_N16563396 U7_N16563314\r\n+ COMPHYS_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nV_U7_V11 U7_N16563396 0 50m\r\nX_U7_U29 HSG_IN HSG_ON BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=5n\r\nX_U7_S7 U7_N16560259 0 U7_HDRV U7_N16558691 DRIVER_U7_S7 \r\nD_U7_D4 U7_N16558691 VIN D_Body \r\nX_U7_U30 LSG_ON U7_N16553249 INV_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U7_U27 HSG_ON U7_ON1 U7_N16553288 NOR2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U7_S6 U7_N16560235 0 BST U7_HDRV DRIVER_U7_S6 \r\nE_U7_E1 U7_N16563264 0 BST SW 1\r\nX_U7_U20 U7_ON1 N16555426 CLK V5V U7_N16552666 0 dffsr_rhpbasic_gen\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U7_U32 U7_N16560235 U7_N16560259 INV_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2\r\nX_U7_U723 U7_BOOT_UVLO HSG_IN U7_N16560235 AND2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nV_U7_V10 U7_N16563374 0 2.2\r\nX_U7_U25 NOC_LATCH U7_N16553383 INV_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=2n\r\nX_U7_S4 LSG_IN 0 U7_N16558691 GND DRIVER_U7_S4 \r\nX_U7_U722 U7_N16563314 IC_ENABLE U7_BOOT_UVLO AND2_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nX_U7_U28 U7_N16553288 U7_N16553383 LSG_IN AND2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nX_U7_U22 U7_ON1 U7_N16553249 HSG_IN AND2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U7_U23 LSG_IN LSG_ON BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=5n\r\nX_U7_S5 U7_HDRV U7_N16558691 VIN U7_N16558691 DRIVER_U7_S5 \r\nD_U7_D6 V5V BST D_D1_BST \r\nE_ABM1 N16610660 0 VALUE { IF(V(COUNT) <64, (1.875m*V(COUNT)+0.94),\r\n+ (-1.875m*V(COUNT)+1.18)) }\r\nR_R5 N16610660 VREF_FSS_GEN 50 TC=0,0 \r\nX_U705 FB N16612714 N16612900 N16612622 COMPHYS_BASIC_GEN PARAMS: VDD=1\r\n+ VSS=0 VTHRESH=0.5\r\nV_V24 N16613349 0 {1.15*0.8}\r\nX_U710 UVP N16612818 asymmetric_delay PARAMS: RISING_EDGE_DELAY=70u\r\n+ VTHRESH=0.5 FALLING_EDGE_DELAY=1n VDD=1 VSS=0\r\nX_U835 UVP N16612818 N16612728 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+ VTHRESH=500E-3\r\nV_V4 N16610930 0 {EN_FSS}\r\nX_U830 N16610762 VREF_FSS_GEN N16610878 N16610794 MUX2_BASIC_GEN\r\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nX_S19 N16612912 0 PG GND TPS62933P_TRANS_S19 \r\nX_U713 N16612830 VIN_PGD_VALID N16612912 NOR2_BASIC_GEN PARAMS: VDD=1\r\n+ VSS=0 VTHRESH=500E-3\r\nI_U3_I1 V5V EN DC 770n \r\nX_U3_U9 U3_N16551489 U3_N16550441 U3_N16551588 U3_N16551453\r\n+ AND3_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nD_U3_D4 EN V5V D_DIDEAL \r\nX_U3_U13 U3_N16552739 U3_N16550441 BUF_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=10n\r\nV_U3_V4 U3_N16548965 0 300m\r\nX_U3_U10 IC_ENABLE IC_DISABLE INV_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nV_U3_V7 U3_N16550245 0 1.21V\r\nR_U3_R2 U3_N16550750 EN 20k TC=0,0 \r\nC_U3_C1 U3_N16550750 0 1p IC=0 TC=0,0 \r\nE_U3_ABM1 V5V 0 VALUE { LIMIT(V(VIN),5,0) }\r\nX_U3_U8 EN U3_N16550245 U3_N16550249 U3_N16552739 COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U3_U11 U3_N16551453 IC_ENABLE BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=5u\r\nX_U3_U12 U3_N16552262 U3_N16551489 BUF_DELAY_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5 DELAY=50n\r\nX_U3_U14 HICCUP_RST U3_N16551588 INV_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U3_U7 VIN U3_N16549034 U3_N16548965 U3_N16552262 COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nG_U3_G1 V5V EN U3_N16550441 0 {1.77u/5}\r\nV_U3_V5 U3_N16549034 0 2.5\r\nV_U3_V6 U3_N16550249 0 40m\r\nX_U11 CLK COUNT COUNT_RE 0 0 RST COUNTER PARAMS: MIN_PW=240n\r\n+ COUNT_RST=128\r\nV_V22 N16612900 0 {0.8*0.05}\r\nX_U712 N16612734 IC_ENABLE IC_ENABLE N16612830 AND3_BASIC_GEN PARAMS:\r\n+ VDD=1 VSS=0 VTHRESH=500E-3\r\nE_U1_E1 U1_N16548262 0 U1_VREF 0 1.5\r\nE_U1_E2 SS_INT 0 SS GND 1\r\nG_U1_ABMII1 V5V SS VALUE { IF(V(U1_SS_DISCH)< 2.5, 5.5u, 0) }\r\nX_U1_U30 HICCUP_RST U1_N16597797 INV_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+ VTHRESH=500E-3\r\nX_U1_U8 SS U1_N16548262 U1_N16548838 SS_END COMPHYS_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nX_U1_U860 U1_N16608629 SS_UNDER_0V U1_SS_DISCH N16608598\r\n+ srlatchrhp_basic_gen PARAMS: VDD=5 VSS=0 VTHRESH=0.5\r\nX_U1_U866 SS_END SS_END BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+ VTHRESH=0.5 DELAY=1u\r\nV_U1_V3 U1_N16548838 0 40m\r\nD_U1_D4 SS V5V D_DIDEAL \r\nV_U1_V6 U1_N16604821 0 15m\r\nX_U1_S4 U1_N16606234 0 SS GND SOFT_START_U1_S4 \r\nX_U1_U865 HICCUP_RST SS_END U1_N16608629 AND2_BASIC_GEN PARAMS: VDD=1\r\n+ VSS=0 VTHRESH=500E-3\r\nC_U1_C10 SS 0 13.75n IC={STEADY_STATE*0.8} TC=0,0 \r\nV_U1_V4 U1_N16548872 0 40m\r\nX_U1_U863 U1_N16597797 IC_DISABLE U1_N16606220 AND2_BASIC_GEN PARAMS:\r\n+ VDD=1 VSS=0 VTHRESH=500E-3\r\nV_U1_V7 U1_N16604869 0 2m\r\nX_U1_U7 SS U1_VREF U1_N16548872 SS_OVER_0P8 COMPHYS_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nE_U1_ABM1 VREF_EA 0 VALUE { IF(V(HICCUP_RST)>2.5, 0,\r\n+ LIMIT(V(SS_INT),VREF,0)) }\r\nV_U1_V5 U1_VREF 0 0.8\r\nX_U1_U864 U1_N16606220 U1_SS_DISCH U1_N16606234 OR2_BASIC_GEN PARAMS:\r\n+ VDD=1 VSS=0 VTHRESH=500E-3\r\nX_U1_U33 U1_N16604821 SS U1_N16604869 SS_UNDER_0V COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nR_R4 N16610794 VREF_FSS2 10 TC=0,0 \r\nV_V25 N16613397 0 {0.8*0.05}\r\nV_V7 N16610762 0 1\r\nX_U834 N16612622 SS_OVER_0P8 N16613565 UVP AND3_BASIC_GEN PARAMS: VDD=1\r\n+ VSS=0 VTHRESH=500E-3\r\nG_U4_G1 U4_N16555613 U4_N16556061 IFOLD_TOFF 0 1m\r\nX_U4_S5 U4_N16555929 0 U4_N16555741 0 OFF_TIME_U4_S5 \r\nR_U4_R2 U4_N16555745 U4_N16555617 {0.25*2Meg} TC=0,0 \r\nX_U4_U15 U4_N16555613 U4_N16555617 U4_N165556333 U4_N16555673\r\n+ COMPHYS_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U4_U24 TOFF TOFF_B INV_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U4_U21 ZC_NOC U4_FCCM U4_N16552718 AND2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U4_U202 U4_FCCM U4_PSM INV_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=1n\r\nD_U4_D4 0 U4_N16555613 D_DIDEAL2 \r\nR_U4_R6 U4_N16556069 IFOLD_TOFF 1k TC=0,0 \r\nR_U4_R7 0 U4_N16556069 4K TC=0,0 \r\nC_U4_C1 U4_N16555741 0 500f IC=0 \r\nX_U4_U26 TOFF_EN U4_N16555929 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+ VTHRESH=0.5 DELAY=2p\r\nX_U4_U201 SS_OVER_0P8 U4_N16599779 U4_FCCM_SEND AND2_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nX_U4_U22 FFWD FFWD_ONESHOT BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=20n\r\nR_U4_R4 0 U4_N16555745 {0.65*2Meg} TC=0,0 \r\nX_U4_U20 FFWD N16557004 U4_N16552718 V5V FFWD_ONESHOT 0\r\n+ dffsr_rhpbasic_gen PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nV_U4_V9 U4_N16599779 0 {EN_FCCM*5}\r\nR_U4_R5 0 U4_N16556061 1k TC=0,0 \r\nI_U4_I3 V5V U4_N16555613 DC 250n \r\nX_U4_S4 U4_FCCM 0 U4_N16555745 0 OFF_TIME_U4_S4 \r\nV_U4_V7 U4_N165556333 0 1m\r\nI_U4_I4 V5V U4_N16555617 DC 250n \r\nE_U4_E1 U4_FCCM 0 U4_FCCM_SEND 0 1\r\nX_U4_U25 U4_N16555673 TOFF BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=200n\r\nX_U4_S6 U4_FCCM 0 U4_N16556069 0 OFF_TIME_U4_S6 \r\nR_U4_R3 U4_N16555741 U4_N16555613 2Meg TC=0,0 \r\nX_U831 SS_END N16610930 N16610878 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0\r\n+ VTHRESH=500E-3\r\nC_C7 0 VREF_FSS_GEN 1.443n TC=0,0 \r\nX_U8_U8 U8_N16554205 U8_RAMP_OK BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=2n\r\nX_U8_F2 V5V U8_N16553899 V5V U8_N16554772 OSCILLATOR_U8_F2 \r\nC_U8_C6 0 U8_VREF_FSS 1.443n TC=0,0 \r\nX_U8_U830 U8_N16602215 U8_N16602297 U8_N16602373 U8_N16602247\r\n+ MUX2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\r\nR_U8_R8 U8_N16605173 U8_N16605474 1 TC=0,0 \r\nR_U8_R7 RT GND 100G TC=0,0 \r\nV_U8_V5 U8_N16554217 0 50m\r\nD_U8_D5 U8_N16553991 V5V D_DIDEAL \r\nX_U8_U9 U8_RAMP_OK U8_N16555029 INV_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U8_U831 SS_END U8_N16602439 U8_N16602373 AND2_BASIC_GEN PARAMS: VDD=1\r\n+ VSS=0 VTHRESH=500E-3\r\nX_U8_U20 U8_N16562262 CLK asymmetric_delay PARAMS: RISING_EDGE_DELAY=1n\r\n+ VTHRESH=2.5 FALLING_EDGE_DELAY=10n VDD=5 VSS=0\r\nC_U8_C1 CLK_RAMP 0 4.5p IC=0 TC=0,0 \r\nX_U8_U17 FFWD U8_N16562246 U8_N16562262 OR2_BASIC_GEN PARAMS: VDD=5\r\n+ VSS=0 VTHRESH=2.5\r\nX_U8_F3 U8_N16605474 RT 0 U8_N16606756 OSCILLATOR_U8_F3 \r\nX_U8_U16 CLK U8_N16555239 INV_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5 DELAY=1n\r\nG_U8_ABMII1 U8_N16553899 U8_N16553991 VALUE {\r\n+ IF(V(U8_N16606756)<1.785u, 11.26u*0.2, IF(V(U8_N16606756)<500u,\r\n+ V(U8_N16606756)*0.2, 28u*0.2)) }\r\nR_U8_R4 U8_N16602247 U8_VREF_FSS 10 TC=0,0 \r\nX_U8_U10 IC_ENABLE U8_N16555239 U8_N16555296 NAND2_BASIC_GEN PARAMS:\r\n+ VDD=5 VSS=0 VTHRESH=2.5\r\nX_U8_S5 U8_N16555296 0 CLK_RAMP 0 OSCILLATOR_U8_S5 \r\nV_U8_V2 U8_N16602297 0 \r\n+PULSE 0.94 1.06 1u 126u 126u 2u 256u\r\nV_U8_V4 U8_N16602439 0 {EN_FSS}\r\nR_U8_R6 U8_N16606756 0 1 TC=0,0 \r\nV_U8_V10 U8_N16556925 0 5\r\nX_U8_U18 CONT RAMP_OK_LATCH TOFF_EN AND2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nX_U8_S4 U8_N16555029 0 U8_N16553991 CLK_RAMP OSCILLATOR_U8_S4 \r\nX_U8_S6 U8_RAMP_OK 0 U8_N16554772 CLK_RAMP OSCILLATOR_U8_S6 \r\nX_U8_U7 CLK_RAMP VREF_FSS2 U8_N16554217 U8_N16554205 COMPHYS_BASIC_GEN\r\n+ PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nV_U8_V7 U8_N16602215 0 1\r\nD_U8_D4 U8_N16554772 V5V D_DIDEAL \r\nX_U8_U15 RAMP_OK_LATCH N16556929 U8_RAMP_OK V5V U8_N16555239\r\n+ U8_N16556925 dffsbrb_shpbasic_gen PARAMS: VDD=5 VSS=0 VTHRESH=2.5\r\nX_U8_U19 TOFF TOFF_EN U8_N16562246 AND2_BASIC_GEN PARAMS: VDD=5 VSS=0\r\n+ VTHRESH=2.5\r\nV_U8_V11 U8_N16605173 GND 0.5\r\nR_U2_R5 U2_VREF_INNER VREF_EA 200k TC=0,0 \r\nC_U2_C3 U2_VREF_INNER 0 100f IC={STEADY_STATE*0.8} \r\nV_U2_V5 U2_N16548563 0 {0.6+7.5m}\r\nG_U2_G2 0 U2_IFOLD_FCCM COMP 0 40u\r\nC_U2_Cea U2_EA_OUT 0 1p IC=0 \r\nG_U2_ABM2I5 U2_N16551838 IPRESET VALUE { LIMIT(({(V(U2_N16550130)\r\n+ -V(COMP))*gain_adder}),GmadderMax,0) }\r\nE_U2_ABM4 ISET 0 VALUE { LIMIT({V(IPRESET) *4.4},5.5,0) }\r\nV_U2_V3 U2_N16545963 0 0.6\r\nX_U2_F1 U2_N16549043 U2_N16549036 0 IFOLD_TOFF ERROR_AMPLIFIER_U2_F1 \r\nE_U2_ABM5 IVALLEY 0 VALUE { LIMIT({V(U2_IFOLD_FCCM) *6.3},3.8,{NOC}) \r\n+ }\r\nG_U2_ABM2I3 U2_N16549036 U2_EA_OUT VALUE { LIMIT(({(V(U2_N16548563)\r\n+ -V(U2_EA_OUT))*643u}),200u,1n) }\r\nR_U2_R6 U2_N16544099 FB_INT 200k TC=0,0 \r\nE_U2_E1 U2_N16546427 0 COMP 0 {1/4}\r\nR_U2_Rc U2_EA_OUT U2_N16545877 600k TC=0,0 \r\nG_U2_G1 U2_N16551838 IPRESET COMP 0 40u\r\nR_U2_R11 U2_IPEAK_TEST 0 {25k*4.4} TC=0,0 \r\nR_U2_R7 0 FB_INT 1T TC=0,0 \r\nV_U2_V4 U2_N16548222 0 1.136\r\nE_U2_ABM2 COMP 0 VALUE { LIMIT(({V(U2_EA_OUT) -V(U2_N16545963)}),1.5,0)\r\n+ }\r\nX_U2_H2 0 U2_N16551838 U2_IPEAK_TEST 0 ERROR_AMPLIFIER_U2_H2 \r\nG_U2_ABM2I4 U2_EA_OUT 0 VALUE { LIMIT(({(V(COMP)\r\n+ -V(U2_N16548222))*100u}),50u,0) }\r\nX_U2_F2 0 U2_N16549043 0 U2_IFOLD_FCCM ERROR_AMPLIFIER_U2_F2 \r\nR_U2_RVI1 U2_IFOLD_FCCM 0 25k TC=0,0 \r\nC_U2_Cc U2_N16545877 0 25p IC=0 \r\nG_U2_ABM2I1 0 U2_EA_OUT VALUE { LIMIT(({(V(U2_VREF_INNER)\r\n+ -V(U2_N16544099))*19u}),1.8u,-1.8u) }\r\nR_U2_R4 0 VREF_EA 1T TC=0,0 \r\nR_U2_RVI IPRESET 0 25k TC=0,0 \r\nG_U2_ABM2I2 U2_EA_OUT 0 VALUE { LIMIT(({(V(U2_N16546427)\r\n+ -V(VREF_EA))*100u}),30u,-1n) }\r\nR_U2_Rea U2_EA_OUT 0 5.26G TC=0,0 \r\nC_U2_C2 U2_N16544099 0 100f IC=0 \r\nV_U2_V6 U2_N16550130 0 0.1\r\n.ENDS TPS62933P_TRANS\r\n*$\r\n.PARAM vref=0.8 noc={2.8*en_fccm+1.5*ooa_en} ilpeakcomp0=0.74 rvi=25k\r\n+ en_fccm=0 gmadder={(ilpeakcomp0)/vcompvalley/rvi/gps_peak} gain_adder=\r\n+ {gmadder*(1-en_fccm)} gps_peak=4.4 vcompvalley=0.1 gmaddermax=\r\n+ {gmadder*vcompvalley} ooa_en=0\r\n*$\r\n.subckt SLOPE_COMP_U9_F1 1 2 3 4 \r\nF_U9_F1 3 4 VF_U9_F1 1\r\nVF_U9_F1 1 2 0V\r\n.ends SLOPE_COMP_U9_F1\r\n*$\r\n.subckt SLOPE_COMP_U9_S5 1 2 3 4 \r\nS_U9_S5 3 4 1 2 _U9_S5\r\nRS_U9_S5 1 2 1G\r\n.MODEL _U9_S5 VSWITCH Roff=10G Ron=100 Voff=1.9 Von=2\r\n.ends SLOPE_COMP_U9_S5\r\n*$\r\n.subckt SLOPE_COMP_U9_S7 1 2 3 4 \r\nS_U9_S7 3 4 1 2 _U9_S7\r\nRS_U9_S7 1 2 1G\r\n.MODEL _U9_S7 VSWITCH Roff=10G Ron=1m Voff=1.9 Von=2\r\n.ends SLOPE_COMP_U9_S7\r\n*$\r\n.subckt SLOPE_COMP_U9_S4 1 2 3 4 \r\nS_U9_S4 3 4 1 2 _U9_S4\r\nRS_U9_S4 1 2 1G\r\n.MODEL _U9_S4 VSWITCH Roff=10G Ron=100m Voff=1.9 Von=2\r\n.ends SLOPE_COMP_U9_S4\r\n*$\r\n.subckt SLOPE_COMP_U9_S6 1 2 3 4 \r\nS_U9_S6 3 4 1 2 _U9_S6\r\nRS_U9_S6 1 2 1G\r\n.MODEL _U9_S6 VSWITCH Roff=10G Ron=100m Voff=1.9 Von=2\r\n.ends SLOPE_COMP_U9_S6\r\n*$\r\n.subckt DRIVER_U7_H1 1 2 3 4 \r\nH_U7_H1 3 4 VH_U7_H1 1\r\nVH_U7_H1 1 2 0V\r\n.ends DRIVER_U7_H1\r\n*$\r\n.subckt DRIVER_U7_S7 1 2 3 4 \r\nS_U7_S7 3 4 1 2 _U7_S7\r\nRS_U7_S7 1 2 1G\r\n.MODEL _U7_S7 VSWITCH Roff=10G Ron=1m Voff=1.9 Von=4\r\n.ends DRIVER_U7_S7\r\n*$\r\n.subckt DRIVER_U7_S6 1 2 3 4 \r\nS_U7_S6 3 4 1 2 _U7_S6\r\nRS_U7_S6 1 2 1G\r\n.MODEL _U7_S6 VSWITCH Roff=10G Ron=1m Voff=1.9 Von=4\r\n.ends DRIVER_U7_S6\r\n*$\r\n.subckt DRIVER_U7_S4 1 2 3 4 \r\nS_U7_S4 3 4 1 2 _U7_S4\r\nRS_U7_S4 1 2 1G\r\n.MODEL _U7_S4 VSWITCH Roff=10Meg Ron=28.1m Voff=1.9 Von=2\r\n.ends DRIVER_U7_S4\r\n*$\r\n.subckt DRIVER_U7_S5 1 2 3 4 \r\nS_U7_S5 3 4 1 2 _U7_S5\r\nRS_U7_S5 1 2 1G\r\n.MODEL _U7_S5 VSWITCH Roff=10Meg Ron=75m Voff=1.9 Von=2\r\n.ends DRIVER_U7_S5\r\n*$\r\n.subckt TPS62933P_TRANS_S19 1 2 3 4 \r\nS_S19 3 4 1 2 _S19\r\nRS_S19 1 2 1G\r\n.MODEL _S19 VSWITCH Roff=5.5e6 Ron=1.375k Voff=0.2 Von=0.8\r\n.ends TPS62933P_TRANS_S19\r\n*$\r\n.subckt SOFT_START_U1_S4 1 2 3 4 \r\nS_U1_S4 3 4 1 2 _U1_S4\r\nRS_U1_S4 1 2 1G\r\n.MODEL _U1_S4 VSWITCH Roff=10G Ron=15k Voff=0.2 Von=0.8\r\n.ends SOFT_START_U1_S4\r\n*$\r\n.subckt OFF_TIME_U4_S5 1 2 3 4 \r\nS_U4_S5 3 4 1 2 _U4_S5\r\nRS_U4_S5 1 2 1G\r\n.MODEL _U4_S5 VSWITCH Roff=1G Ron=1 Voff=1.9 Von=2\r\n.ends OFF_TIME_U4_S5\r\n*$\r\n.subckt OFF_TIME_U4_S4 1 2 3 4 \r\nS_U4_S4 3 4 1 2 _U4_S4\r\nRS_U4_S4 1 2 1G\r\n.MODEL _U4_S4 VSWITCH Roff=1G Ron=1 Voff=1.9 Von=2\r\n.ends OFF_TIME_U4_S4\r\n*$\r\n.subckt OFF_TIME_U4_S6 1 2 3 4 \r\nS_U4_S6 3 4 1 2 _U4_S6\r\nRS_U4_S6 1 2 1G\r\n.MODEL _U4_S6 VSWITCH Roff=10G Ron=1 Voff=1.9 Von=2\r\n.ends OFF_TIME_U4_S6\r\n*$\r\n.subckt OSCILLATOR_U8_F2 1 2 3 4 \r\nF_U8_F2 3 4 VF_U8_F2 100m\r\nVF_U8_F2 1 2 0V\r\n.ends OSCILLATOR_U8_F2\r\n*$\r\n.subckt OSCILLATOR_U8_F3 1 2 3 4 \r\nF_U8_F3 3 4 VF_U8_F3 1\r\nVF_U8_F3 1 2 0V\r\n.ends OSCILLATOR_U8_F3\r\n*$\r\n.subckt OSCILLATOR_U8_S5 1 2 3 4 \r\nS_U8_S5 3 4 1 2 _U8_S5\r\nRS_U8_S5 1 2 1G\r\n.MODEL _U8_S5 VSWITCH Roff=1G Ron=100m Voff=1.9 Von=2\r\n.ends OSCILLATOR_U8_S5\r\n*$\r\n.subckt OSCILLATOR_U8_S4 1 2 3 4 \r\nS_U8_S4 3 4 1 2 _U8_S4\r\nRS_U8_S4 1 2 1G\r\n.MODEL _U8_S4 VSWITCH Roff=100Meg Ron=100m Voff=1.9 Von=2\r\n.ends OSCILLATOR_U8_S4\r\n*$\r\n.subckt OSCILLATOR_U8_S6 1 2 3 4 \r\nS_U8_S6 3 4 1 2 _U8_S6\r\nRS_U8_S6 1 2 1G\r\n.MODEL _U8_S6 VSWITCH Roff=100Meg Ron=100m Voff=1.9 Von=2\r\n.ends OSCILLATOR_U8_S6\r\n*$\r\n.subckt ERROR_AMPLIFIER_U2_F1 1 2 3 4 \r\nF_U2_F1 3 4 VF_U2_F1 1\r\nVF_U2_F1 1 2 0V\r\n.ends ERROR_AMPLIFIER_U2_F1\r\n*$\r\n.subckt ERROR_AMPLIFIER_U2_H2 1 2 3 4 \r\nH_U2_H2 3 4 VH_U2_H2 -1\r\nVH_U2_H2 1 2 0V\r\n.ends ERROR_AMPLIFIER_U2_H2\r\n*$\r\n.subckt ERROR_AMPLIFIER_U2_F2 1 2 3 4 \r\nF_U2_F2 3 4 VF_U2_F2 {-10*NOC}\r\nVF_U2_F2 1 2 0V\r\n.ends ERROR_AMPLIFIER_U2_F2\r\n*$\r\n.model D_DIDEAL d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=0.001\r\n+ n=0.001\r\n*$\r\n.subckt srlatchrhp_basic_gen s r q qb params: vdd=1 vss=0 vthresh=0.5 \r\ngq 0 qint value = {if(v(r) > {vthresh},-5,if(v(s)>{vthresh},5, 0))}\r\ncqint qint 0 1n\r\nrqint qint 0 1000meg\r\nd_d10 qint my5 d_d1\r\nv1 my5 0 {vdd}\r\nd_d11 myvss qint d_d1\r\nv2 myvss 0 {vss} \r\neq qqq 0 qint 0 1\r\nx3 qqq qqqd1 buf_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}\r\nrqq qqqd1 q 1\r\neqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}\r\nrqb qbr qb 1 \r\ncdummy1 q 0 1n \r\ncdummy2 qb 0 1n\r\n.ic v(qint) {vss}\r\n.model d_d1 d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=0.05\r\n+ n=0.01\r\n.ends srlatchrhp_basic_gen\r\n*$\r\n.subckt dffsr_rhpbasic_gen q qb clk d r s params: vdd=1 vss=0 vthresh=0.5 \r\nx1 clk clkdel inv_delay_basic_gen params: vdd={vdd} vss={vss} vthresh=\r\n+ {vthresh} delay = 15n\r\nx2 clk clkdel clkint and2_basic_gen params: vdd={vdd} vss={vss} vthresh=\r\n+ {vthresh} \r\ngq 0 qint value = {if(v(r) > {vthresh},-5,if(v(s) > {vthresh},5, if(v(clkint)>\r\n+ {vthresh}, \r\n+ if(v(d)> {vthresh},5,-5),0)))}\r\ncqint qint 0 1n\r\nrqint qint 0 1000meg\r\nd_d10 qint my5 d_d1\r\nv1 my5 0 {vdd}\r\nd_d11 myvss qint d_d1\r\nv2 myvss 0 {vss} \r\neq qqq 0 qint 0 1\r\nx3 qqq qqqd1 buf_delay_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}\r\n+ delay = 20n\r\nrqq qqqd1 q 1\r\neqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}\r\nrqb qbr qb 1 \r\ncdummy1 q 0 1nf \r\ncdummy2 qb 0 1nf \r\n.ic v(qint) {vss}\r\n.model d_d1 d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=0.05\r\n+ n=0.01\r\n.ends dffsr_rhpbasic_gen\r\n*$\r\n.subckt asymmetric_delay inp out params: rising_edge_delay=1 vthresh=0.5\r\n+ falling_edge_delay=1 vdd=1 vss=0\r\ne_abm3 inp1 0 value { if(v(inp) > {vthresh}, {vdd} , {vss}) }\r\ne_abm1 yin4 0 value { if(v(yin3) > {vthresh}, {vdd} , {vss}) }\r\ne_abm2 yin2 0 value { if(v(yin1) > {vthresh}, {vdd} , {vss}) }\r\nr_rint inp1 yin1 1 \r\nc_cint yin1 0 {1.443*rising_edge_delay} \r\nd_d10 yin1 inp1 d_d1\r\nr_r1 yin4 out 1 \r\nr_rout yin2 yin3 1 \r\nc_cout yin3 0 {1.443*falling_edge_delay} \r\nc_c1 0 out 1n \r\nd_d11 yin2 yin3 d_d1\r\n.model d_d1 d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=0.005\r\n+ n=0.1\r\n.ends asymmetric_delay\r\n*$\r\n.model D_DIDEAL2 d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=1.36621\r\n+ n=0.001\r\n*$\r\n.model D_Body d\r\n+ is=1e-15\r\n+ n=1\r\n+ rs=0.01\r\n+ tt=1e-11\r\n*$\r\n.model D_D1_BST d\r\n+ is=1e-15\r\n+ n=0.1\r\n+ tt=1e-11\r\n*$\r\n.subckt dffsbrb_rhpbasic_gen q qb clk d rb sb params: vdd=1 vss=0 vthresh=0.5 \r\nx1 clk clkdel inv_delay_basic_gen params: vdd={vdd} vss={vss} vthresh=\r\n+ {vthresh} delay = 15n\r\nx2 clk clkdel clkint and2_basic_gen params: vdd={vdd} vss={vss} vthresh=\r\n+ {vthresh} \r\ngq 0 qint value = {if(v(rb) < {vthresh},-5,if(v(sb)< {vthresh},5,\r\n+ if(v(clkint)> {vthresh}, \r\n+ if(v(d)> {vthresh},5,-5),0)))}\r\ncqint qint 0 1n\r\nrqint qint 0 1000meg\r\nd_d10 qint my5 d_d1\r\nv1 my5 0 5\r\nd_d11 0 qint d_d1 \r\neq qqq 0 qint 0 1\r\nx3 qqq qqqd1 buf_delay_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}\r\n+ delay = 20n\r\nrqq qqqd1 q 1\r\neqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}\r\nrqb qbr qb 1 \r\ncdummy1 q 0 1nf \r\ncdummy2 qb 0 1nf \r\n.ic v(qint) {vss}\r\n.model d_d1 d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=0.05\r\n+ n=0.01\r\n.ends dffsbrb_rhpbasic_gen\r\n*$\r\n.subckt dffsbrb_shpbasic_gen q qb clk d rb sb params: vdd=1 vss=0 vthresh=0.5 \r\nx1 clk clkdel inv_delay_basic_gen params: vdd={vdd} vss={vss} vthresh=\r\n+ {vthresh} delay = 15n\r\nx2 clk clkdel clkint and2_basic_gen params: vdd={vdd} vss={vss} vthresh=\r\n+ {vthresh}\r\ngq 0 qint value = {if(v(sb) < {vthresh},5,if(v(rb)<{vthresh},-5, if(v(clkint)>\r\n+ {vthresh}, \r\n+ if(v(d)> {vthresh},5,-5),0)))}\r\ncqint qint 0 1n\r\nrqint qint 0 1000meg\r\nd_d10 qint my5 d_d1\r\nv1 my5 0 {vdd}\r\nd_d11 myvss qint d_d1\r\nv2 myvss 0 {vss} \r\neq qqq 0 qint 0 1\r\nx3 qqq qqqd1 buf_delay_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}\r\n+ delay = 20n\r\nrqq qqqd1 q 1\r\neqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}\r\nrqb qbr qb 1 \r\ncdummy1 q 0 1nf \r\ncdummy2 qb 0 1nf \r\n.ic v(qint) {vss}\r\n.model d_d1 d\r\n+ is=1e-15\r\n+ tt=1e-11\r\n+ rs=0.05\r\n+ n=0.01\r\n.ends dffsbrb_shpbasic_gen\r\n*$\r\n.subckt one_shot in out params: t=100\r\ns_s1 meas 0 reset2 0 s1\r\ne_abm1 ch 0 value { if( v(in)>0.5 | v(out)>0.5,1,0) }\r\nr_r2 reset2 reset 0.1 \r\ne_abm3 out 0 value { if( v(meas)<0.5 & v(ch)>0.5,1,0) }\r\nr_r1 meas ch {t} \r\nc_c2 0 reset2 1.4427n \r\nc_c1 0 meas 1.4427n \r\ne_abm2 reset 0 value { if(v(ch)<0.5,1,0) }\r\n.model s1 vswitch\r\n+ roff=1e+09\r\n+ ron=1\r\n+ voff=0.25\r\n+ von=0.75\r\n.ends one_shot\r\n*$\r\n.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\r\nEIN INP1 INM1 INP INM 1 \r\nEHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }\r\nEOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }\r\nR1 OUT 1 1\r\nC1 1 0 5n\r\nRINP1 INP1 0 1K\r\n.ENDS COMPHYS_BASIC_GEN\r\n*$\r\n.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \r\n+ V(B) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS NAND2_BASIC_GEN\r\n*$\r\n.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS INV_BASIC_GEN\r\n*$\r\n.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \r\nE_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT YINT1 YINT2 1\r\nCINT YINT2 0 {DELAY*1.443}\r\nE_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \r\n+ {VSS},{VDD})}}\r\nRINT2 YINT3 Y 1\r\nCINT2 Y 0 1n\r\n.ENDS INV_DELAY_BASIC_GEN\r\n*$\r\n.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \r\n+ V(B) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS AND2_BASIC_GEN\r\n*$\r\n.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \r\n+ V(B) > {VTHRESH} &\r\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS AND3_BASIC_GEN\r\n*$\r\n.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \r\n+ V(B) > {VTHRESH},{VSS},{VDD})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS NOR2_BASIC_GEN\r\n*$\r\n.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \r\n+ V(B) > {VTHRESH},{VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS OR2_BASIC_GEN\r\n*$\r\n.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS BUF_BASIC_GEN\r\n*$\r\n.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \r\nE_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT YINT1 YINT2 1\r\nCINT YINT2 0 {DELAY*1.443}\r\nE_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \r\n+ {VDD},{VSS})}}\r\nRINT2 YINT3 Y 1\r\nCINT2 Y 0 1n\r\n.ENDS BUF_DELAY_BASIC_GEN\r\n*$\r\n.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\r\nE_ABM Yint 0 VALUE {IF (V(INP) > \r\n+ V(INM), {VDD},{VSS})}\r\nR1 Yint Y 1\r\nC1 Y 0 1n\r\n.ENDS COMP_BASIC_GEN\r\n*$\r\n.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \r\nE_ABMGATE YINT 0 VALUE {{IF(V(S) > {VTHRESH}, \r\n+ V(B),V(A))}}\r\nRINT YINT Y 1\r\nCINT Y 0 1n\r\n.ENDS MUX2_BASIC_GEN\r\n*$\r\n.SUBCKT Counter CLK COUNT_FE COUNT_RE GND RESET RST_INT PARAMS: min_pw=10n count_rst=128 \r\nR_R4 N16838390 N16838391 {MIN_PW/2} \r\nR_R5 N16842332 CLKRE 1 \r\nC_C5 GND CLKRE 1n \r\nR_R3 RST_INT N16832011 1 \r\nE_ABM4 N16813271 0 VALUE { IF(V(RESET)>0.5 |\r\n+ V(RST_INT)>0.5,0,IF(V(CLKRE)>0.55,V(COUNT_FE)+1,V(COUNT_RE))) }\r\nR_R6 N168433471 CLKI 1 \r\nE_ABM6 N16832011 0 VALUE { if(v(COUNT_RE) < 10m,0,if(v(COUNT_FE)>\r\n+ {COUNT_RST}-0.1,1, V(RST_INT))) }\r\nC_C1 GND COUNT_RE_INT 1n IC=0 \r\nC_C6 GND CLKI 1n \r\nC_C3 GND RST_INT 1n IC=0 \r\nE_ABM10 N168433471 0 VALUE { IF(V(CLK)<0.5,1,0) }\r\nR_R1 COUNT_FE_INT N33733 1 \r\nE_ABM8 N16840706 0 VALUE { IF(V(RST_INT)<0.5,1,0) }\r\nC_C4 GND N16838391 1.443n \r\nE_E4 COUNT_RE GND COUNT_RE_INT GND 1\r\nR_R2 COUNT_RE_INT N16813271 1 \r\nE_ABM2 N33733 0 VALUE { IF(V(RESET)>0.5 |\r\n+ V(RST_INT)>0.5,0,IF(V(CLKI)>0.55,V(COUNT_RE_INT),V(COUNT_FE))) }\r\nE_E3 COUNT_FE GND COUNT_FE_INT GND 1\r\nC_C2 GND COUNT_FE_INT 1n IC=0 \r\nE_ABM7 N16838390 0 VALUE { IF(V(CLK)<0.5,1,0) }\r\nE_ABM9 N16842332 0 VALUE { IF(V(N16838391)>0.5,0,IF(V(CLK)>0.5 &\r\n+ V(N16840706)>0.5,1,0)) }\r\n.ENDS Counter\r\n*$\r\n.SUBCKT CESR IN OUT\r\n+ PARAMS: C=100u ESR=0.01 X=1 IC=0 ESL=0\r\nC\tIN 1 {C*X} IC={IC}\r\nRESR\t1 OUT {ESR/X}\r\n.ENDS CESR\r\n*$\r\n.SUBCKT LDCR IN OUT\r\n+ PARAMS: L=1u DCR=0.01 IC=0\r\nL\tIN 1 {L} IC={IC}\r\nRDCR\t1 OUT {DCR}\r\n.ENDS LDCR\r\n*quot;
}