tscircuit/ti

ti tscircuit library

Version
1.0.85
License
unset
Stars
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dist/lib/subcircuits/LoadSwitch_TPS22919/circuit.json

PCBPCB preview for dist/lib/subcircuits/LoadSwitch_TPS22919/circuit.json
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[
  {
    "type": "source_group",
    "source_group_id": "source_group_0",
    "is_subcircuit": true,
    "was_automatically_named": true,
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_0",
    "name": "IN",
    "pin_number": 1,
    "port_hints": [
      "IN",
      "pin1",
      "1"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_1",
    "name": "GND",
    "pin_number": 2,
    "port_hints": [
      "GND",
      "pin2",
      "2"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_2",
    "name": "ON",
    "pin_number": 3,
    "port_hints": [
      "ON",
      "pin3",
      "3"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_3",
    "name": "NC",
    "pin_number": 4,
    "port_hints": [
      "NC",
      "pin4",
      "4"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_4",
    "name": "QOD",
    "pin_number": 5,
    "port_hints": [
      "QOD",
      "pin5",
      "5"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_5",
    "name": "OUT",
    "pin_number": 6,
    "port_hints": [
      "OUT",
      "pin6",
      "6"
    ],
    "source_component_id": "source_component_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_0",
    "ftype": "simple_chip",
    "name": "U1",
    "manufacturer_part_number": "TPS22919DCKR",
    "supplier_part_numbers": {
      "jlcpcb": [
        "C2149796"
      ]
    },
    "source_group_id": "source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_6",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "terminal1",
      "1",
      "left"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_7",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "terminal2",
      "2",
      "right"
    ],
    "source_component_id": "source_component_1",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_1",
    "ftype": "simple_voltage_source",
    "name": "V_IN",
    "voltage": 5,
    "supplier_part_numbers": {},
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_8",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_2",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_9",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_2",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_2",
    "ftype": "simple_capacitor",
    "name": "C_IN",
    "supplier_part_numbers": {
      "jlcpcb": [
        "C52923",
        "C14445",
        "C29266"
      ]
    },
    "capacitance": 0.000001,
    "display_capacitance": "1uF",
    "are_pins_interchangeable": false,
    "source_group_id": "source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_10",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "anode",
      "pos",
      "left",
      "1"
    ],
    "source_component_id": "source_component_3",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_11",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "cathode",
      "neg",
      "right",
      "2"
    ],
    "source_component_id": "source_component_3",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_3",
    "ftype": "simple_resistor",
    "name": "R_QOD",
    "supplier_part_numbers": {
      "jlcpcb": [
        "C25741",
        "C60491",
        "C2906859"
      ]
    },
    "resistance": 100000,
    "display_resistance": "100kΩ",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_12",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "neg",
      "cathode",
      "2",
      "right"
    ],
    "source_component_id": "source_component_4",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_13",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "pos",
      "anode",
      "1",
      "left"
    ],
    "source_component_id": "source_component_4",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_4",
    "ftype": "simple_capacitor",
    "name": "C_L",
    "supplier_part_numbers": {
      "jlcpcb": [
        "C19702",
        "C96446",
        "C1691"
      ]
    },
    "capacitance": 0.00001,
    "display_capacitance": "10uF",
    "are_pins_interchangeable": false,
    "source_group_id": "source_group_0"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_14",
    "name": "pin1",
    "pin_number": 1,
    "port_hints": [
      "pin1",
      "anode",
      "pos",
      "left",
      "1"
    ],
    "source_component_id": "source_component_5",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_port",
    "source_port_id": "source_port_15",
    "name": "pin2",
    "pin_number": 2,
    "port_hints": [
      "pin2",
      "cathode",
      "neg",
      "right",
      "2"
    ],
    "source_component_id": "source_component_5",
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_component",
    "source_component_id": "source_component_5",
    "ftype": "simple_resistor",
    "name": "R_L",
    "supplier_part_numbers": {
      "jlcpcb": [
        "C25744",
        "C60490",
        "C25531"
      ]
    },
    "resistance": 10000,
    "display_resistance": "10kΩ",
    "are_pins_interchangeable": true,
    "source_group_id": "source_group_0"
  },
  {
    "type": "source_net",
    "source_net_id": "source_net_0",
    "name": "GND",
    "member_source_group_ids": [],
    "is_ground": true,
    "is_power": false,
    "is_positive_voltage_source": false,
    "subcircuit_id": "subcircuit_source_group_0",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_0",
    "connected_source_port_ids": [
      "source_port_7",
      "source_port_0"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": ".V_IN > .pin2 to U1.pin1",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_0",
    "message": "<trace#21843(from:.V_IN > .pin2 to:U1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_0",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_1",
    "connected_source_port_ids": [
      "source_port_6"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": ".V_IN > .pin1 to net.GND",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_1",
    "message": "<trace#21844(from:.V_IN > .pin1 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_1",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_2",
    "connected_source_port_ids": [
      "source_port_9",
      "source_port_0"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_0",
    "max_length": null,
    "display_name": ".C_IN > .pos to U1.pin1",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_2",
    "message": "<trace#21845(from:.C_IN > .pos to:U1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_2",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_3",
    "connected_source_port_ids": [
      "source_port_8"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_0",
    "max_length": null,
    "display_name": ".C_IN > .pin2 to net.GND",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_3",
    "message": "<trace#21846(from:.C_IN > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_3",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_4",
    "connected_source_port_ids": [
      "source_port_10",
      "source_port_4"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": ".R_QOD > .pin1 to U1.QOD",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_4",
    "message": "<trace#21847(from:.R_QOD > .pin1 to:U1.QOD) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_4",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_5",
    "connected_source_port_ids": [
      "source_port_11",
      "source_port_5"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": ".R_QOD > .pin2 to U1.OUT",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_5",
    "message": "<trace#21848(from:.R_QOD > .pin2 to:U1.OUT) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_5",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_6",
    "connected_source_port_ids": [
      "source_port_13",
      "source_port_5"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_0",
    "max_length": null,
    "display_name": ".C_L > .pos to U1.OUT",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_6",
    "message": "<trace#21849(from:.C_L > .pos to:U1.OUT) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_6",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_7",
    "connected_source_port_ids": [
      "source_port_12"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_0",
    "max_length": null,
    "display_name": ".C_L > .pin2 to net.GND",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_7",
    "message": "<trace#21850(from:.C_L > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_7",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_8",
    "connected_source_port_ids": [
      "source_port_15",
      "source_port_5"
    ],
    "connected_source_net_ids": [],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": ".R_L > .pin2 to U1.OUT",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_8",
    "message": "<trace#21851(from:.R_L > .pin2 to:U1.OUT) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_8",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_9",
    "connected_source_port_ids": [
      "source_port_14"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": ".R_L > .pin1 to net.GND",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_9",
    "message": "<trace#21852(from:.R_L > .pin1 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_9",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "source_trace",
    "source_trace_id": "source_trace_10",
    "connected_source_port_ids": [
      "source_port_1"
    ],
    "connected_source_net_ids": [
      "source_net_0"
    ],
    "subcircuit_id": "subcircuit_source_group_0",
    "display_name": "U1.GND to net.GND",
    "subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
  },
  {
    "type": "source_unnamed_trace_warning",
    "source_unnamed_trace_warning_id": "source_unnamed_trace_warning_10",
    "message": "<trace#21791(from:U1.GND to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
    "source_trace_id": "source_trace_10",
    "subcircuit_id": "subcircuit_source_group_0",
    "warning_type": "source_unnamed_trace_warning"
  },
  {
    "type": "simulation_spice_subcircuit",
    "simulation_spice_subcircuit_id": "simulation_spice_subcircuit_0",
    "source_component_id": "source_component_0",
    "spice_pin_to_source_port_map": {
      "GND": "source_port_1",
      "ON": "source_port_2",
      "QOD": "source_port_4",
      "VIN": "source_port_0",
      "VOUT": "source_port_5"
    },
    "subcircuit_source": "*$ TPS22919\n*****************************************************************************\n*  (C) Copyright 2018 Texas Instruments Incorporated. All rights reserved.\n***********************************************************************\n** This model is designed as an aid for customers of Texas Instruments.\n** TI and its licensors and suppliers make no warranties, either expressed\n** or implied, with respect to this model, including the warranties of\n** merchantability or fitness for a particular purpose. The model is\n** provided solely on an \"as is\" basis. The entire risk as to its quality\n** and performance is with the customer\n********************************************************************************\n**Released by: WEBENCH(R) Design Center, Texas Instruments Inc.\n* Part: TPS22919\n* Date: 09OCT2018\n* Model Type: Transient\n* Simulator: PSPICE\n* Simulator Version: 16.2.0.s003\n* EVM Order Number: \n* EVM Users Guide: \n* Datasheet: SLVSEN5 –MARCH 2018\n*\n* Model Version: Final 1.00\n*\n*****************************************************************************\n* Updates:\n*\n* Final 1.00\n* Release to Web.\n* \n*****************************************************************************\n*\n* Model Usage Notes:\n*\n* A. Features that have been modelled\n*\t1. The following features have been modelled\n*      a. Switching Characteristics for VIN ranging from 1.8V to 5.5V\n*      b. RON variation with VIN\n*      c. Adjustable output rise time \n*      d. Adjustable quick output discharge\n*      e. Quiescent current vs VIN at room temperature\n*      f. Shutdown current vs VIN at room temperature\n* 2. Temperature effects have not been modelled \n*\n*****************************************************************************\n.SUBCKT TPS22919_TRANS GND ON QOD VIN VOUT  \nE_U1_U2_E7         U1_U2_VGATE_OUT 0 U1_U2_VGATE VOUT 1\nG_U1_U2_G1         U1_U2_VGATE_CLAMP U1_U2_VGATE U1_U2_N16813340 0 1\nX_U1_U2_S5    U1_U2_ON_INTB 0 VOUT 0 DRIVER_U1_U2_S5 \nC_U1_U2_Cgd         U1_U2_N16813296 U1_U2_VGATE  0.4n  \nE_U1_U2_E8         U1_U2_VOUT_INT 0 VOUT 0 1\nE_U1_U2_E4         U1_U2_N16813658 0 TABLE { V(VIN, 0) } \n+ ( (0,0) (1.8,92m) (3.6,51m) (5,50m) )\nC_U1_U2_Cgs         U1_U2_VGATE VOUT  0.1n  \nD_U1_U2_D5         U1_U2_VGATE U1_U2_VGATE_CLAMP DD \nD_U1_U2_D6         VOUT U1_U2_N16813296 DD \nX_U1_U2_U791         U1_N03821 U1_U2_ON_INTB INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+  VTHRESH=500E-3\nE_U1_U2_ABM10         U1_U2_SC_LV2 0 VALUE { IF(V(VOUT)<0.36,1,0)    }\nG_U1_U2_ABM2I4         U1_U2_VGATE VOUT VALUE { IF(V(U1_U2_VSC)<0.5, 0,\n+  LIMIT((V(U1_U2_I_SENSE)-V(U1_U2_ILIM_VALUE))*1m, 0,100u))    }\nX_U1_U2_H1    U1_U2_N16813604 U1_U2_N16813296 U1_U2_I_SENSE 0 DRIVER_U1_U2_H1 \nE_U1_U2_E6         U1_U2_ITD 0 TABLE { V(VIN, 0) } \n+ ( (0,0) (1.8,0.2u) (3.6,0.17u) (5,0.15u) )\nE_U1_U2_ABM9         U1_U2_SC_LV1 0 VALUE { IF(V(VOUT)<V(U1_U2_N16888292),  \n+ 1,0)   }\nE_U1_U2_ABM11         U1_U2_ILIM_VALUE 0 VALUE {\n+  IF(V(U1_U2_PRE_VSC)<0.5,10,IF(V(U1_U2_SC_LV2)>0.5,0.15,3))    }\nV_U1_U2_V1         VIN U1_U2_N16888292 1.5\nX_U1_U2_U790         U1_U2_PRE_VSC U1_U2_VSC BUF_DELAY_BASIC_GEN PARAMS: VDD=1\n+  VSS=0 VTHRESH=0.5 DELAY=2u\nE_U1_U2_E5         U1_U2_IGATE 0 TABLE { V(VIN, 0) } \n+ ( (0,0) (1.8,0.7u) (3.6,0.989u) (5,1.19u) )\nV_U1_U2_V2         U1_U2_VGATE_CLAMP VIN 5\nG_U1_U2_G2         U1_U2_VGATE U1_U2_VOUT_INT U1_U2_N16913031 0 1\nX_U1_U2_U789         U1_U2_SC_LV1 U1_U2_SC_LV2 U1_U2_PRE_VSC OR2_BASIC_GEN\n+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nM_U1_U2_M1         U1_U2_N16813296 U1_U2_VGATE VOUT VOUT NMOS01           \nE_U1_U2_ABM13         U1_U2_N16913031 0 VALUE { IF(V(U1_U2_ON_INTB)<0.2,0,  \n+ V(U1_U2_N16928533))   }\nD_U1_U2_D7         VOUT U1_U2_VGATE DD \nE_U1_U2_E10         U1_U2_N16928533 0 TABLE { V(VIN, 0) } \n+ ( (0,0) (1.8,277u) (3.6,269u) (5,278u) )\nX_U1_U2_U4         VIN U1_U2_N16813604 U1_U2_N16813658 0 RVAR PARAMS:  RREF=1\nE_U1_U2_ABM8         U1_U2_N16813340 0 VALUE { IF ( V(U1_N03821) > 0.5 &\n+  V(U1_U2_VGATE_OUT) < 0.65, V(U1_U2_ITD),  \n+ IF ( V(U1_N03821) > 0.5 & V(U1_U2_VGATE_OUT) >= 0.65, V(U1_U2_IGATE) ,  0  )\n+   )   }\nD_U1_U2_D8         U1_U2_VOUT_INT U1_U2_VGATE DD \nX_U1_U2_S4    U1_U2_ON_INTB 0 QOD GND DRIVER_U1_U2_S4 \nX_U1_U1_U5         ON U1_U1_THRISE U1_U1_HYS ON_INT_PRE COMPHYS_BASIC_GEN\n+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U1_U1_S1    U1_U1_N427964 0 U1_U1_N427858 0 CONTROL_U1_U1_S1 \nD_U1_U1_D3         U1_U1_N427858 U1_U1_N14507001 DD \nE_U1_U1_E1         U1_U1_THRISE 0 TABLE { V(VIN, 0) } \n+ ( \n+  (0,0)(1,0.783)(1.2,0.784)(1.8,0.788)(2.5,0.792)(3.3,0.794)(4.2,0.798)(5,0.801)(5.5,0.805)\n+  )\nX_U1_U1_U43         U1_U1_N427858 U1_N03821 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0\n+  VTHRESH=0.5\nE_U1_U1_E2         U1_U1_HYS 0 TABLE { V(VIN, 0) } \n+ (\n+  (0,0)(1,98m)(1.2,99m)(1.8,100m)(2.5,104m)(3.3,102m)(4.2,106m)(5,105m)(5.5,106m)\n+  )\nV_U1_U1_V5         U1_U1_N14507001 0 2\nR_U1_U1_R3         U1_U1_N15516119 U1_U1_N15516099  10 TC=0,0 \nX_U1_U1_S3    ON_INT_PRE 0 ON 0 CONTROL_U1_U1_S3 \nG_U1_U1_G1         U1_U1_N427858 0 TABLE { V(U1_U1_N15516099, 0) } \n+ ( (0,0)(1,220u)(1.8,380u)(2.5,460u)(3.3,380u)(4.2,400u)(5,380u) )\nC_U1_U1_C1         0 U1_U1_N427858  1n IC=0 \nC_U1_U1_C4         U1_U1_N15516099 0  1n  \nV_U1_U1_V4         U1_U1_N427908 0 1\nG_U1_U1_ABM2I4         U1_U1_N14507001 U1_U1_N427858 VALUE { IF (V(ON_INT_PRE)\n+  > 0.5, 1m, 0)    }\nE_U1_U1_ABM5         U1_U1_N15516119 0 VALUE { IF(V(ON_INT_PRE) <0.5, V(VIN),0)\n+     }\nX_U1_U1_U46         U1_N03821 ON_INT_PRE U1_U1_N427964 NOR2_BASIC_GEN PARAMS:\n+  VDD=1 VSS=0 VTHRESH=500E-3\nX_U1_U1_S2    U1_U1_N427944 0 U1_U1_N427908 U1_U1_N427858 CONTROL_U1_U1_S2 \nX_U1_U1_U44         ON_INT_PRE U1_N03821 U1_U1_N427944 AND2_BASIC_GEN PARAMS:\n+  VDD=1 VSS=0 VTHRESH=500E-3\nC_U2_C2         0 U2_N14553136  1n  \nR_U2_R4         U2_N14553248 U2_N14553232  10 TC=0,0 \nG_U2_G1         VIN GND TABLE { V(U2_N14553232, 0) } \n+ ( (0,0) (1.8,6.9u) (5,6.9u) )\nC_U2_C3         0 U2_N14553232  1n  \nE_U2_ABM2         U2_N14553152 0 VALUE { IF (V(ON_INT_PRE) < 0.5 , V(VIN) ,  0)\n+     }\nR_U2_R3         U2_N14553152 U2_N14553136  10 TC=0,0 \nE_U2_ABM3         U2_N14553248 0 VALUE { IF (V(ON_INT_PRE) > 0.5 , V(VIN) ,  0)\n+     }\nG_U2_G2         VIN GND TABLE { V(U2_N14553136, 0) } \n+ ( (0,0) (1.8,2n) (5,2n) )\n.ENDS TPS22919_TRANS\n*$\n.subckt DRIVER_U1_U2_S5 1 2 3 4  \nS_U1_U2_S5         3 4 1 2 _U1_U2_S5\nRS_U1_U2_S5         1 2 1G\n.MODEL         _U1_U2_S5 VSWITCH Roff=1E9 Ron=500k Voff=0.2 Von=0.8\n.ends DRIVER_U1_U2_S5\n*$\n.subckt DRIVER_U1_U2_H1 1 2 3 4  \nH_U1_U2_H1         3 4 VH_U1_U2_H1 1\nVH_U1_U2_H1         1 2 0V\n.ends DRIVER_U1_U2_H1\n*$\n.subckt DRIVER_U1_U2_S4 1 2 3 4  \nS_U1_U2_S4         3 4 1 2 _U1_U2_S4\nRS_U1_U2_S4         1 2 1G\n.MODEL         _U1_U2_S4 VSWITCH Roff=1E9 Ron=27 Voff=0.2 Von=0.8\n.ends DRIVER_U1_U2_S4\n*$\n.subckt CONTROL_U1_U1_S1 1 2 3 4  \nS_U1_U1_S1         3 4 1 2 _U1_U1_S1\nRS_U1_U1_S1         1 2 1G\n.MODEL         _U1_U1_S1 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8\n.ends CONTROL_U1_U1_S1\n*$\n.subckt CONTROL_U1_U1_S3 1 2 3 4  \nS_U1_U1_S3         3 4 1 2 _U1_U1_S3\nRS_U1_U1_S3         1 2 1G\n.MODEL         _U1_U1_S3 VSWITCH Roff=10G Ron=500k Voff=0.2 Von=0.8\n.ends CONTROL_U1_U1_S3\n*$\n.subckt CONTROL_U1_U1_S2 1 2 3 4  \nS_U1_U1_S2         3 4 1 2 _U1_U1_S2\nRS_U1_U1_S2         1 2 1G\n.MODEL         _U1_U1_S2 VSWITCH Roff=100e6 Ron=1m Voff=0.2 Von=0.8\n.ends CONTROL_U1_U1_S2\n*$\n.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \n+ V(B) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NAND2_BASIC_GEN\n*$\n.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\nEIN INP1 INM1 INP INM 1 \nEHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }\nEOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }\nR1 OUT 1 1\nC1 1 0 5n\nRINP1 INP1 0 1K\n.ENDS COMPHYS_BASIC_GEN\n*$\n.MODEL DD D( IS=1F N=0.01 TT = 10p )\n*$\n.MODEL NMOS01 NMOS (VTO = 0.65 KP = 5.931 LAMBDA = 0.001)\n*$\n.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  \n+ V(B) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS AND2_BASIC_GEN\n*$\n.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \n+ V(B) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS OR2_BASIC_GEN\n*$\n.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS BUF_BASIC_GEN\n*$\n.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  \n+ V(B) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NOR2_BASIC_GEN\n*$\n.SUBCKT RVAR 101 102 201 202 Params: Rref=1\n* nodes : 101 102 : nodes between which variable resistance is placed\n* 201 202 : nodes to whose voltage the resistance is proportional\n* parameters : rref : reference value of the resistance\nrin 201 202 1G; input resistance\nr 301 0 {rref}\nfcopy 0 301 vsense 1; copy output current thru Z\neout 101 106 poly(2) 201 202 301 0 0 0 0 0 1; multiply VoverZ with Vctrl\nvsense 106 102 0; sense iout\n.ENDS RVAR\n*$\n**Reset has higher priority in this latch\n.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nGQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}\nCQint Qint 0 1n\nRQint Qint 0 1000MEG\nD_D10 Qint MY5 D_D1\nV1 MY5 0 {VDD}\nD_D11 MYVSS Qint D_D1\nV2 MYVSS 0 {VSS} \nEQ Qqq 0 Qint 0 1\nX3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\nRQq Qqqd1 Q 1\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\nRQb Qbr QB 1 \nCdummy1 Q 0 1n \nCdummy2 QB 0 1n\n.IC V(Qint) {VSS}\n.MODEL D_D1 D (IS = 1e-15 TT = 10p Rs=0.05 N = 0.1)\n.ENDS SRLATCHRHP_BASIC_GEN\n*$\n.SUBCKT D_D1 1 2\nD1 1 2 DD1\n.MODEL DD1 D (IS = 1e-15 TT = 10p Rs=0.05 N = 0.1)\n.ENDS D_D1\n*$\n.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \nE_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT1 YINT2 1\nCINT YINT2 0 {DELAY*1.3}\nE_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT2 YINT3 Y 1\nCINT2 Y 0 1n\n.ENDS BUF_DELAY_BASIC_GEN\n*$\n.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS INV_BASIC_GEN\n*$\n.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\nE_ABM Yint 0 VALUE {IF (V(INP) > \n+ V(INM), {VDD},{VSS})}\nR1 Yint Y 1\nC1 Y 0 1n\n.ENDS COMP_BASIC_GEN\n*$\n.SUBCKT RISING_ONESHOT IN OUT PARAMS: PULSE=100n VDD=1 VSS=0 VTHRESH=0.5\nD_D1         INT IN DD \nC_C1         0 INT  1n  \nX_U22         INT IN_B_DELAYED INV_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS}\n+  VTHRESH={VTHRESH}\nR_R1         IN INT  {PULSE/(0.693 * 1E-9)}  \nX_U1         IN IN_B_DELAYED OUT AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS}\n+  VTHRESH={VTHRESH}\n.MODEL DD D( IS=1F N=0.01 TT = 10p )\n.ENDS RISING_ONESHOT\n*
quot; }, { "type": "simulation_voltage_source", "simulation_voltage_source_id": "simulation_voltage_source_0", "is_dc_source": false, "terminal1_source_port_id": "source_port_6", "terminal2_source_port_id": "source_port_7", "voltage": 5 }, { "type": "schematic_component", "schematic_component_id": "schematic_component_0", "center": { "x": 0, "y": 0 }, "rotation": 0, "size": { "width": 2, "height": 3 }, "port_arrangement": { "left_side": { "pins": [ "IN", "ON", "GND" ], "direction": "top-to-bottom" }, "right_side": { "pins": [ "OUT", "QOD" ], "direction": "top-to-bottom" } }, "pin_spacing": 0.2, "pin_styles": { "pin1": {}, "pin2": {}, "pin3": {}, "pin5": {}, "pin6": {} }, "port_labels": { "pin1": "IN", "pin2": "GND", "pin3": "ON", "pin4": "NC", "pin5": "QOD", "pin6": "OUT" }, "source_component_id": "source_component_0", "schematic_group_id": "schematic_group_0" }, { "type": "schematic_text", "schematic_text_id": "schematic_text_0", "text": "TPS22919DCKR", "schematic_component_id": "schematic_component_0", "anchor": "left", "rotation": 0, "position": { "x": -1, "y": -1.63 }, "color": "#006464", "font_size": 0.18 }, { "type": "schematic_text", "schematic_text_id": "schematic_text_1", "text": "U1", "schematic_component_id": "schematic_component_0", "anchor": "left", "rotation": 0, "position": { "x": -1, "y": 1.63 }, "color": "#006464", "font_size": 0.18 }, { "type": "schematic_component", "schematic_component_id": "schematic_component_1", "center": { "x": -4.8, "y": 0.4 }, "size": { "width": 0.6194553499999995, "height": 1.08 }, "source_component_id": "source_component_1", "is_box_with_pins": true, "symbol_name": "ac_voltmeter_up", "symbol_display_value": "5V", "schematic_group_id": "schematic_group_0" }, { "type": "schematic_component", "schematic_component_id": "schematic_component_2", "center": { "x": -3.3, "y": 0.4 }, "size": { "width": 0.6235344000000015, "height": 1.0558211000000002 }, "source_component_id": "source_component_2", "is_box_with_pins": true, "symbol_name": "capacitor_polarized_down", "symbol_display_value": "1uF", "schematic_group_id": "schematic_group_0" }, { "type": "schematic_component", "schematic_component_id": "schematic_component_3", "center": { "x": 2, "y": 0.2 }, "size": { "width": 0.9, "height": 0.6 }, "source_component_id": "source_component_3", "is_box_with_pins": true, "symbol_name": "boxresistor_up", "symbol_display_value": "100kΩ", "schematic_group_id": "schematic_group_0" }, { "type": "schematic_component", "schematic_component_id": "schematic_component_4", "center": { "x": 4, "y": 0.4 }, "size": { "width": 0.6235344000000015, "height": 1.0558211000000002 }, "source_component_id": "source_component_4", "is_box_with_pins": true, "symbol_name": "capacitor_polarized_down", "symbol_display_value": "10uF", "schematic_group_id": "schematic_group_0" }, { "type": "schematic_component", "schematic_component_id": "schematic_component_5", "center": { "x": 5, "y": 0.4 }, "size": { "width": 0.9, "height": 0.6 }, "source_component_id": "source_component_5", "is_box_with_pins": true, "symbol_name": "boxresistor_up", "symbol_display_value": "10kΩ", "schematic_group_id": "schematic_group_0" }, { "type": "schematic_group", "schematic_group_id": "schematic_group_0", "is_subcircuit": true, "subcircuit_id": "subcircuit_source_group_0", "name": "unnamed_group1", "center": { "x": 0, "y": 0 }, "width": 0, "height": 0, "schematic_component_ids": [], "source_group_id": "source_group_0", "show_as_schematic_box": false }, { "type": "schematic_port", "schematic_port_id": "schematic_port_0", "schematic_component_id": "schematic_component_0", "center": { "x": -1.4, "y": 0.9500000000000001 }, "source_port_id": "source_port_0", "facing_direction": "left", "distance_from_component_edge": 0.4, "side_of_component": "left", "pin_number": 1, "true_ccw_index": 0, "display_pin_label": "IN", "is_connected": true }, { "type": "schematic_port", "schematic_port_id": "schematic_port_1", "schematic_component_id": "schematic_component_0", "center": { "x": -1.4, "y": -1.05 }, "source_port_id": "source_port_1", "facing_direction": "left", "distance_from_component_edge": 0.4, "side_of_component": "left", "pin_number": 2, "true_ccw_index": 1, "display_pin_label": "GND", "is_connected": true }, { "type": "schematic_port", "schematic_port_id": "schematic_port_2", "schematic_component_id": "schematic_component_0", "center": { "x": -1.4, "y": -0.050000000000000044 }, "source_port_id": "source_port_2", "facing_direction": "left", "distance_from_component_edge": 0.4, "side_of_component": "left", "pin_number": 3, "true_ccw_index": 2, "display_pin_label": "ON", "is_connected": false }, { "type": "schematic_port", "schematic_port_id": "schematic_port_3", "schematic_component_id": "schematic_component_0", "center": { "x": 1.4, "y": -0.35000000000000003 }, "source_port_id": "source_port_4", "facing_direction": "right", "distance_from_component_edge": 0.4, "side_of_component": "right", "pin_number": 5, "true_ccw_index": 4, "display_pin_label": "QOD", "is_connected": true }, { "type": "schematic_port", "schematic_port_id": "schematic_port_4", "schematic_component_id": "schematic_component_0", "center": { "x": 1.4, "y": 0.95 }, "source_port_id": "source_port_5", "facing_direction": "right", "distance_from_component_edge": 0.4, "side_of_component": "right", "pin_number": 6, "true_ccw_index": 5, "display_pin_label": "OUT", "is_connected": true }, { "type": "schematic_port", "schematic_port_id": "schematic_port_5", "schematic_component_id": "schematic_component_1", "center": { "x": -4.795, "y": -0.14 }, "source_port_id": "source_port_6", "facing_direction": "down", "distance_from_component_edge": 0.4, "pin_number": 1, "display_pin_label": "terminal1", "is_connected": true }, { "type": "schematic_port", "schematic_port_id": "schematic_port_6", "schematic_component_id": "schematic_component_1", "center": { "x": -4.805, "y": 0.9400000000000001 }, "source_port_id": "source_port_7", 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