tscircuit/ti
ti tscircuit library
- Version
- 1.0.85
- License
- unset
- Stars
- 0
dist/lib/subcircuits/BatteryManagement_BQ25895/circuit.json
PCB
Schematic
[
{
"type": "source_group",
"source_group_id": "source_group_0",
"is_subcircuit": true,
"was_automatically_named": true,
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_0",
"name": "VBUS",
"pin_number": 1,
"port_hints": [
"VBUS",
"pin1",
"1"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_1",
"name": "USB_D_POS",
"pin_number": 2,
"port_hints": [
"USB_D_POS",
"D_POS",
"pin2",
"2"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_2",
"name": "USB_D_NEG",
"pin_number": 3,
"port_hints": [
"USB_D_NEG",
"D_NEG",
"pin3",
"3"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_3",
"name": "STAT",
"pin_number": 4,
"port_hints": [
"STAT",
"pin4",
"4"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net14"
},
{
"type": "source_port",
"source_port_id": "source_port_4",
"name": "I2C_SCL",
"pin_number": 5,
"port_hints": [
"I2C_SCL",
"SCL",
"pin5",
"5"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_port",
"source_port_id": "source_port_5",
"name": "I2C_SDA",
"pin_number": 6,
"port_hints": [
"I2C_SDA",
"SDA",
"pin6",
"6"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_port",
"source_port_id": "source_port_6",
"name": "INT",
"pin_number": 7,
"port_hints": [
"INT",
"pin7",
"7"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_port",
"source_port_id": "source_port_7",
"name": "OTG",
"pin_number": 8,
"port_hints": [
"OTG",
"pin8",
"8"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_port",
"source_port_id": "source_port_8",
"name": "CE",
"pin_number": 9,
"port_hints": [
"CE",
"pin9",
"9"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_port",
"source_port_id": "source_port_9",
"name": "ILIM",
"pin_number": 10,
"port_hints": [
"ILIM",
"pin10",
"10"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_10",
"name": "TS",
"pin_number": 11,
"port_hints": [
"TS",
"pin11",
"11"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_port",
"source_port_id": "source_port_11",
"name": "QON",
"pin_number": 12,
"port_hints": [
"QON",
"pin12",
"12"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net19"
},
{
"type": "source_port",
"source_port_id": "source_port_12",
"name": "BAT1",
"pin_number": 13,
"port_hints": [
"BAT1",
"pin13",
"13"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_port",
"source_port_id": "source_port_13",
"name": "BAT2",
"pin_number": 14,
"port_hints": [
"BAT2",
"pin14",
"14"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_port",
"source_port_id": "source_port_14",
"name": "SYS1",
"pin_number": 15,
"port_hints": [
"SYS1",
"pin15",
"15"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_port",
"source_port_id": "source_port_15",
"name": "SYS2",
"pin_number": 16,
"port_hints": [
"SYS2",
"pin16",
"16"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_port",
"source_port_id": "source_port_16",
"name": "PGND1",
"pin_number": 17,
"port_hints": [
"PGND1",
"pin17",
"17"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_17",
"name": "PGND2",
"pin_number": 18,
"port_hints": [
"PGND2",
"pin18",
"18"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_18",
"name": "SW1",
"pin_number": 19,
"port_hints": [
"SW1",
"pin19",
"19"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_port",
"source_port_id": "source_port_19",
"name": "SW2",
"pin_number": 20,
"port_hints": [
"SW2",
"pin20",
"20"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_port",
"source_port_id": "source_port_20",
"name": "BTST",
"pin_number": 21,
"port_hints": [
"BTST",
"pin21",
"21"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net16"
},
{
"type": "source_port",
"source_port_id": "source_port_21",
"name": "REGN",
"pin_number": 22,
"port_hints": [
"REGN",
"pin22",
"22"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net17"
},
{
"type": "source_port",
"source_port_id": "source_port_22",
"name": "PMID",
"pin_number": 23,
"port_hints": [
"PMID",
"pin23",
"23"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_23",
"name": "DSEL",
"pin_number": 24,
"port_hints": [
"DSEL",
"pin24",
"24"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_24",
"name": "PAD",
"pin_number": 25,
"port_hints": [
"PAD",
"pin25",
"25"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_0",
"ftype": "simple_chip",
"name": "U1",
"manufacturer_part_number": "BQ25895RTWR",
"supplier_part_numbers": {
"jlcpcb": [
"C80200"
]
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_25",
"name": "VBUS",
"pin_number": 1,
"port_hints": [
"VBUS",
"pin1",
"1"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_26",
"name": "D_POS",
"pin_number": 2,
"port_hints": [
"D_POS",
"pin2",
"2"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_27",
"name": "D_NEG",
"pin_number": 3,
"port_hints": [
"D_NEG",
"pin3",
"3"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_28",
"name": "GND",
"pin_number": 4,
"port_hints": [
"GND",
"pin4",
"4"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_1",
"ftype": "simple_chip",
"name": "J1",
"manufacturer_part_number": "USB Input",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_29",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_30",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_2",
"ftype": "simple_capacitor",
"name": "C1",
"supplier_part_numbers": {
"jlcpcb": [
"C15849",
"C6119852",
"C29936"
]
},
"capacitance": 0.000001,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_31",
"name": "5V",
"pin_number": 1,
"port_hints": [
"5V",
"pin1",
"1"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_32",
"name": "GND",
"pin_number": 2,
"port_hints": [
"GND",
"pin2",
"2"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_3",
"ftype": "simple_chip",
"name": "J2",
"manufacturer_part_number": "Phone OTG",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_33",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_34",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_4",
"ftype": "simple_capacitor",
"name": "C2",
"supplier_part_numbers": {
"jlcpcb": []
},
"capacitance": 0.00004,
"display_capacitance": "40uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_35",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_36",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_5",
"ftype": "simple_resistor",
"name": "R1",
"supplier_part_numbers": {
"jlcpcb": [
"C2960702",
"C304749",
"C2984354"
]
},
"resistance": 260,
"display_resistance": "260Ω",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_37",
"name": "VREF",
"pin_number": 1,
"port_hints": [
"VREF",
"pin1",
"1"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_38",
"name": "SDA",
"pin_number": 2,
"port_hints": [
"SDA",
"pin2",
"2"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_port",
"source_port_id": "source_port_39",
"name": "SCL",
"pin_number": 3,
"port_hints": [
"SCL",
"pin3",
"3"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_port",
"source_port_id": "source_port_40",
"name": "INT",
"pin_number": 4,
"port_hints": [
"INT",
"pin4",
"4"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_port",
"source_port_id": "source_port_41",
"name": "OTG",
"pin_number": 5,
"port_hints": [
"OTG",
"pin5",
"5"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_port",
"source_port_id": "source_port_42",
"name": "CE",
"pin_number": 6,
"port_hints": [
"CE",
"pin6",
"6"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_component",
"source_component_id": "source_component_6",
"ftype": "simple_chip",
"name": "J3",
"manufacturer_part_number": "Host",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_43",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_44",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_component",
"source_component_id": "source_component_7",
"ftype": "simple_resistor",
"name": "R2",
"supplier_part_numbers": {
"jlcpcb": [
"C667535",
"C217844",
"C234344"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_45",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_8",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_46",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_8",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_component",
"source_component_id": "source_component_8",
"ftype": "simple_resistor",
"name": "R3",
"supplier_part_numbers": {
"jlcpcb": [
"C22833",
"C321687",
"C170443"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_47",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_48",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_component",
"source_component_id": "source_component_9",
"ftype": "simple_resistor",
"name": "R4",
"supplier_part_numbers": {
"jlcpcb": [
"C22843",
"C2930050",
"C2907083"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_49",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_10",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_port",
"source_port_id": "source_port_50",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_10",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net13"
},
{
"type": "source_component",
"source_component_id": "source_component_10",
"ftype": "simple_resistor",
"name": "R5",
"supplier_part_numbers": {
"jlcpcb": [
"C22843",
"C2930050",
"C2907083"
]
},
"resistance": 2200,
"display_resistance": "2.2kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_51",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net13"
},
{
"type": "source_port",
"source_port_id": "source_port_52",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net14"
},
{
"type": "source_component",
"source_component_id": "source_component_11",
"ftype": "simple_led",
"name": "D1",
"color": "yellow",
"symbol_display_value": "yellow",
"supplier_part_numbers": {
"jlcpcb": [
"C965799",
"C84263",
"C965804"
]
},
"are_pins_interchangeable": false,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_53",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_12",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_port",
"source_port_id": "source_port_54",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_12",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net16"
},
{
"type": "source_component",
"source_component_id": "source_component_12",
"ftype": "simple_capacitor",
"name": "C3",
"supplier_part_numbers": {
"jlcpcb": [
"C19666",
"C1705",
"C6119856"
]
},
"capacitance": 4.7e-8,
"display_capacitance": "47nF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_55",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_13",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net17"
},
{
"type": "source_port",
"source_port_id": "source_port_56",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_13",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_13",
"ftype": "simple_capacitor",
"name": "C4",
"supplier_part_numbers": {
"jlcpcb": [
"C19666",
"C1705",
"C6119856"
]
},
"capacitance": 0.0000047,
"display_capacitance": "4.7uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_57",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_14",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_port",
"source_port_id": "source_port_58",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_14",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_component",
"source_component_id": "source_component_14",
"name": "L1",
"ftype": "simple_inductor",
"inductance": "2.2uH",
"display_inductance": "2.2µH",
"supplier_part_numbers": {
"jlcpcb": []
},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_59",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_15",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_port",
"source_port_id": "source_port_60",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_15",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_15",
"ftype": "simple_capacitor",
"name": "C5",
"supplier_part_numbers": {
"jlcpcb": [
"C19702",
"C96446",
"C1691"
]
},
"capacitance": 0.00001,
"display_capacitance": "10uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_61",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_16",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_port",
"source_port_id": "source_port_62",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_16",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_16",
"ftype": "simple_capacitor",
"name": "C6",
"supplier_part_numbers": {
"jlcpcb": [
"C19702",
"C96446",
"C1691"
]
},
"capacitance": 0.00001,
"display_capacitance": "10uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_63",
"name": "BAT_POS",
"pin_number": 1,
"port_hints": [
"BAT_POS",
"pin1",
"1"
],
"source_component_id": "source_component_17",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_port",
"source_port_id": "source_port_64",
"name": "GND",
"pin_number": 2,
"port_hints": [
"GND",
"pin2",
"2"
],
"source_component_id": "source_component_17",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_17",
"ftype": "simple_chip",
"name": "BT1",
"manufacturer_part_number": "Battery",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_65",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_18",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_port",
"source_port_id": "source_port_66",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_18",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_18",
"ftype": "simple_capacitor",
"name": "C7",
"supplier_part_numbers": {
"jlcpcb": [
"C19702",
"C96446",
"C1691"
]
},
"capacitance": 0.00001,
"display_capacitance": "10uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_67",
"name": "QON",
"pin_number": 1,
"port_hints": [
"QON",
"pin1",
"1"
],
"source_component_id": "source_component_19",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net19"
},
{
"type": "source_port",
"source_port_id": "source_port_68",
"name": "GND",
"pin_number": 2,
"port_hints": [
"GND",
"pin2",
"2"
],
"source_component_id": "source_component_19",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_19",
"ftype": "simple_chip",
"name": "SW1",
"manufacturer_part_number": "Optional QON Pushbutton",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_69",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_20",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net17"
},
{
"type": "source_port",
"source_port_id": "source_port_70",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_20",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_component",
"source_component_id": "source_component_20",
"ftype": "simple_resistor",
"name": "R6",
"supplier_part_numbers": {
"jlcpcb": [
"C23068",
"C2930111",
"C227977"
]
},
"resistance": 5230,
"display_resistance": "5.23kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_71",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_21",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_port",
"source_port_id": "source_port_72",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_21",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_21",
"ftype": "simple_resistor",
"name": "R7",
"supplier_part_numbers": {
"jlcpcb": [
"C2960871",
"C23000",
"C137745"
]
},
"resistance": 30100,
"display_resistance": "30.1kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_73",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_22",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_port",
"source_port_id": "source_port_74",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_22",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_22",
"ftype": "simple_resistor",
"name": "RT1",
"supplier_part_numbers": {
"jlcpcb": [
"C25804",
"C2906982",
"C98220"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_net",
"source_net_id": "source_net_0",
"name": "GND",
"member_source_group_ids": [],
"is_ground": true,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_net",
"source_net_id": "source_net_1",
"name": "VREF",
"member_source_group_ids": [],
"is_ground": false,
"is_power": true,
"is_positive_voltage_source": true,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "The \"J\" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />",
"source_component_id": "source_component_1",
"refdes": "J1",
"source_component_ftype": "simple_chip",
"expected_prefixes": [
"U",
"IC"
],
"actual_prefix": "J",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_0"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "The \"J\" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />",
"source_component_id": "source_component_3",
"refdes": "J2",
"source_component_ftype": "simple_chip",
"expected_prefixes": [
"U",
"IC"
],
"actual_prefix": "J",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_1"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "The \"J\" prefix is being used with a <chip />, try using it with a <connector /> or <jumper />",
"source_component_id": "source_component_6",
"refdes": "J3",
"source_component_ftype": "simple_chip",
"expected_prefixes": [
"U",
"IC"
],
"actual_prefix": "J",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_2"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "The \"S\" prefix is being used with a <chip />, try using it with a <switch /> or <pushbutton />",
"source_component_id": "source_component_19",
"refdes": "SW1",
"source_component_ftype": "simple_chip",
"expected_prefixes": [
"U",
"IC"
],
"actual_prefix": "SW",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_3"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "Component RT1 has ftype=\"simple_resistor\" but reference designator should start with R",
"source_component_id": "source_component_22",
"refdes": "RT1",
"source_component_ftype": "simple_resistor",
"expected_prefixes": [
"R"
],
"actual_prefix": "RT",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_4"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_0",
"connected_source_port_ids": [
"source_port_16"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".U1 > .pin17 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_0",
"message": "<trace#5895(from:.U1 > .pin17 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_0",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_1",
"connected_source_port_ids": [
"source_port_17"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".U1 > .pin18 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_1",
"message": "<trace#5896(from:.U1 > .pin18 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_1",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_2",
"connected_source_port_ids": [
"source_port_23"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".U1 > .pin24 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_2",
"message": "<trace#5897(from:.U1 > .pin24 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_2",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_3",
"connected_source_port_ids": [
"source_port_24"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".U1 > .pin25 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_3",
"message": "<trace#5898(from:.U1 > .pin25 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_3",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_4",
"connected_source_port_ids": [
"source_port_28"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".J1 > .pin4 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_4",
"message": "<trace#5899(from:.J1 > .pin4 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_4",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_5",
"connected_source_port_ids": [
"source_port_30"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": ".C1 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_5",
"message": "<trace#5900(from:.C1 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_5",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_6",
"connected_source_port_ids": [
"source_port_32"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".J2 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_6",
"message": "<trace#5901(from:.J2 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_6",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_7",
"connected_source_port_ids": [
"source_port_34"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": ".C2 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_7",
"message": "<trace#5902(from:.C2 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_7",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_8",
"connected_source_port_ids": [
"source_port_36"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".R1 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_8",
"message": "<trace#5903(from:.R1 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_8",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_9",
"connected_source_port_ids": [
"source_port_37"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".J3 > .pin1 to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_9",
"message": "<trace#5904(from:.J3 > .pin1 to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_9",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_10",
"connected_source_port_ids": [
"source_port_43"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".R2 > .pin1 to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_10",
"message": "<trace#5905(from:.R2 > .pin1 to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_10",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_11",
"connected_source_port_ids": [
"source_port_45"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".R3 > .pin1 to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_11",
"message": "<trace#5906(from:.R3 > .pin1 to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_11",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_12",
"connected_source_port_ids": [
"source_port_47"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".R4 > .pin1 to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_12",
"message": "<trace#5907(from:.R4 > .pin1 to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_12",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_13",
"connected_source_port_ids": [
"source_port_56"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": ".C4 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_13",
"message": "<trace#5908(from:.C4 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_13",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_14",
"connected_source_port_ids": [
"source_port_60"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": ".C5 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_14",
"message": "<trace#5909(from:.C5 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_14",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_15",
"connected_source_port_ids": [
"source_port_62"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": ".C6 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_15",
"message": "<trace#5910(from:.C6 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_15",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_16",
"connected_source_port_ids": [
"source_port_64"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".BT1 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_16",
"message": "<trace#5911(from:.BT1 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_16",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_17",
"connected_source_port_ids": [
"source_port_66"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": ".C7 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_17",
"message": "<trace#5912(from:.C7 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_17",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_18",
"connected_source_port_ids": [
"source_port_68"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".SW1 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_18",
"message": "<trace#5913(from:.SW1 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_18",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_19",
"connected_source_port_ids": [
"source_port_72"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".R7 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_19",
"message": "<trace#5914(from:.R7 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_19",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_20",
"connected_source_port_ids": [
"source_port_74"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".RT1 > .pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_20",
"message": "<trace#5915(from:.RT1 > .pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_20",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_21",
"connected_source_port_ids": [
"source_port_25",
"source_port_29"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "J1.pin1 to C1.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_21",
"message": "<trace#5682(from:J1.pin1 to:C1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_21",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_22",
"connected_source_port_ids": [
"source_port_29",
"source_port_0"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "VBUS_C1_U1",
"max_length": null,
"display_name": "C1.pin1 to U1.VBUS",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_23",
"connected_source_port_ids": [
"source_port_26",
"source_port_1"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "USB_DP_U1",
"display_name": "J1.pin2 to U1.D_POS",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_24",
"connected_source_port_ids": [
"source_port_27",
"source_port_2"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "USB_DN_U1",
"display_name": "J1.pin3 to U1.D_NEG",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_25",
"connected_source_port_ids": [
"source_port_31",
"source_port_33"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "J2.pin1 to C2.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_22",
"message": "<trace#5686(from:J2.pin1 to:C2.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_25",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_26",
"connected_source_port_ids": [
"source_port_33",
"source_port_22"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C2.pin1 to U1.PMID",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_23",
"message": "<trace#5687(from:C2.pin1 to:U1.PMID) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_26",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_27",
"connected_source_port_ids": [
"source_port_35",
"source_port_9"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R1.pin1 to U1.ILIM",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_24",
"message": "<trace#5688(from:R1.pin1 to:U1.ILIM) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_27",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_28",
"connected_source_port_ids": [
"source_port_38",
"source_port_44"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "J3.pin2 to R2.pin2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_25",
"message": "<trace#5689(from:J3.pin2 to:R2.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_28",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_29",
"connected_source_port_ids": [
"source_port_44",
"source_port_5"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R2.pin2 to U1.SDA",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_26",
"message": "<trace#5690(from:R2.pin2 to:U1.SDA) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_29",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_30",
"connected_source_port_ids": [
"source_port_39",
"source_port_46"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "J3.pin3 to R3.pin2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_27",
"message": "<trace#5691(from:J3.pin3 to:R3.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_30",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_31",
"connected_source_port_ids": [
"source_port_46",
"source_port_4"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R3.pin2 to U1.SCL",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_28",
"message": "<trace#5692(from:R3.pin2 to:U1.SCL) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_31",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_32",
"connected_source_port_ids": [
"source_port_40",
"source_port_48"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "J3.pin4 to R4.pin2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_29",
"message": "<trace#5693(from:J3.pin4 to:R4.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_32",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_33",
"connected_source_port_ids": [
"source_port_48",
"source_port_6"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R4.pin2 to U1.INT",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_30",
"message": "<trace#5694(from:R4.pin2 to:U1.INT) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_33",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_34",
"connected_source_port_ids": [
"source_port_41",
"source_port_7"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "J3.pin5 to U1.OTG",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_31",
"message": "<trace#5695(from:J3.pin5 to:U1.OTG) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_34",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_35",
"connected_source_port_ids": [
"source_port_42",
"source_port_8"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "J3.pin6 to U1.CE",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_32",
"message": "<trace#5696(from:J3.pin6 to:U1.CE) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_35",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_36",
"connected_source_port_ids": [
"source_port_49",
"source_port_58"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "SYS_STAT_PULLUP",
"display_name": "R5.pin1 to L1.pin2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_37",
"connected_source_port_ids": [
"source_port_50",
"source_port_51"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R5.pin2 to D1.anode",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net13"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_33",
"message": "<trace#5698(from:R5.pin2 to:D1.anode) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_37",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_38",
"connected_source_port_ids": [
"source_port_52",
"source_port_3"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "D1.cathode to U1.STAT",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net14"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_34",
"message": "<trace#5699(from:D1.cathode to:U1.STAT) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_38",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_39",
"connected_source_port_ids": [
"source_port_18",
"source_port_57"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.SW1 to L1.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_35",
"message": "<trace#5700(from:U1.SW1 to:L1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_39",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_40",
"connected_source_port_ids": [
"source_port_19",
"source_port_57"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.SW2 to L1.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_36",
"message": "<trace#5701(from:U1.SW2 to:L1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_40",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_41",
"connected_source_port_ids": [
"source_port_53",
"source_port_57"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C3.pin1 to L1.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net15"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_37",
"message": "<trace#5702(from:C3.pin1 to:L1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_41",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_42",
"connected_source_port_ids": [
"source_port_54",
"source_port_20"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C3.pin2 to U1.BTST",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net16"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_38",
"message": "<trace#5703(from:C3.pin2 to:U1.BTST) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_42",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_43",
"connected_source_port_ids": [
"source_port_21",
"source_port_55"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "U1.REGN to C4.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net17"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_39",
"message": "<trace#5704(from:U1.REGN to:C4.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_43",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_44",
"connected_source_port_ids": [
"source_port_55",
"source_port_69"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "REGN_TS_BIAS",
"max_length": null,
"display_name": "C4.pin1 to R6.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net17"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_45",
"connected_source_port_ids": [
"source_port_58",
"source_port_59"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "L1.pin2 to C5.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_40",
"message": "<trace#5706(from:L1.pin2 to:C5.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_45",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_46",
"connected_source_port_ids": [
"source_port_59",
"source_port_61"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C5.pin1 to C6.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_41",
"message": "<trace#5707(from:C5.pin1 to:C6.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_46",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_47",
"connected_source_port_ids": [
"source_port_58",
"source_port_14"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "SYS_L1_U1_1",
"display_name": "L1.pin2 to U1.SYS1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_48",
"connected_source_port_ids": [
"source_port_58",
"source_port_15"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "SYS_L1_U1_2",
"display_name": "L1.pin2 to U1.SYS2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_49",
"connected_source_port_ids": [
"source_port_63",
"source_port_65"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "BT1.pin1 to C7.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_42",
"message": "<trace#5710(from:BT1.pin1 to:C7.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_49",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_50",
"connected_source_port_ids": [
"source_port_65",
"source_port_12"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "BAT_C7_U1_1",
"max_length": null,
"display_name": "C7.pin1 to U1.BAT1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_51",
"connected_source_port_ids": [
"source_port_65",
"source_port_13"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "BAT_C7_U1_2",
"max_length": null,
"display_name": "C7.pin1 to U1.BAT2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net18"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_52",
"connected_source_port_ids": [
"source_port_67",
"source_port_11"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "SW1.pin1 to U1.QON",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net19"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_43",
"message": "<trace#5713(from:SW1.pin1 to:U1.QON) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_52",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_53",
"connected_source_port_ids": [
"source_port_70",
"source_port_71"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R6.pin2 to R7.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_44",
"message": "<trace#5714(from:R6.pin2 to:R7.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_53",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_54",
"connected_source_port_ids": [
"source_port_70",
"source_port_73"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R6.pin2 to RT1.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_45",
"message": "<trace#5715(from:R6.pin2 to:RT1.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_54",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_55",
"connected_source_port_ids": [
"source_port_70",
"source_port_10"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R6.pin2 to U1.TS",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net20"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_46",
"message": "<trace#5716(from:R6.pin2 to:U1.TS) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_55",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 0,
"y": 0
},
"rotation": 0,
"size": {
"width": 2.6,
"height": 7.5
},
"port_arrangement": {
"left_side": {
"pins": [
"PMID",
"VBUS",
"D_POS",
"D_NEG",
"ILIM",
"STAT",
"SDA",
"SCL",
"INT",
"OTG",
"CE"
],
"direction": "top-to-bottom"
},
"right_side": {
"pins": [
"SW1",
"BTST",
"REGN",
"PGND1",
"SYS1",
"BAT1",
"QON",
"TS"
],
"direction": "top-to-bottom"
}
},
"pin_spacing": 0.2,
"pin_styles": {
"pin1": {},
"pin2": {},
"pin3": {},
"pin4": {},
"pin5": {},
"pin6": {},
"pin7": {},
"pin8": {},
"pin10": {},
"pin12": {},
"pin13": {},
"pin15": {},
"pin17": {},
"pin19": {},
"pin21": {},
"pin22": {},
"pin23": {}
},
"port_labels": {
"pin1": "VBUS",
"pin2": "USB_D_POS",
"pin3": "USB_D_NEG",
"pin4": "STAT",
"pin5": "I2C_SCL",
"pin6": "I2C_SDA",
"pin7": "INT",
"pin8": "OTG",
"pin9": "CE",
"pin10": "ILIM",
"pin11": "TS",
"pin12": "QON",
"pin13": "BAT1",
"pin14": "BAT2",
"pin15": "SYS1",
"pin16": "SYS2",
"pin17": "PGND1",
"pin18": "PGND2",
"pin19": "SW1",
"pin20": "SW2",
"pin21": "BTST",
"pin22": "REGN",
"pin23": "PMID",
"pin24": "DSEL",
"pin25": "PAD"
},
"source_component_id": "source_component_0",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_0",
"text": "BQ25895RTWR",
"schematic_component_id": "schematic_component_0",
"anchor": "left",
"rotation": 0,
"position": {
"x": -1.3,
"y": -3.88
},
"color": "#006464",
"font_size": 0.18
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_1",
"text": "U1",
"schematic_component_id": "schematic_component_0",
"anchor": "left",
"rotation": 0,
"position": {
"x": -1.3,
"y": 3.88
},
"color": "#006464",
"font_size": 0.18
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_1",
"center": {
"x": -10.8,
"y": 1.4
},
"rotation": 0,
"size": {
"width": 1.6,
"height": 1
},
"port_arrangement": {
"right_side": {
"pins": [
"pin1",
"pin2",
"pin3",
"pin4"
],
"direction": "top-to-bottom"
}
},
"pin_spacing": 0.2,
"port_labels": {
"pin1": "VBUS",
"pin2": "D_POS",
"pin3": "D_NEG",
"pin4": "GND"
},
"source_component_id": "source_component_1",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_2",
"text": "USB Input",
"schematic_component_id": "schematic_component_1",
"anchor": "left",
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