tscircuit/ti
ti tscircuit library
- Version
- 1.0.85
- License
- unset
- Stars
- 0
dist/lib/simulations/DRV8876-driver-pwm-operation-with-current-feedback/circuit.json
PCB
Schematic
[
{
"type": "source_group",
"source_group_id": "source_group_0",
"is_subcircuit": true,
"was_automatically_named": true,
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_0",
"name": "EN",
"pin_number": 1,
"port_hints": [
"EN",
"pin1",
"1"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_1",
"name": "PH",
"pin_number": 2,
"port_hints": [
"PH",
"pin2",
"2"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_2",
"name": "nSLEEP",
"pin_number": 3,
"port_hints": [
"nSLEEP",
"pin3",
"3"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_3",
"name": "nFAULT",
"pin_number": 4,
"port_hints": [
"nFAULT",
"pin4",
"4"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_port",
"source_port_id": "source_port_4",
"name": "VREF",
"pin_number": 5,
"port_hints": [
"VREF",
"pin5",
"5"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_port",
"source_port_id": "source_port_5",
"name": "IPROPI",
"pin_number": 6,
"port_hints": [
"IPROPI",
"pin6",
"6"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_port",
"source_port_id": "source_port_6",
"name": "IMODE",
"pin_number": 7,
"port_hints": [
"IMODE",
"pin7",
"7"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_7",
"name": "OUT1",
"pin_number": 8,
"port_hints": [
"OUT1",
"pin8",
"8"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_8",
"name": "PGND",
"pin_number": 9,
"port_hints": [
"PGND",
"pin9",
"9"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_9",
"name": "OUT2",
"pin_number": 10,
"port_hints": [
"OUT2",
"pin10",
"10"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net14"
},
{
"type": "source_port",
"source_port_id": "source_port_10",
"name": "VM",
"pin_number": 11,
"port_hints": [
"VM",
"pin11",
"11"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_11",
"name": "VCP",
"pin_number": 12,
"port_hints": [
"VCP",
"pin12",
"12"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_port",
"source_port_id": "source_port_12",
"name": "CPH",
"pin_number": 13,
"port_hints": [
"CPH",
"pin13",
"13"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_port",
"source_port_id": "source_port_13",
"name": "CPL",
"pin_number": 14,
"port_hints": [
"CPL",
"pin14",
"14"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_port",
"source_port_id": "source_port_14",
"name": "GND",
"pin_number": 15,
"port_hints": [
"GND",
"pin15",
"15"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_15",
"name": "PMODE",
"pin_number": 16,
"port_hints": [
"PMODE",
"pin16",
"16"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_16",
"name": "PAD",
"pin_number": 17,
"port_hints": [
"PAD",
"pin17",
"17"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_17",
"name": "top",
"port_hints": [
"top"
],
"source_component_id": "source_manually_placed_via_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_18",
"name": "bottom",
"port_hints": [
"bottom"
],
"source_component_id": "source_manually_placed_via_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_19",
"name": "pin1",
"port_hints": [
"pin1"
],
"source_component_id": "source_manually_placed_via_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_manually_placed_via",
"source_manually_placed_via_id": "source_manually_placed_via_0",
"source_group_id": "source_group_0",
"source_net_id": "",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_20",
"name": "top",
"port_hints": [
"top"
],
"source_component_id": "source_manually_placed_via_1",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_21",
"name": "bottom",
"port_hints": [
"bottom"
],
"source_component_id": "source_manually_placed_via_1",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_22",
"name": "pin1",
"port_hints": [
"pin1"
],
"source_component_id": "source_manually_placed_via_1",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_manually_placed_via",
"source_manually_placed_via_id": "source_manually_placed_via_1",
"source_group_id": "source_group_0",
"source_net_id": "",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_23",
"name": "top",
"port_hints": [
"top"
],
"source_component_id": "source_manually_placed_via_2",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_24",
"name": "bottom",
"port_hints": [
"bottom"
],
"source_component_id": "source_manually_placed_via_2",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_25",
"name": "pin1",
"port_hints": [
"pin1"
],
"source_component_id": "source_manually_placed_via_2",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_manually_placed_via",
"source_manually_placed_via_id": "source_manually_placed_via_2",
"source_group_id": "source_group_0",
"source_net_id": "",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_26",
"name": "top",
"port_hints": [
"top"
],
"source_component_id": "source_manually_placed_via_3",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_27",
"name": "bottom",
"port_hints": [
"bottom"
],
"source_component_id": "source_manually_placed_via_3",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_28",
"name": "pin1",
"port_hints": [
"pin1"
],
"source_component_id": "source_manually_placed_via_3",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_manually_placed_via",
"source_manually_placed_via_id": "source_manually_placed_via_3",
"source_group_id": "source_group_0",
"source_net_id": "",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_component",
"source_component_id": "source_component_0",
"ftype": "simple_chip",
"name": "U1",
"manufacturer_part_number": "DRV8876",
"supplier_part_numbers": {
"jlcpcb": [
"C575551"
]
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_29",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"terminal1",
"1"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_30",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"terminal2",
"2"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_1",
"ftype": "simple_voltage_source",
"name": "V_VM",
"voltage": 24,
"supplier_part_numbers": {},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_31",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"terminal1",
"1"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_32",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"terminal2",
"2"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_2",
"ftype": "simple_voltage_source",
"name": "V_CC",
"voltage": 3.3,
"supplier_part_numbers": {},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_33",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"terminal1",
"1"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_port",
"source_port_id": "source_port_34",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"terminal2",
"2"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_3",
"ftype": "simple_voltage_source",
"name": "V_EN_PWM",
"voltage": 3.3,
"frequency": 50000,
"wave_shape": "square",
"duty_cycle": 0.25,
"pulse_delay": 1.2,
"rise_time": 0.00009999999999999999,
"fall_time": 0.00009999999999999999,
"supplier_part_numbers": {},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_35",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"terminal1",
"1"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_port",
"source_port_id": "source_port_36",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"terminal2",
"2"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_4",
"ftype": "simple_voltage_source",
"name": "V_SLEEP",
"voltage": 3.3,
"wave_shape": "square",
"pulse_delay": 0.05,
"rise_time": 0.00009999999999999999,
"fall_time": 0.00009999999999999999,
"pulse_width": 4,
"period": 5,
"supplier_part_numbers": {},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_37",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_38",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_5",
"ftype": "simple_capacitor",
"name": "C_VM_BYPASS",
"supplier_part_numbers": {
"jlcpcb": [
"C1525",
"C307331",
"C60474"
]
},
"capacitance": 1e-7,
"display_capacitance": "0.1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_39",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_40",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_6",
"ftype": "simple_capacitor",
"name": "C_VM_BULK",
"supplier_part_numbers": {
"jlcpcb": [
"C96123",
"C403725",
"C172351"
]
},
"capacitance": 0.000047,
"display_capacitance": "47uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_41",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_port",
"source_port_id": "source_port_42",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_component",
"source_component_id": "source_component_7",
"ftype": "simple_capacitor",
"name": "C_VCP",
"supplier_part_numbers": {
"jlcpcb": [
"C1525",
"C307331",
"C60474"
]
},
"capacitance": 1e-7,
"display_capacitance": "0.1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_43",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_8",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_port",
"source_port_id": "source_port_44",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_8",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_component",
"source_component_id": "source_component_8",
"ftype": "simple_capacitor",
"name": "C_CP",
"supplier_part_numbers": {
"jlcpcb": [
"C1532",
"C337699",
"C77023"
]
},
"capacitance": 2.2e-8,
"display_capacitance": "0.022uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_45",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_46",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_component",
"source_component_id": "source_component_9",
"ftype": "simple_resistor",
"name": "R_REF1",
"supplier_part_numbers": {
"jlcpcb": [
"C25759",
"C163487",
"C324823"
]
},
"resistance": 16000,
"display_resistance": "16kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_47",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_10",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_port",
"source_port_id": "source_port_48",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_10",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_10",
"ftype": "simple_resistor",
"name": "R_REF2",
"supplier_part_numbers": {
"jlcpcb": [
"C166559"
]
},
"resistance": 50000,
"display_resistance": "50kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_49",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_port",
"source_port_id": "source_port_50",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_11",
"ftype": "simple_resistor",
"name": "R_IPROPI",
"supplier_part_numbers": {
"jlcpcb": [
"C4109",
"C2909344",
"C25552"
]
},
"resistance": 2000,
"display_resistance": "2kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_51",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"1",
"left"
],
"source_component_id": "source_component_12",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_port",
"source_port_id": "source_port_52",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"2",
"right"
],
"source_component_id": "source_component_12",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_12",
"ftype": "simple_capacitor",
"name": "C_IPROPI",
"supplier_part_numbers": {
"jlcpcb": [
"C15195",
"C5137480",
"C60133"
]
},
"capacitance": 1e-8,
"display_capacitance": "10nF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_53",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_13",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_54",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_13",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_component",
"source_component_id": "source_component_13",
"ftype": "simple_resistor",
"name": "R_NFAULT_PULLUP",
"supplier_part_numbers": {
"jlcpcb": [
"C25744",
"C60490",
"C25531"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_55",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"1"
],
"source_component_id": "source_component_14",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_56",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"2"
],
"source_component_id": "source_component_14",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_14",
"ftype": "simple_ammeter",
"name": "I_MOTOR_PROBE",
"supplier_part_numbers": {},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_57",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_15",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_58",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_15",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net13"
},
{
"type": "source_component",
"source_component_id": "source_component_15",
"name": "L_MOTOR",
"ftype": "simple_inductor",
"inductance": "10mH",
"display_inductance": "10mH",
"supplier_part_numbers": {
"jlcpcb": []
},
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_59",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_16",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net13"
},
{
"type": "source_port",
"source_port_id": "source_port_60",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_16",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net14"
},
{
"type": "source_component",
"source_component_id": "source_component_16",
"ftype": "simple_resistor",
"name": "R_MOTOR",
"supplier_part_numbers": {
"jlcpcb": [
"C4198",
"C2907132",
"C137758"
]
},
"resistance": 24,
"display_resistance": "24Ω",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_net",
"source_net_id": "source_net_0",
"name": "VM",
"member_source_group_ids": [],
"is_ground": false,
"is_power": true,
"is_positive_voltage_source": true,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_net",
"source_net_id": "source_net_1",
"name": "GND",
"member_source_group_ids": [],
"is_ground": true,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_net",
"source_net_id": "source_net_2",
"name": "VCC",
"member_source_group_ids": [],
"is_ground": false,
"is_power": true,
"is_positive_voltage_source": true,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_net",
"source_net_id": "source_net_3",
"name": "VREF",
"member_source_group_ids": [],
"is_ground": false,
"is_power": true,
"is_positive_voltage_source": true,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_net",
"source_net_id": "source_net_4",
"name": "IPROPI",
"member_source_group_ids": [],
"is_ground": false,
"is_power": false,
"is_positive_voltage_source": false,
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_refdes_convention_warning",
"warning_type": "source_refdes_convention_warning",
"message": "Component I_MOTOR_PROBE has ftype=\"simple_ammeter\" but reference designator should start with A",
"source_component_id": "source_component_14",
"refdes": "I_MOTOR_PROBE",
"source_component_ftype": "simple_ammeter",
"expected_prefixes": [
"A"
],
"actual_prefix": "I",
"source_refdes_convention_warning_id": "source_refdes_convention_warning_0"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_0",
"connected_source_port_ids": [
"source_port_55",
"source_port_7"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".I_MOTOR_PROBE > .pos to U1.OUT1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_0",
"message": "<trace#5376(from:.I_MOTOR_PROBE > .pos to:U1.OUT1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_0",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_1",
"connected_source_port_ids": [
"source_port_56",
"source_port_57"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": ".I_MOTOR_PROBE > .neg to L_MOTOR.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_1",
"message": "<trace#5377(from:.I_MOTOR_PROBE > .neg to:L_MOTOR.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_1",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_2",
"connected_source_port_ids": [
"source_port_29"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_VM.pin1 to net.VM",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_2",
"message": "<trace#5204(from:V_VM.pin1 to:net.VM) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_2",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_3",
"connected_source_port_ids": [
"source_port_30"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_VM.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_3",
"message": "<trace#5205(from:V_VM.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_3",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_4",
"connected_source_port_ids": [
"source_port_31"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_CC.pin1 to net.VCC",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_4",
"message": "<trace#5206(from:V_CC.pin1 to:net.VCC) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_4",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_5",
"connected_source_port_ids": [
"source_port_32"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_CC.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_5",
"message": "<trace#5207(from:V_CC.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_5",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_6",
"connected_source_port_ids": [
"source_port_33",
"source_port_0"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_EN_PWM.pin1 to U1.EN",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net5"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_6",
"message": "<trace#5208(from:V_EN_PWM.pin1 to:U1.EN) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_6",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_7",
"connected_source_port_ids": [
"source_port_34"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_EN_PWM.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_7",
"message": "<trace#5209(from:V_EN_PWM.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_7",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_8",
"connected_source_port_ids": [
"source_port_35",
"source_port_2"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_SLEEP.pin1 to U1.nSLEEP",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net6"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_8",
"message": "<trace#5210(from:V_SLEEP.pin1 to:U1.nSLEEP) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_8",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_9",
"connected_source_port_ids": [
"source_port_36"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "V_SLEEP.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_9",
"message": "<trace#5211(from:V_SLEEP.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_9",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_10",
"connected_source_port_ids": [
"source_port_10"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.VM to net.VM",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_10",
"message": "<trace#5212(from:U1.VM to:net.VM) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_10",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_11",
"connected_source_port_ids": [
"source_port_1"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.PH to net.VCC",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_11",
"message": "<trace#5213(from:U1.PH to:net.VCC) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_11",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_12",
"connected_source_port_ids": [
"source_port_15"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.PMODE to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_12",
"message": "<trace#5214(from:U1.PMODE to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_12",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_13",
"connected_source_port_ids": [
"source_port_6"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.IMODE to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_13",
"message": "<trace#5215(from:U1.IMODE to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_13",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_14",
"connected_source_port_ids": [
"source_port_14"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.GND to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_14",
"message": "<trace#5216(from:U1.GND to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_14",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_15",
"connected_source_port_ids": [
"source_port_8"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.PGND to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_15",
"message": "<trace#5217(from:U1.PGND to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_15",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_16",
"connected_source_port_ids": [
"source_port_16"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.PAD to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_16",
"message": "<trace#5218(from:U1.PAD to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_16",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_17",
"connected_source_port_ids": [
"source_port_37"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_VM_BYPASS.pin1 to net.VM",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_17",
"message": "<trace#5219(from:C_VM_BYPASS.pin1 to:net.VM) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_17",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_18",
"connected_source_port_ids": [
"source_port_38"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_VM_BYPASS.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_18",
"message": "<trace#5220(from:C_VM_BYPASS.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_18",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_19",
"connected_source_port_ids": [
"source_port_39"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_VM_BULK.pin1 to net.VM",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_19",
"message": "<trace#5221(from:C_VM_BULK.pin1 to:net.VM) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_19",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_20",
"connected_source_port_ids": [
"source_port_40"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_VM_BULK.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_20",
"message": "<trace#5222(from:C_VM_BULK.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_20",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_21",
"connected_source_port_ids": [
"source_port_11",
"source_port_41"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "U1.VCP to C_VCP.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net7"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_21",
"message": "<trace#5223(from:U1.VCP to:C_VCP.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_21",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_22",
"connected_source_port_ids": [
"source_port_42"
],
"connected_source_net_ids": [
"source_net_0"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_VCP.pin2 to net.VM",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_22",
"message": "<trace#5224(from:C_VCP.pin2 to:net.VM) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_22",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_23",
"connected_source_port_ids": [
"source_port_12",
"source_port_43"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "U1.CPH to C_CP.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net8"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_23",
"message": "<trace#5225(from:U1.CPH to:C_CP.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_23",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_24",
"connected_source_port_ids": [
"source_port_13",
"source_port_44"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "U1.CPL to C_CP.pin2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net9"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_24",
"message": "<trace#5226(from:U1.CPL to:C_CP.pin2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_24",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_25",
"connected_source_port_ids": [
"source_port_45"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_REF1.pin1 to net.VCC",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_25",
"message": "<trace#5227(from:R_REF1.pin1 to:net.VCC) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_25",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_26",
"connected_source_port_ids": [
"source_port_46"
],
"connected_source_net_ids": [
"source_net_3"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_REF1.pin2 to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_26",
"message": "<trace#5228(from:R_REF1.pin2 to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_26",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_27",
"connected_source_port_ids": [
"source_port_47"
],
"connected_source_net_ids": [
"source_net_3"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_REF2.pin1 to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_27",
"message": "<trace#5229(from:R_REF2.pin1 to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_27",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_28",
"connected_source_port_ids": [
"source_port_48"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_REF2.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_28",
"message": "<trace#5230(from:R_REF2.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_28",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_29",
"connected_source_port_ids": [
"source_port_4"
],
"connected_source_net_ids": [
"source_net_3"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.VREF to net.VREF",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net10"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_29",
"message": "<trace#5231(from:U1.VREF to:net.VREF) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_29",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_30",
"connected_source_port_ids": [
"source_port_5"
],
"connected_source_net_ids": [
"source_net_4"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.IPROPI to net.IPROPI",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_30",
"message": "<trace#5232(from:U1.IPROPI to:net.IPROPI) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_30",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_31",
"connected_source_port_ids": [
"source_port_49"
],
"connected_source_net_ids": [
"source_net_4"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_IPROPI.pin1 to net.IPROPI",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_31",
"message": "<trace#5233(from:R_IPROPI.pin1 to:net.IPROPI) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_31",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_32",
"connected_source_port_ids": [
"source_port_50"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_IPROPI.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_32",
"message": "<trace#5234(from:R_IPROPI.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_32",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_33",
"connected_source_port_ids": [
"source_port_51"
],
"connected_source_net_ids": [
"source_net_4"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_IPROPI.pin1 to net.IPROPI",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net11"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_33",
"message": "<trace#5235(from:C_IPROPI.pin1 to:net.IPROPI) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_33",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_34",
"connected_source_port_ids": [
"source_port_52"
],
"connected_source_net_ids": [
"source_net_1"
],
"subcircuit_id": "subcircuit_source_group_0",
"max_length": null,
"display_name": "C_IPROPI.pin2 to net.GND",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_34",
"message": "<trace#5236(from:C_IPROPI.pin2 to:net.GND) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_34",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_35",
"connected_source_port_ids": [
"source_port_53"
],
"connected_source_net_ids": [
"source_net_2"
],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_NFAULT_PULLUP.pin1 to net.VCC",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_35",
"message": "<trace#5237(from:R_NFAULT_PULLUP.pin1 to:net.VCC) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_35",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_36",
"connected_source_port_ids": [
"source_port_54",
"source_port_3"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_NFAULT_PULLUP.pin2 to U1.nFAULT",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net12"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_36",
"message": "<trace#5238(from:R_NFAULT_PULLUP.pin2 to:U1.nFAULT) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_36",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_37",
"connected_source_port_ids": [
"source_port_7",
"source_port_55"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "U1.OUT1 to I_MOTOR_PROBE.pos",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_37",
"message": "<trace#5239(from:U1.OUT1 to:I_MOTOR_PROBE.pos) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_37",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_38",
"connected_source_port_ids": [
"source_port_56",
"source_port_57"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "I_MOTOR_PROBE.neg to L_MOTOR.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_38",
"message": "<trace#5240(from:I_MOTOR_PROBE.neg to:L_MOTOR.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_38",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_39",
"connected_source_port_ids": [
"source_port_58",
"source_port_59"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "L_MOTOR.pin2 to R_MOTOR.pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net13"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_39",
"message": "<trace#5241(from:L_MOTOR.pin2 to:R_MOTOR.pin1) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_39",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_40",
"connected_source_port_ids": [
"source_port_60",
"source_port_9"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"display_name": "R_MOTOR.pin2 to U1.OUT2",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net14"
},
{
"type": "source_unnamed_trace_warning",
"source_unnamed_trace_warning_id": "source_unnamed_trace_warning_40",
"message": "<trace#5242(from:R_MOTOR.pin2 to:U1.OUT2) /> is missing a name. Add a name prop to make the trace easier to identify.",
"source_trace_id": "source_trace_40",
"subcircuit_id": "subcircuit_source_group_0",
"warning_type": "source_unnamed_trace_warning"
},
{
"type": "simulation_spice_subcircuit",
"simulation_spice_subcircuit_id": "simulation_spice_subcircuit_0",
"source_component_id": "source_component_0",
"spice_pin_to_source_port_map": {
"CPH": "source_port_12",
"CPL": "source_port_13",
"EN_IN1": "source_port_0",
"GND": "source_port_14",
"IMODE": "source_port_6",
"IPROPI": "source_port_5",
"nFAULT": "source_port_3",
"nSLEEP": "source_port_2",
"OUT1": "source_port_7",
"OUT2": "source_port_9",
"PGND": "source_port_8",
"PAD": "source_port_16",
"PH_IN2": "source_port_1",
"PMODE": "source_port_15",
"VCP": "source_port_11",
"VM": "source_port_10",
"VREF": "source_port_4"
},
"subcircuit_source": "* DRV8876\n*****************************************************************************\n* (C) Copyright 2018 Texas Instruments Incorporated. All rights reserved.\n*****************************************************************************\n** This model is designed as an aid for customers of Texas Instruments.\n** TI and its licensors and suppliers make no warranties, either expressed\n** or implied, with respect to this model, including the warranties of\n** merchantability or fitness for a particular purpose. The model is\n** provided solely on an \"as is\" basis. The entire risk as to its quality\n** and performance is with the customer.\n*****************************************************************************\n*\n** Released by: WEBENCH Design Center, Texas Instruments Inc.\n* Part: DRV8876\n* Date: 28MAY2018\n* Model Type: Transient\n* Simulator: PSPICE\n* Simulator Version: 16.2.0.s003\n* EVM Order Number:\n* EVM Users Guide:\n* Datasheet:\n*\n* Model Version: Final 1.00\n*\n*****************************************************************************\n*\n* Updates:\n*\n* Final 1.00\n* Release to Web\n*\n*****************************************************************************\n* Model Usage Notes:\n*\n* A. Features that have been modelled\n*\t1. Control Mode\n*\t2. Current Senses\n*\t3. Current Chopping Mode\n*\t4. Over Current Respond\n*\t5. Rds\n*\t6. UVLO, Logic Level, Tri-Level Logic, Quad-Level Logic\n*\t\n*\n* B. Model Limitations and Features that haven't been modelled\n*\t1. Thermal operation and quiscent current are not modelled \n* 2. Charge pump operation\n*\n*****************************************************************************\n*$\n.SUBCKT DRV8876_TRANS CPH CPL EN_IN1 GND IMODE IPROPI nFAULT nSLEEP OUT1 OUT2 PGND PAD\n+ PH_IN2 PMODE VCP VM VREF \nR_R9 GND CPH 1MEG TC=0,0 \nR_R4 GND PMODE 44k TC=0,0 \nX_S1 FAULT 0 nFAULT GND DRV8876_S1 \nX_U_ISENSE_U50 U_ISENSE_N376760 RETRY U_ISENSE_N269698 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U38 U_ISENSE_TOFF U_ISENSE_TOFF_DEL BUF_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=2u\nV_U_ISENSE_V1 U_ISENSE_V1V 0 1Vdc\nX_U_ISENSE_U23 U_ISENSE_N156704 U_ISENSE_N157536 U_ISENSE_CUR_TRIP\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U68 U_ISENSE_CUR_LIM2B U_ISENSE_N411658 INV_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nC_U_ISENSE_C3 0 U_ISENSE_N180191 10n TC=0,0 \nE_U_ISENSE_ABM1 U_ISENSE_N246869 0 VALUE { IF(V(VISENSE)>{ILIM},1,0) \n+ }\nX_U_ISENSE_U49 U_ISENSE_ILIM12 U_ISENSE_ILIM1 U_ISENSE_ILIM11\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nE_U_ISENSE_ABM3 U_ISENSE_N243273 0 VALUE { IF(V(IMON2)>{ILIM},1,0) }\nX_U_ISENSE_U56 U_ISENSE_N269698 U_ISENSE_N269804 U_ISENSE_LIM_CUR2\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U28 U_ISENSE_N183649 RETRY U_ISENSE_N183681 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nE_U_ISENSE_ABM2 U_ISENSE_N241780 0 VALUE { IF(V(IMON1)>{ILIM},1,0) }\nX_U_ISENSE_U69 U_ISENSE_N343928 U_ISENSE_N429471 BUF_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=1u\nX_U_ISENSE_U66 U_ISENSE_ILIM11 U_ISENSE_TRETRY U_ISENSE_N183649 N183653\n+ srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_ISENSE_U15 U_ISENSE_N246869 U_ISENSE_N249666 U_ISENSE_ILIM12\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U75 U_ISENSE_N411658 U_ISENSE_LIM_CUR2\n+ U_ISENSE_LIM2_CUR_BUFB NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U71 U_ISENSE_LIM_CUR1 U_ISENSE_CUR_LIM1B INV_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=1u\nX_U_ISENSE_S2 U_ISENSE_N180351 0 U_ISENSE_N180191 0 ISENSE_U_ISENSE_S2 \nX_U_ISENSE_U24 U_ISENSE_N441309 U_ISENSE_LIM1_CUR_BUFB\n+ U_ISENSE_LIM2_CUR_BUFB U_ISENSE_N443070 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nX_U_ISENSE_U43 U_ISENSE_N159306 U_ISENSE_PRE_HS2_BUF\n+ BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=2u\nX_U_ISENSE_U22 U_ISENSE_N163934 PRE_HS2 U_ISENSE_CUR_LIM2B HS2\n+ AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U64 U_ISENSE_TRETRY_DEL U_ISENSE_TRETRY_DELB INV_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U26 U_ISENSE_N152518 U_ISENSE_N154160 U_ISENSE_N177215\n+ U_ISENSE_V1V U_ISENSE_TOFF_DEL U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U42 U_ISENSE_N159306 N235259 PRE_HS2 U_ISENSE_V1V\n+ U_ISENSE_PRE_HS2_BUF U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nC_U_ISENSE_C1 0 U_ISENSE_N152348 10n TC=0,0 \nX_U_ISENSE_U6 U_ISENSE_N152348 U_ISENSE_V1V d_d_drv88xx PARAMS:\nX_U_ISENSE_U30 U_ISENSE_N185137 LATCH U_ISENSE_N185169 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U7 U_ISENSE_N152348 U_ISENSE_TOFF BUF_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U_ISENSE_U47 U_ISENSE_N243273 HALF_BRDG U_ISENSE_ILIM2 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U13 U_ISENSE_N230041 U_ISENSE_N159306 U_ISENSE_N161337\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nG_U_ISENSE_ABMII1 U_ISENSE_V1V U_ISENSE_N152348 VALUE {\n+ IF(V(U_ISENSE_N152518)>0.5,200u,0) }\nX_U_ISENSE_U62 U_ISENSE_TRETRY U_ISENSE_TRETRY_DEL BUF_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=0.5u\nX_U_ISENSE_U59 U_ISENSE_N220871 U_ISENSE_CUR_TRIP U_ISENSE_LIM_CUR1\n+ U_ISENSE_LIM_CUR2 FAULT OR4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U73 U_ISENSE_CUR_LIM1B U_ISENSE_N437423 INV_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U74 U_ISENSE_N437423 U_ISENSE_LIM_CUR1\n+ U_ISENSE_LIM1_CUR_BUFB NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U17 U_ISENSE_CUR_TRIP U_ISENSE_N163934 INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U18 U_ISENSE_N230041 U_ISENSE_PRE_HS1_BUF\n+ BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=2u\nX_U_ISENSE_U45 U_ISENSE_ILIM12 U_ISENSE_N251988 U_ISENSE_CUR_LIM\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U51 U_ISENSE_ILIM12 U_ISENSE_ILIM2 U_ISENSE_ILIM22\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U31 U_ISENSE_N185137 N185141 U_ISENSE_ILIM11 U_ISENSE_V1V\n+ U_ISENSE_N185125 U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nX_U_ISENSE_U52 U_ISENSE_N269762 LATCH U_ISENSE_N269804 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U16 U_ISENSE_N241780 HALF_BRDG U_ISENSE_ILIM1 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_ISENSE_V3 U_ISENSE_N180167 0 1Vdc\nX_U_ISENSE_U5 U_ISENSE_ITRIP FIXOFF U_ISENSE_N177215 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U36 U_ISENSE_LIM_CUR2 U_ISENSE_CUR_TRIP PRE_LS2 LS2\n+ OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U67 U_ISENSE_ILIM22 U_ISENSE_TRETRY U_ISENSE_N376760 N376766\n+ srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_ISENSE_U11 U_ISENSE_N157504 CBC U_ISENSE_N157536 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U60 U_ISENSE_N180191 U_ISENSE_TRETRY BUF_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5\nX_U_ISENSE_U53 U_ISENSE_N269762 N269768 U_ISENSE_ILIM22 U_ISENSE_V1V\n+ U_ISENSE_N269758 U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nG_U_ISENSE_ABMII2 U_ISENSE_N180167 U_ISENSE_N180191 VALUE {\n+ IF(V(U_ISENSE_N180213)>0.5,2.5u,0) }\nX_U_ISENSE_U40 VM_UV_OK U_ISENSE_N220871 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U33 U_ISENSE_N183681 U_ISENSE_N185169 U_ISENSE_LIM_CUR1\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U3 U_ISENSE_N443070 U_ISENSE_ITRIP BUF_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=1.7u\nX_U_ISENSE_U65 U_ISENSE_TRETRY_DEL U_ISENSE_N381777 U_ISENSE_N180351\n+ U_ISENSE_N180213 srlatchrhp_basic_gen PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_ISENSE_U63 U_ISENSE_CUR_LIM RETRY RETRY U_ISENSE_N343928\n+ AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U32 NSLEEP_H VM_UV_OK U_ISENSE_N185125 NAND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U9 U_ISENSE_N155740 N155826 U_ISENSE_ITRIP U_ISENSE_V1V\n+ U_ISENSE_TOFF U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nX_U_ISENSE_U10 U_ISENSE_N155740 FIXOFF U_ISENSE_N156704 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U12 U_ISENSE_N157504 N157508 U_ISENSE_ITRIP U_ISENSE_V1V\n+ U_ISENSE_N161337 U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nX_U_ISENSE_U46 HALF_BRDG U_ISENSE_N249666 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U54 NSLEEP_H VM_UV_OK U_ISENSE_N269758 NAND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U21 U_ISENSE_CUR_LIM1B PRE_HS1 U_ISENSE_N163934 HS1\n+ AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U44 U_ISENSE_ILIM1 U_ISENSE_ILIM2 U_ISENSE_N251988\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U8 U_ISENSE_ITRIP U_ISENSE_ITRIPB INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U34 U_ISENSE_N429471 U_ISENSE_N343928 U_ISENSE_N381777\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U41 U_ISENSE_N230041 N228169 PRE_HS1 U_ISENSE_V1V\n+ U_ISENSE_PRE_HS1_BUF U_ISENSE_V0V dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nV_U_ISENSE_V2 U_ISENSE_V0V 0 0Vdc\nX_U_ISENSE_U70 U_ISENSE_TRETRY U_ISENSE_TRETRY_DELB U_ISENSE_TRETRY_OS\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_ISENSE_U20 U_ISENSE_N180191 U_ISENSE_N180167 d_d_drv88xx PARAMS:\nX_U_ISENSE_S1 U_ISENSE_N154160 0 U_ISENSE_N152348 0 ISENSE_U_ISENSE_S1 \nX_U_ISENSE_U72 U_ISENSE_LIM_CUR2 U_ISENSE_CUR_LIM2B INV_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=1u\nX_U_ISENSE_U1 IPROPI VREF U_ISENSE_N441309 COMP_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5\nX_U_ISENSE_U35 U_ISENSE_LIM_CUR1 U_ISENSE_CUR_TRIP PRE_LS1 LS1\n+ OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nR_R1 GND EN_IN1 100k TC=0,0 \nX_U6 GND PMODE d_d_drv88xx PARAMS:\nV_V1 V5INT GND 5\nR_R2 GND PH_IN2 100k TC=0,0 \nR_R8 GND CPL 1MEG TC=0,0 \nR_R10 GND VCP 1MEG TC=0,0 \nX_U4 GND PH_IN2 d_d_drv88xx PARAMS:\nX_U3 GND EN_IN1 d_d_drv88xx PARAMS:\nR_R5 PMODE V5INT 156k TC=0,0 \nR_R6 GND IMODE 136k TC=0,0 \nR_R7 IMODE V5INT 68k TC=0,0 \nR_R3 GND NSLEEP 100k TC=0,0 \nX_U7 GND IMODE d_d_drv88xx PARAMS:\nV_U_LOGIC_V23 U_LOGIC_N42309 0 2Vdc\nX_U_LOGIC_U67 U_LOGIC_TSLEEP_OK U_LOGIC_N69191 U_LOGIC_N69139\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U37 U_LOGIC_N25826 U_LOGIC_N25834 INV_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n\nX_U_LOGIC_U43 U_LOGIC_N25838 U_LOGIC_N26138 U_LOGIC_IMOD_L1B\n+ U_LOGIC_IMOD_L2 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U70 U_LOGIC_NSLEEP_L U_LOGIC_N84898 U_LOGIC_OUT1_HIZ\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nE_U_LOGIC_E5 U_LOGIC_PH_IN2_INT 0 PH_IN2 GND 1\nX_U_LOGIC_U103 U_LOGIC_N268778 U_LOGIC_N268778 PRE_HS1 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V2 U_LOGIC_N01515 0 100m\nX_U_LOGIC_U78 U_LOGIC_N125074 U_LOGIC_N125098 U_LOGIC_N125146\n+ U_LOGIC_N125170 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U98 U_LOGIC_VM_UV NSLEEP_H U_LOGIC_N223410 OR2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U80 U_LOGIC_N102715 U_LOGIC_PH_EN U_LOGIC_N116935\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U20 U_LOGIC_N09353 U_LOGIC_N09361 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V8 U_LOGIC_N09191 0 180m\nX_U_LOGIC_U24 U_LOGIC_EN_IN1_INT U_LOGIC_N11855 U_LOGIC_N11903\n+ U_LOGIC_N13435 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_LOGIC_U72 U_LOGIC_EN_IN1_H U_LOGIC_PH_IN2_H U_LOGIC_N83638\n+ NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U54 U_LOGIC_TSLEEP_OK U_LOGIC_PMOD_L U_LOGIC_N56953\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V21 U_LOGIC_N31106 0 10m\nX_U_LOGIC_U63 U_LOGIC_TSLEEP_OK U_LOGIC_N179815 U_LOGIC_N67962\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U44 U_LOGIC_IMOD_L2 U_LOGIC_IMOD_L2B INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U100 U_LOGIC_PRE_LS1 U_LOGIC_PRE_LS1 PRE_LS1 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U84 U_LOGIC_EN_IN1_L U_LOGIC_N125258 U_LOGIC_N125300\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V10 U_LOGIC_N09317 0 1.1\nX_U_LOGIC_U81 U_LOGIC_PWM U_LOGIC_PH_IN2_H U_LOGIC_N117275\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V11 U_LOGIC_N11855 0 1.5\nX_U_LOGIC_U38 U_LOGIC_N25826 U_LOGIC_N26006 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U96 U_LOGIC_IMOD_L1 U_LOGIC_IMOD_L4 U_LOGIC_N69191\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nC_U_LOGIC_C1 0 U_LOGIC_N44249 1u TC=0,0 \nX_U_LOGIC_U101 U_LOGIC_PRE_LS2 U_LOGIC_PRE_LS2 PRE_LS2 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U56 U_LOGIC_PWM N65437 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N65361\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U79 U_LOGIC_PH_IN2_L U_LOGIC_EN_IN1_H U_LOGIC_N97045\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U90 U_LOGIC_OUT1_HIZ PRE_LS1 U_LOGIC_N133737 NOR2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U1 U_LOGIC_VM_INT U_LOGIC_N01225 U_LOGIC_N01515\n+ U_LOGIC_N01638 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_LOGIC_U3 U_LOGIC_N01763 U_LOGIC_N01638 VM_UV_OK AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U15 U_LOGIC_N09217 U_LOGIC_N09221 U_LOGIC_PMOD_L\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U31 U_LOGIC_PH_IN2_INT U_LOGIC_N16208 U_LOGIC_N16256\n+ U_LOGIC_N16036 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_LOGIC_U34 NSLEEP_H U_LOGIC_NSLEEP_L INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U39 U_LOGIC_IMOD_INT U_LOGIC_N26094 U_LOGIC_N26126\n+ U_LOGIC_N25830 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_LOGIC_U85 U_LOGIC_PWM U_LOGIC_EN_IN1_H U_LOGIC_N125098\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U46 U_LOGIC_N31126 U_LOGIC_N31130 INV_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n\nX_U_LOGIC_U21 U_LOGIC_PMOD_L U_LOGIC_PMOD_LB INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nE_U_LOGIC_E7 U_LOGIC_IMOD_INT 0 IMODE GND 1\nV_U_LOGIC_V13 U_LOGIC_N16208 0 1.5\nX_U_LOGIC_U27 U_LOGIC_EN_IN1_H U_LOGIC_EN_IN1_L INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U55 NSLEEP_H U_LOGIC_NSLEEP_H_BUF BUF_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=1u\nX_U_LOGIC_U57 U_LOGIC_TSLEEP_OK U_LOGIC_PMOD_H U_LOGIC_N65361\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U82 HALF_BRDG U_LOGIC_EN_IN1_L U_LOGIC_N118650 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V12 U_LOGIC_N11903 0 150m\nV_U_LOGIC_V19 U_LOGIC_N26126 0 10m\nX_U_LOGIC_U16 U_LOGIC_N09195 U_LOGIC_N09217 INV_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n\nX_U_LOGIC_U91 U_LOGIC_N133737 U_LOGIC_NSLEEP_H_BUF1 U_LOGIC_N268778\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nE_U_LOGIC_E6 U_LOGIC_NSLEEP_INT 0 NSLEEP GND 1\nX_U_LOGIC_U64 LATCH N68620 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N68544\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U22 U_LOGIC_N09357 U_LOGIC_N09361 U_LOGIC_PMOD_LB\n+ U_LOGIC_PMOD_HIZ AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U47 U_LOGIC_N31126 U_LOGIC_N31134 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U53 U_LOGIC_PH_EN N64335 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N56953\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U73 U_LOGIC_NSLEEP_L U_LOGIC_N87407 U_LOGIC_OUT2_HIZ\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U52 U_LOGIC_N44249 U_LOGIC_TSLEEP_OK BUF_DELAY_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n\nX_U_LOGIC_U58 HALF_BRDG N65980 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N65904\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U86 U_LOGIC_PH_IN2_H U_LOGIC_EN_IN1_H U_LOGIC_N125258\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U74 U_LOGIC_PWM U_LOGIC_N87397 U_LOGIC_N87407 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U10 U_LOGIC_IMOD_INT U_LOGIC_N25928 U_LOGIC_N25976\n+ U_LOGIC_N25826 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nV_U_LOGIC_V22 U_LOGIC_N31070 0 2\nV_U_LOGIC_V14 U_LOGIC_N16256 0 150m\nX_U_LOGIC_U17 U_LOGIC_N09195 U_LOGIC_N09221 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U23 U_LOGIC_PMOD_HIZ U_LOGIC_PMOD_L U_LOGIC_PMOD_H\n+ NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U94 U_LOGIC_IMOD_L1 U_LOGIC_IMOD_L2 U_LOGIC_N179815\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U65 U_LOGIC_TSLEEP_OK U_LOGIC_N68596 U_LOGIC_N68544\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U40 U_LOGIC_N25830 U_LOGIC_N25838 INV_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n\nX_U_LOGIC_U68 CBC N71310 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N71234\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V17 U_LOGIC_N25928 0 0.45\nX_U_LOGIC_U75 U_LOGIC_EN_IN1_H U_LOGIC_PH_IN2_H U_LOGIC_N87397\n+ NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U87 U_LOGIC_N125170 NSLEEP_H U_LOGIC_PRE_LS2 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U51 VM_UV_OK U_LOGIC_VM_UV INV_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nX_U_LOGIC_U35 U_LOGIC_NSLEEP_INT U_LOGIC_N18462 U_LOGIC_N18510\n+ U_LOGIC_N18290 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_LOGIC_U59 U_LOGIC_TSLEEP_OK U_LOGIC_PMOD_HIZ U_LOGIC_N65904\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U28 U_LOGIC_N16036 U_LOGIC_N16078 BUF_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=750n\nX_U_LOGIC_U60 U_LOGIC_PH_EN N67469 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N67393\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U18 U_LOGIC_PMOD_INT U_LOGIC_N09317 U_LOGIC_N09349\n+ U_LOGIC_N09353 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nE_U_LOGIC_E3 U_LOGIC_PMOD_INT 0 PMODE GND 1\nV_U_LOGIC_V15 U_LOGIC_N18462 0 1.5\nX_U_LOGIC_U88 HALF_BRDG U_LOGIC_PH_IN2_L U_LOGIC_N125146 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U48 U_LOGIC_IMOD_L3B U_LOGIC_IMOD_L1B U_LOGIC_IMOD_L2B\n+ U_LOGIC_IMOD_L4 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nG_U_LOGIC_ABMI1 U_LOGIC_N42309 U_LOGIC_N44249 VALUE { IF(V(NSLEEP_H) <\n+ 0.5 & V(VM_UV_OK) > 0.5,0.5m,0) }\nX_U_LOGIC_U2 U_LOGIC_N01638 U_LOGIC_N01763 BUF_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=10u\nX_U_LOGIC_U41 U_LOGIC_N25830 U_LOGIC_N26138 INV_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U29 U_LOGIC_N16078 U_LOGIC_N16078 U_LOGIC_PH_IN2_H\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U50 U_LOGIC_N31130 U_LOGIC_N31134 U_LOGIC_IMOD_L1B\n+ U_LOGIC_IMOD_L2B U_LOGIC_IMOD_L3 AND4_BASIC_GEN PARAMS: VDD=1 VSS=0\n+ VTHRESH=500E-3\nX_U_LOGIC_U25 U_LOGIC_N13435 U_LOGIC_N13457 BUF_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=750n\nX_U_LOGIC_S1 U_LOGIC_N223410 0 U_LOGIC_N44249 0 LOGIC_U_LOGIC_S1 \nX_U_LOGIC_U77 U_LOGIC_EN_IN1_L U_LOGIC_N97045 U_LOGIC_N102715\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U69 U_LOGIC_TSLEEP_OK U_LOGIC_N71286 U_LOGIC_N71234\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V18 U_LOGIC_N25976 0 10m\nX_U_LOGIC_U49 U_LOGIC_IMOD_L3 U_LOGIC_IMOD_L3B INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V9 U_LOGIC_N09349 0 180m\nV_U_LOGIC_V20 U_LOGIC_N26094 0 1.1\nX_U_LOGIC_U4 U_LOGIC_N44249 U_LOGIC_N42309 d_d_drv88xx PARAMS:\nX_U_LOGIC_U61 U_LOGIC_TSLEEP_OK U_LOGIC_PMOD_L U_LOGIC_N67393\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U95 U_LOGIC_IMOD_L3 U_LOGIC_IMOD_L4 U_LOGIC_N68596\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U76 U_LOGIC_N116935 U_LOGIC_N117275 U_LOGIC_N118650\n+ U_LOGIC_N119572 OR3_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U26 U_LOGIC_N13457 U_LOGIC_N13457 U_LOGIC_EN_IN1_H\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U9 U_LOGIC_PMOD_INT U_LOGIC_N09143 U_LOGIC_N09191\n+ U_LOGIC_N09195 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U_LOGIC_U71 U_LOGIC_PWM U_LOGIC_N83638 U_LOGIC_N84898 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U66 FIXOFF N69215 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N69139\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U92 U_LOGIC_OUT2_HIZ PRE_LS2 U_LOGIC_N140494 NOR2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V16 U_LOGIC_N18510 0 35m\nX_U_LOGIC_U36 U_LOGIC_N25834 U_LOGIC_N26006 U_LOGIC_IMOD_L1\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U99 U_LOGIC_NSLEEP_H_BUF U_LOGIC_NSLEEP_H_BUF1\n+ BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=0.2u\nX_U_LOGIC_U83 U_LOGIC_N119572 NSLEEP_H U_LOGIC_PRE_LS1 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U89 U_LOGIC_N125300 U_LOGIC_PH_EN U_LOGIC_N125074\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U42 U_LOGIC_IMOD_L1 U_LOGIC_IMOD_L1B INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U30 U_LOGIC_PH_IN2_H U_LOGIC_PH_IN2_L INV_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=500E-3\nE_U_LOGIC_E4 U_LOGIC_EN_IN1_INT 0 EN_IN1 GND 1\nX_U_LOGIC_U105 U_LOGIC_N278783 U_LOGIC_N278783 PRE_HS2 AND2_BASIC_GEN\n+ PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V7 U_LOGIC_N09143 0 0.65\nX_U_LOGIC_U19 U_LOGIC_N09353 U_LOGIC_N09357 INV_DELAY_BASIC_GEN PARAMS:\n+ VDD=1 VSS=0 VTHRESH=0.5 DELAY=10n\nX_U_LOGIC_U93 U_LOGIC_N140494 U_LOGIC_NSLEEP_H_BUF1 U_LOGIC_N278783\n+ AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nX_U_LOGIC_U32 U_LOGIC_N18290 NSLEEP_H BUF_DELAY_BASIC_GEN PARAMS: VDD=1\n+ VSS=0 VTHRESH=0.5 DELAY=1.11m\nX_U_LOGIC_U97 U_LOGIC_IMOD_L2 U_LOGIC_IMOD_L3 U_LOGIC_N71286\n+ OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nE_U_LOGIC_E1 U_LOGIC_VM_INT 0 VM GND 1\nX_U_LOGIC_U62 RETRY N68038 U_LOGIC_NSLEEP_H_BUF U_LOGIC_N67962\n+ U_LOGIC_NSLEEP_L 0 dffsr_rhpbasic_gen PARAMS: VDD=1 VSS=0 VTHRESH=500E-3\nV_U_LOGIC_V1 U_LOGIC_N01225 0 4.45\nX_U_LOGIC_U45 U_LOGIC_IMOD_INT U_LOGIC_N31070 U_LOGIC_N31106\n+ U_LOGIC_N31126 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5\nX_U5 GND NSLEEP d_d_drv88xx PARAMS:\nX_U_MOS_H3 U_MOS_S2 OUT2 IMON2 0 MOS_U_MOS_H3 \nG_U_MOS_ABM2I1 VREF IPROPI VALUE { (V(U_MOS_IMON1_DEL) +\n+ V(U_MOS_IMON2_DEL)) *AIPROPI }\nE_U_MOS_ABM60 U_MOS_DRV1 0 VALUE { IF(V(HS1)>0.5 & V(VM_UV_OK)>0.5,\n+ 5,0) }\nX_U_MOS_M5 U_MOS_VM_OK U_MOS_GATE2 U_MOS_S2 dmg4800lsd PARAMS:\nR_U_MOS_R1 IMON1 U_MOS_IMON1_DEL 254 TC=0,0 \nV_U_MOS_V1 U_MOS_VMOK_5 U_MOS_VM_OK 5\nE_U_MOS_ABM61 U_MOS_DRV3 0 VALUE { IF(V(LS1)>0.5 & V(VM_UV_OK)>0.5,\n+ 5,0) }\nX_U_MOS_U9 U_MOS_GATE4 U_MOS_V5V d_d_drv88xx PARAMS:\nX_U_MOS_M6 U_MOS_S2 U_MOS_GATE4 PGND dmg4800lsd PARAMS:\nG_U_MOS_ABMII5 U_MOS_V5V U_MOS_GATE4 VALUE { IF(V(LS2)>0.5 &\n+ V(VM_UV_OK)>0.5, 5.2m,0) }\nE_U_MOS_ABM58 U_MOS_DRV2 0 VALUE { IF(V(HS2)>0.5 & V(VM_UV_OK)>0.5,\n+ V(U_MOS_VM_OK)+5,0) }\nX_U_MOS_U10 PGND U_MOS_GATE4 d_d_drv88xx PARAMS:\nX_U_MOS_M7 U_MOS_S1 U_MOS_GATE3 PGND dmg4800lsd PARAMS:\nG_U_MOS_ABMII6 U_MOS_GATE4 PGND VALUE { IF(V(LS2)>0.5 &\n+ V(VM_UV_OK)>0.5, 0,100m) }\nE_U_MOS_ABM59 U_MOS_DRV4 0 VALUE { IF(V(LS2)>0.5 & V(VM_UV_OK)>0.5,\n+ 5,0) }\nX_U_MOS_U7 U_MOS_GATE1 U_MOS_VMOK_5 d_d_drv88xx PARAMS:\nX_U_MOS_U11 U_MOS_GATE3 U_MOS_V5V d_d_drv88xx PARAMS:\nG_U_MOS_ABMII1 U_MOS_VMOK_5 U_MOS_GATE2 VALUE { IF(V(HS2)>0.5 &\n+ V(VM_UV_OK)>0.5, 5.2m,0) }\nV_U_MOS_V2 U_MOS_V5V PGND 5\nG_U_MOS_ABMII3 U_MOS_VMOK_5 U_MOS_GATE1 VALUE { IF(V(HS1)>0.5 &\n+ V(VM_UV_OK)>0.5, 5.2m,0) }\nG_U_MOS_ABMII7 U_MOS_V5V U_MOS_GATE3 VALUE { IF(V(LS1)>0.5 &\n+ V(VM_UV_OK)>0.5, 5.2m,0) }\nE_U_MOS_E2 U_MOS_OUT2_INT 0 U_MOS_S2 0 1\nX_U_MOS_U8 U_MOS_OUT1_INT U_MOS_GATE1 d_d_drv88xx PARAMS:\nX_U_MOS_U5 U_MOS_GATE2 U_MOS_VMOK_5 d_d_drv88xx PARAMS:\nC_U_MOS_C1 0 U_MOS_IMON1_DEL 3n TC=0,0 \nX_U_MOS_U12 PGND U_MOS_GATE3 d_d_drv88xx PARAMS:\nG_U_MOS_ABMII4 U_MOS_GATE1 U_MOS_OUT1_INT VALUE { IF(V(HS1)>0.5 &\n+ V(VM_UV_OK)>0.5, 0,100m) }\nG_U_MOS_ABMII8 U_MOS_GATE3 PGND VALUE { IF(V(LS1)>0.5 &\n+ V(VM_UV_OK)>0.5, 0,100m) }\nX_U_MOS_H2 U_MOS_S1 OUT1 IMON1 0 MOS_U_MOS_H2 \nX_U_MOS_U6 U_MOS_OUT2_INT U_MOS_GATE2 d_d_drv88xx PARAMS:\nE_U_MOS_ABM55 VISENSE 0 VALUE { ( V(IMON1) \n+ +V(IMON2) ) }\nG_U_MOS_ABMII2 U_MOS_GATE2 U_MOS_OUT2_INT VALUE { IF(V(HS2)>0.5 &\n+ V(VM_UV_OK)>0.5, 0,100m) }\nE_U_MOS_E1 U_MOS_OUT1_INT 0 U_MOS_S1 0 1\nR_U_MOS_R2 IMON2 U_MOS_IMON2_DEL 254 TC=0,0 \nX_U_MOS_M8 U_MOS_VM_OK U_MOS_GATE1 U_MOS_S1 dmg4800lsd PARAMS:\nX_U_MOS_U4 IPROPI VREF d_d_drv88xx PARAMS:\nC_U_MOS_C2 0 U_MOS_IMON2_DEL 3n TC=0,0 \nE_U_MOS_ABM54 U_MOS_VM_OK 0 VALUE { IF(V(VM_UV_OK)>0.5 , V(VM) ,0) }\n.IC V(U_ISENSE_N180213 )=0\n.PARAM ilim=5.5 aipropi=1000u\n.ENDS DRV8876_TRANS\n*$\n.subckt DRV8876_S1 1 2 3 4 \nS_S1 3 4 1 2 _S1\nRS_S1 1 2 1G\n.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.2 Von=0.8\n.ends DRV8876_S1\n*$\n.subckt ISENSE_U_ISENSE_S2 1 2 3 4 \nS_U_ISENSE_S2 3 4 1 2 _U_ISENSE_S2\nRS_U_ISENSE_S2 1 2 1G\n.MODEL _U_ISENSE_S2 VSWITCH Roff=1e6 Ron=1m Voff=0.2 Von=0.8\n.ends ISENSE_U_ISENSE_S2\n*$\n.subckt ISENSE_U_ISENSE_S1 1 2 3 4 \nS_U_ISENSE_S1 3 4 1 2 _U_ISENSE_S1\nRS_U_ISENSE_S1 1 2 1G\n.MODEL _U_ISENSE_S1 VSWITCH Roff=1e6 Ron=0.01 Voff=0.2 Von=0.8\n.ends ISENSE_U_ISENSE_S1\n*$\n.subckt LOGIC_U_LOGIC_S1 1 2 3 4 \nS_U_LOGIC_S1 3 4 1 2 _U_LOGIC_S1\nRS_U_LOGIC_S1 1 2 1G\n.MODEL _U_LOGIC_S1 VSWITCH Roff=1e6 Ron=500 Voff=0.2 Von=0.8\n.ends LOGIC_U_LOGIC_S1\n*$\n.subckt MOS_U_MOS_H3 1 2 3 4 \nH_U_MOS_H3 3 4 VH_U_MOS_H3 1\nVH_U_MOS_H3 1 2 0V\n.ends MOS_U_MOS_H3\n*$\n.subckt MOS_U_MOS_H2 1 2 3 4 \nH_U_MOS_H2 3 4 VH_U_MOS_H2 1\nVH_U_MOS_H2 1 2 0V\n.ends MOS_U_MOS_H2\n*$\n*$\n.subckt D_D_DRV88xx 1 2\nd1 1 2 dd\n.model dd d\n+ is=1e-015\n+ n=0.01\n+ tt=1e-011\n.ends D_D_DRV88xx\n*$\n.subckt one_shot in out\n+ params: t=100\ns_s1 meas 0 reset2 0 s1\ne_abm1 ch 0 value { if( v(in)>0.5 | v(out)>0.5,1,0) }\nr_r2 reset2 reset 0.1 \ne_abm3 out 0 value { if( v(meas)<0.5 & v(ch)>0.5,1,0) }\nr_r1 meas ch {t} \nc_c2 0 reset2 1.4427n \nc_c1 0 meas 1.4427n \ne_abm2 reset 0 value { if(v(ch)<0.5,1,0) }\n.model s1 vswitch\n+ roff=1e+009\n+ ron=1\n+ voff=0.25\n+ von=0.75\n.ends one_shot\n*$\n.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nGQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}\nCQint Qint 0 1n\nRQint Qint 0 1000MEG\nD_D10 Qint MY5 D_D5\nV1 MY5 0 {VDD}\nD_D11 MYVSS Qint D_D5\nV2 MYVSS 0 {VSS} \nEQ Qqq 0 Qint 0 1\nX3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}\nRQq Qqqd1 Q 1\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\nRQb Qbr QB 1 \nCdummy1 Q 0 1n \nCdummy2 QB 0 1n\n.IC V(Qint) {VSS}\n.MODEL D_D5 D( IS=1e-15 TT=10p Rs=0.05 N=.1 )\n.ENDS SRLATCHRHP_BASIC_GEN\n*$\n.subckt srlatchshp_basic_gen s r q qb params: vdd=1 vss=0 vthresh=0.5 \ngq 0 qint value = {if(v(s) > {vthresh},5,if(v(r)>{vthresh},-5, 0))}\ncqint qint 0 1n\nrqint qint 0 1000meg\nd_d10 qint my5 d_d1\nv1 my5 0 {vdd}\nd_d11 myvss qint d_d1\nv2 myvss 0 {vss} \neq qqq 0 qint 0 1\nx3 qqq qqqd1 buf_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}\nrqq qqqd1 q 1\neqb qb 0 value = {1-v(q)} \ncdummy1 q 0 1n \ncdummy2 qb 0 1n \n.ic v(qint) {vss}\n.ends srlatchshp_basic_gen \n*$\n.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH} |\n+ V(C) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NOR3_BASIC_GEN\n*$\n.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NAND2_BASIC_GEN\n*$\n.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH} &\n+ V(C) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NAND3_BASIC_GEN\n*$\n.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH},{VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS NOR2_BASIC_GEN\n*$\n.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH} &\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS AND3_BASIC_GEN\n*$\n.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\nEIN INP1 INM1 INP INM 1 \nEHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }\nEOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }\nR1 OUT 1 1\nC1 1 0 5n\nRINP1 INP1 0 1K\n.ENDS COMPHYS_BASIC_GEN\n*$\n.SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VSS},{VDD})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS INV_BASIC_GEN\n*$\n.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS OR2_BASIC_GEN\n*$\n.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH} |\n+ V(C) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS OR3_BASIC_GEN\n*$\n.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5\t\nE_ABM Yint 0 VALUE {IF (V(INP) > \n+ V(INM), {VDD},{VSS})}\nR1 Yint Y 1\nC1 Y 0 1n\n.ENDS COMP_BASIC_GEN\n*$\n.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS AND2_BASIC_GEN\n*$\n.SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS BUF_BASIC_GEN\n*$\n.SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \nE_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT1 YINT2 1\nCINT YINT2 0 {DELAY*1.3}\nE_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT2 YINT3 Y 1\nCINT2 Y 0 1n\n.ENDS BUF_DELAY_BASIC_GEN\n*$\n.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \n***Set has higher priority in this\n** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations\n**Faster flip-flops require a a smaller time step to simulate\nX1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 1u\nX2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} \nGQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, \n+ IF(V(D)> {VTHRESH},5,-5),0)))}\nCQint Qint 0 1n\nRQint Qint 0 1000MEG\nD_D10 Qint MY5 D_D4\nV1 MY5 0 {VDD}\nD_D11 MYVSS Qint D_D4\nV2 MYVSS 0 {VSS} \nEQ Qqq 0 Qint 0 1\nX3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n\nRQq Qqqd1 Q 1\nEQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}\nRQb Qbr Qb 1 \nCdummy1 Q 0 1nF \nCdummy2 QB 0 1nF \n.IC V(Qint) {VSS}\n.MODEL D_D4 D( IS=1e-15 TT=10p Rs=0.05 N=.1 )\n.ENDS DFFSR_RHPBASIC_GEN\n*$\n.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n \nE_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , \n+ {VDD},{VSS})}}\nRINT YINT1 YINT2 1\nCINT YINT2 0 {DELAY*1.3}\nE_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , \n+ {VSS},{VDD})}}\nRINT2 YINT3 Y 1\nCINT2 Y 0 1n\n.ENDS INV_DELAY_BASIC_GEN\n*$\n.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & \n+ V(B) > {VTHRESH} &\n+ V(C) > {VTHRESH} &\n+ V(D) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS AND4_BASIC_GEN\n*$\n.SUBCKT DMG4800LSD D G S\nM1 1 G 3 3 NMOS L=1.84U W=50m M=1\nRD D 1 0.1m\nRS S 3 0.1m\nCGS G 3 10p\nCGD G 1 40p\n*CGS G 3 692p\n*EGD 12 0 G 1 1\n*VFB 14 0 0\n*FFB G 1 VFB 1\n*R1 13 0 1.00\n*D1 12 13 DLIM\n*DDG 15 14 DCGD\n*R2 12 15 1.00\n*D2 15 0 DLIM\nDSD 3 D DSUB\n*.MODEL NMOS NMOS LEVEL=3 U0=400 VMAX=40k\n*+ ETA=0.1m VTO=1.62 TOX=60n NSUB=2.16e16\n.MODEL NMOS NMOS LEVEL=3 U0=400 VMAX=40k\n+ VTO=1.62 TOX=60n \n*.MODEL NMOS NMOS (VTO = 1.7 KP = 20 LAMBDA = 0.0001)\n.MODEL DCGD D CJO=488p VJ=450m M=0.420\n.MODEL DSUB D IS=36.1n N=1.50 RS=21.8m BV=30\n+ CJO=48p VJ=0.950 M=0.920\n.MODEL DLIM D IS=100U\n.ENDS DMG4800LSD\n*$\n.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 \nE_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | \n+ V(B) > {VTHRESH} |\n+ V(C) > {VTHRESH} |\n+ V(D) > {VTHRESH},{VDD},{VSS})}}\nRINT YINT Y 1\nCINT Y 0 1n\n.ENDS OR4_BASIC_GEN\n*$\n"
},
{
"type": "simulation_voltage_source",
"simulation_voltage_source_id": "simulation_voltage_source_0",
"is_dc_source": false,
"terminal1_source_port_id": "source_port_29",
"terminal2_source_port_id": "source_port_30",
"voltage": 24
},
{
"type": "simulation_voltage_source",
"simulation_voltage_source_id": "simulation_voltage_source_1",
"is_dc_source": false,
"terminal1_source_port_id": "source_port_31",
"terminal2_source_port_id": "source_port_32",
"voltage": 3.3
},
{
"type": "simulation_voltage_source",
"simulation_voltage_source_id": "simulation_voltage_source_2",
"is_dc_source": false,
"terminal1_source_port_id": "source_port_33",
"terminal2_source_port_id": "source_port_34",
"voltage": 3.3,
"frequency": 50000,
"wave_shape": "square",
"duty_cycle": 0.25,
"pulse_delay": 1.2,
"rise_time": 0.00009999999999999999,
"fall_time": 0.00009999999999999999
},
{
"type": "simulation_voltage_source",
"simulation_voltage_source_id": "simulation_voltage_source_3",
"is_dc_source": false,
"terminal1_source_port_id": "source_port_35",
"terminal2_source_port_id": "source_port_36",
"voltage": 3.3,
"wave_shape": "square",
"pulse_delay": 0.05,
"rise_time": 0.00009999999999999999,
"fall_time": 0.00009999999999999999,
"pulse_width": 4,
"period": 5
},
{
"type": "simulation_current_probe",
"simulation_current_probe_id": "simulation_current_probe_0",
"name": "I_MOTOR_PROBE",
"source_component_id": "source_component_14",
"positive_source_port_id": "source_port_55",
"negative_source_port_id": "source_port_56",
"subcircuit_id": "subcircuit_source_group_0",
"color": "#00d95f"
},
{
"type": "simulation_oscilloscope_trace",
"simulation_oscilloscope_trace_id": "simulation_oscilloscope_trace_0",
"simulation_current_probe_id": "simulation_current_probe_0",
"display_name": "IOUT",
"color": "#00d95f",
"display_center_value": 0.5,
"amps_per_div": 0.5,
"display_center_offset_divs": -2
},
{
"type": "simulation_voltage_probe",
"simulation_voltage_probe_id": "simulation_voltage_probe_0",
"name": "OUT1_PROBE",
"signal_input_source_port_id": "source_port_7",
"reference_input_source_port_id": "source_port_8",
"subcircuit_id": "subcircuit_source_group_0",
"color": "#f1d900"
},
{
"type": "simulation_oscilloscope_trace",
"simulation_oscilloscope_trace_id": "simulation_oscilloscope_trace_1",
"simulation_voltage_probe_id": "simulation_voltage_probe_0",
"display_name": "OUT1",
"color": "#f1d900",
"display_center_value": 12,
"volts_per_div": 5,
"display_center_offset_divs": 3
},
{
"type": "simulation_voltage_probe",
"simulation_voltage_probe_id": "simulation_voltage_probe_1",
"name": "OUT2_PROBE",
"signal_input_source_port_id": "source_port_9",
"reference_input_source_port_id": "source_port_8",
"subcircuit_id": "subcircuit_source_group_0",
"color": "#00cfe8"
},
{
"type": "simulation_oscilloscope_trace",
"simulation_oscilloscope_trace_id": "simulation_oscilloscope_trace_2",
"simulation_voltage_probe_id": "simulation_voltage_probe_1",
"display_name": "OUT2",
"color": "#00cfe8",
"display_center_value": 12,
"volts_per_div": 5,
"display_center_offset_divs": 2
},
{
"type": "simulation_voltage_probe",
"simulation_voltage_probe_id": "simulation_voltage_probe_2",
"name": "IPROPI_PROBE",
"signal_input_source_port_id": "source_port_5",
"reference_input_source_port_id": "source_port_14",
"subcircuit_id": "subcircuit_source_group_0",
"color": "#d946ef"
},
{
"type": "simulation_oscilloscope_trace",
"simulation_oscilloscope_trace_id": "simulation_oscilloscope_trace_3",
"simulation_voltage_probe_id": "simulation_voltage_probe_2",
"display_name": "VIPROPI",
"color": "#d946ef",
"display_center_value": 0.6,
"volts_per_div": 1,
"display_center_offset_divs": -1
},
{
"type": "simulation_experiment",
"simulation_experiment_id": "simulation_experiment_0",
"name": "DRV8876 Driver PWM Operation With Current Feedback",
"experiment_type": "spice_transient_analysis",
"end_time_ms": 2,
"start_time_ms": 1.8,
"time_per_step": 0.00009999999999999999,
"spice_options": {
"method": "gear",
"reltol": 0.01,
"abstol": "1n",
"vntol": "1u"
}
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 0,
"y": 0
},
"rotation": 0,
"size": {
"width": 3,
"height": 7
},
"port_arrangement": {
"left_side": {
"pins": [
"EN",
"PH",
"nSLEEP",
"nFAULT",
"VREF",
"IPROPI",
"IMODE"
],
"direction": "top-to-bottom"
},
"right_side": {
"pins": [
"VM",
"VCP",
"CPH",
"CPL",
"OUT1",
"OUT2",
"PGND",
"GND",
"PAD"
],
"direction": "top-to-bottom"
}
},
"pin_spacing": 0.2,
"pin_styles": {
"pin2": {},
"pin3": {},
"pin5": {},
"pin7": {},
"pin10": {},
"pin11": {},
"pin13": {},
"pin15": {},
"pin17": {}
},
"port_labels": {
"pin1": "EN",
"pin2": "PH",
"pin3": "nSLEEP",
"pin4": "nFAULT",
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},
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{
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"message": "Static reachability precheck failed: 2 route(s) have no legal path under the current reservation and start-region rules source_net_2_mst0 (pcb_port_45->pcb_port_1), source_net_2_mst1 (pcb_port_45->pcb_port_37) (capacity-autorouter@0.0.710)"
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