tscircuit/ti
ti tscircuit library
- Version
- 1.0.85
- License
- unset
- Stars
- 0
dist/lib/chips/CC2745R10E0WRHARQ1/circuit.json
PCB
Schematic
[
{
"type": "source_group",
"source_group_id": "source_group_0",
"is_subcircuit": true,
"was_automatically_named": true,
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_0",
"name": "VDDR",
"pin_number": 1,
"port_hints": [
"VDDR",
"VDDR1",
"pin1",
"1"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"must_be_connected": true
},
{
"type": "source_port",
"source_port_id": "source_port_1",
"name": "VDDR",
"pin_number": 2,
"port_hints": [
"VDDR",
"VDDR2",
"pin2",
"2"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_2",
"name": "DIO0",
"pin_number": 3,
"port_hints": [
"DIO0",
"pin3",
"3"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_3",
"name": "DIO1",
"pin_number": 4,
"port_hints": [
"DIO1",
"pin4",
"4"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_4",
"name": "DIO2",
"pin_number": 5,
"port_hints": [
"DIO2",
"pin5",
"5"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_5",
"name": "DIO3",
"pin_number": 6,
"port_hints": [
"DIO3",
"pin6",
"6"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_6",
"name": "DIO4",
"pin_number": 7,
"port_hints": [
"DIO4",
"pin7",
"7"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_7",
"name": "DIO5",
"pin_number": 8,
"port_hints": [
"DIO5",
"pin8",
"8"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_8",
"name": "VDDIO",
"pin_number": 9,
"port_hints": [
"VDDIO",
"VDDIO1",
"pin9",
"9"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_9",
"name": "DIO7",
"pin_number": 10,
"port_hints": [
"DIO7",
"pin10",
"10"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_10",
"name": "DDIO9_SWDIOIO9",
"pin_number": 11,
"port_hints": [
"DDIO9_SWDIOIO9",
"SWDIO",
"DIO9_SWDIO",
"pin11",
"11"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_11",
"name": "DIO10_SWDCK",
"pin_number": 12,
"port_hints": [
"DIO10_SWDCK",
"SWDCK",
"pin12",
"12"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_12",
"name": "DIO11",
"pin_number": 13,
"port_hints": [
"DIO11",
"pin13",
"13"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_13",
"name": "DIO12",
"pin_number": 14,
"port_hints": [
"DIO12",
"pin14",
"14"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_14",
"name": "DIO15",
"pin_number": 15,
"port_hints": [
"DIO15",
"pin15",
"15"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_15",
"name": "DIO16",
"pin_number": 16,
"port_hints": [
"DIO16",
"pin16",
"16"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_16",
"name": "VDDIO",
"pin_number": 17,
"port_hints": [
"VDDIO",
"VDDIO2",
"pin17",
"17"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_17",
"name": "VDDS",
"pin_number": 18,
"port_hints": [
"VDDS",
"VDDS1",
"pin18",
"18"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_18",
"name": "DIO17_A8",
"pin_number": 19,
"port_hints": [
"DIO17_A8",
"ADC_A8",
"pin19",
"19"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_19",
"name": "DIO18_A7",
"pin_number": 20,
"port_hints": [
"DIO18_A7",
"ADC_A7",
"pin20",
"20"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_20",
"name": "DIO19_A6",
"pin_number": 21,
"port_hints": [
"DIO19_A6",
"ADC_A6",
"pin21",
"21"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_21",
"name": "DIO20_A5",
"pin_number": 22,
"port_hints": [
"DIO20_A5",
"ADC_A5",
"pin22",
"22"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_22",
"name": "DIO21_A4",
"pin_number": 23,
"port_hints": [
"DIO21_A4",
"ADC_A4",
"pin23",
"23"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_23",
"name": "DIO22_A3",
"pin_number": 24,
"port_hints": [
"DIO22_A3",
"ADC_A3",
"pin24",
"24"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_24",
"name": "N_RESET",
"pin_number": 25,
"port_hints": [
"N_RESET",
"nRST",
"pin25",
"25"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_25",
"name": "DIO23_X32P",
"pin_number": 26,
"port_hints": [
"DIO23_X32P",
"pin26",
"26"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_26",
"name": "DIO24_X32N",
"pin_number": 27,
"port_hints": [
"DIO24_X32N",
"pin27",
"27"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_27",
"name": "VDDD",
"pin_number": 28,
"port_hints": [
"VDDD",
"pin28",
"28"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_28",
"name": "VDDS",
"pin_number": 29,
"port_hints": [
"VDDS",
"VDDS2",
"pin29",
"29"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_29",
"name": "DCDC_SW",
"pin_number": 30,
"port_hints": [
"DCDC_SW",
"pin30",
"30"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_30",
"name": "VDDS",
"pin_number": 31,
"port_hints": [
"VDDS",
"VDDS3",
"pin31",
"31"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_31",
"name": "DIO27",
"pin_number": 32,
"port_hints": [
"DIO27",
"ADC_A1",
"DIO27_A1",
"pin32",
"32"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_32",
"name": "DIO28",
"pin_number": 33,
"port_hints": [
"DIO28",
"ADC_A0",
"DIO28_A0",
"pin33",
"33"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_33",
"name": "VDDR",
"pin_number": 34,
"port_hints": [
"VDDR",
"VDDR3",
"pin34",
"34"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_34",
"name": "X48P",
"pin_number": 35,
"port_hints": [
"X48P",
"pin35",
"35"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_35",
"name": "X48N",
"pin_number": 36,
"port_hints": [
"X48N",
"pin36",
"36"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_36",
"name": "NC",
"pin_number": 37,
"port_hints": [
"NC",
"pin37",
"37"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_37",
"name": "VDDS",
"pin_number": 38,
"port_hints": [
"VDDS",
"VDDS4",
"pin38",
"38"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_38",
"name": "ANT",
"pin_number": 39,
"port_hints": [
"ANT",
"pin39",
"39"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_39",
"name": "RFGND",
"pin_number": 40,
"port_hints": [
"RFGND",
"pin40",
"40"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_40",
"name": "EGP",
"pin_number": 41,
"port_hints": [
"EGP",
"thermalpad",
"pin41",
"41"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_component",
"source_component_id": "source_component_0",
"ftype": "simple_chip",
"name": "unnamed_chip1",
"manufacturer_part_number": "CC2745R10E0WRHARQ1",
"supplier_part_numbers": {
"jlcpcb": []
},
"source_group_id": "source_group_0",
"internally_connected_source_port_ids": [
[
"source_port_0",
"source_port_1",
"source_port_33"
],
[
"source_port_8",
"source_port_16"
],
[
"source_port_17",
"source_port_28",
"source_port_30",
"source_port_37"
]
]
},
{
"type": "source_component_internal_connection",
"source_component_internal_connection_id": "source_component_internal_connection_0",
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"source_port_ids": [
"source_port_0",
"source_port_1",
"source_port_33"
]
},
{
"type": "source_component_internal_connection",
"source_component_internal_connection_id": "source_component_internal_connection_1",
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"source_port_ids": [
"source_port_8",
"source_port_16"
]
},
{
"type": "source_component_internal_connection",
"source_component_internal_connection_id": "source_component_internal_connection_2",
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"source_port_ids": [
"source_port_17",
"source_port_28",
"source_port_30",
"source_port_37"
]
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 0,
"y": 0
},
"rotation": 0,
"size": {
"width": 3,
"height": 5.6
},
"port_arrangement": {
"left_side": {
"pins": [
1,
2,
34,
18,
29,
31,
38,
28,
9,
17,
19,
20,
21,
22,
23,
24,
32,
33,
26,
27,
30
],
"direction": "top-to-bottom"
},
"right_side": {
"pins": [
39,
25,
3,
4,
5,
6,
7,
8,
10,
11,
12,
13,
14,
15,
16,
35,
36,
37,
40,
41
],
"direction": "top-to-bottom"
}
},
"pin_spacing": 0.2,
"pin_styles": {
"pin16": {},
"pin17": {},
"pin25": {},
"pin26": {},
"pin27": {},
"pin28": {},
"pin30": {},
"pin33": {},
"pin35": {},
"pin36": {},
"pin37": {},
"pin39": {},
"pin41": {}
},
"port_labels": {
"pin1": "VDDR",
"pin2": "VDDR",
"pin3": "DIO0",
"pin4": "DIO1",
"pin5": "DIO2",
"pin6": "DIO3",
"pin7": "DIO4",
"pin8": "DIO5",
"pin9": "VDDIO",
"pin10": "DIO7",
"pin11": "DDIO9_SWDIOIO9",
"pin12": "DIO10_SWDCK",
"pin13": "DIO11",
"pin14": "DIO12",
"pin15": "DIO15",
"pin16": "DIO16",
"pin17": "VDDIO",
"pin18": "VDDS",
"pin19": "DIO17_A8",
"pin20": "DIO18_A7",
"pin21": "DIO19_A6",
"pin22": "DIO20_A5",
"pin23": "DIO21_A4",
"pin24": "DIO22_A3",
"pin25": "N_RESET",
"pin26": "DIO23_X32P",
"pin27": "DIO24_X32N",
"pin28": "VDDD",
"pin29": "VDDS",
"pin30": "DCDC_SW",
"pin31": "VDDS",
"pin32": "DIO27",
"pin33": "DIO28",
"pin34": "VDDR",
"pin35": "X48P",
"pin36": "X48N",
"pin37": "NC",
"pin38": "VDDS",
"pin39": "ANT",
"pin40": "RFGND",
"pin41": "EGP"
},
"source_component_id": "source_component_0",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_0",
"text": "CC2745R10E0WRHARQ1",
"schematic_component_id": "schematic_component_0",
"anchor": "left",
"rotation": 0,
"position": {
"x": -1.5,
"y": -2.9299999999999997
},
"color": "#006464",
"font_size": 0.18
},
{
"type": "schematic_text",
"schematic_text_id": "schematic_text_1",
"text": "",
"schematic_component_id": "schematic_component_0",
"anchor": "left",
"rotation": 0,
"position": {
"x": -1.5,
"y": 2.9299999999999997
},
"color": "#006464",
"font_size": 0.18
},
{
"type": "schematic_group",
"schematic_group_id": "schematic_group_0",
"is_subcircuit": true,
"subcircuit_id": "subcircuit_source_group_0",
"name": "unnamed_group1",
"center": {
"x": 0,
"y": 0
},
"width": 0,
"height": 0,
"schematic_component_ids": [],
"source_group_id": "source_group_0",
"show_as_schematic_box": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_0",
"schematic_component_id": "schematic_component_0",
"center": {
"x": -1.9,
"y": 2.550000000000001
},
"source_port_id": "source_port_0",
"facing_direction": "left",
"distance_from_component_edge": 0.4,
"side_of_component": "left",
"pin_number": 1,
"true_ccw_index": 0,
"display_pin_label": "VDDR",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_1",
"schematic_component_id": "schematic_component_0",
"center": {
"x": -1.9,
"y": 2.350000000000001
},
"source_port_id": "source_port_1",
"facing_direction": "left",
"distance_from_component_edge": 0.4,
"side_of_component": "left",
"pin_number": 2,
"true_ccw_index": 1,
"display_pin_label": "VDDR",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_2",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 1.9,
"y": 1.7500000000000004
},
"source_port_id": "source_port_2",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 3,
"true_ccw_index": 2,
"display_pin_label": "DIO0",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_3",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 1.9,
"y": 1.5500000000000003
},
"source_port_id": "source_port_3",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 4,
"true_ccw_index": 3,
"display_pin_label": "DIO1",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_4",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 1.9,
"y": 1.3500000000000005
},
"source_port_id": "source_port_4",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 5,
"true_ccw_index": 4,
"display_pin_label": "DIO2",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_5",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 1.9,
"y": 1.1500000000000004
},
"source_port_id": "source_port_5",
"facing_direction": "right",
"distance_from_component_edge": 0.4,
"side_of_component": "right",
"pin_number": 6,
"true_ccw_index": 5,
"display_pin_label": "DIO3",
"is_connected": false
},
{
"type": "schematic_port",
"schematic_port_id": "schematic_port_6",
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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