techmannih/nema34-mounted-stepper-controller

engineering/reviewer-eco.json

{
  "status": "cad-verified-order-hold",
  "baseline": "4698062",
  "user_decisions": {
    "separate_usb_ports": true,
    "industrial_interfaces": "retain CAN, RS485, RS232 and all I/O",
    "external_motor_bridges": "retain TMC5160A and eight CSD19534Q5A MOSFETs",
    "industrial_connector_placement": "J7 beside motor connector J2 at the board edge"
  },
  "changes": [
    "J1 is PD POWER only; J10 is USB DATA with independent regulated logic power and VBUS attach sense",
    "J10 CC1 and CC2 have independent 5.1k Rd and USBLC6-4SC6 ESD protection",
    "U5 boots from PD VBUS before the eFuse; U22 retains VMOTOR brake backup; U23/U24 OR to board V3V3. U28/U25 derive V3V3_USB from DATA VBUS; U26/U27 combine the two logic rails without joining their VBUS inputs.",
    "J7 20-pin JST PHD replaces J6/J7/J9 without deleting industrial features",
    "TMC5160 SD_MODE pin functions: pin23 DCEN grounded, pin24 DCIN grounded, pin25 DCO NC; encoder SPI and ABI test pads retained",
    "R105 and D12 PCB orientations corrected; only local copper rerouted, logical connections preserved",
    "J7 moved from the board center to (-2, -39) mm beside J2; SW1 shifted 4 mm left for clearance. Schematic and pinout unchanged; affected copper rerouted and VMOTOR reinforced with 2.4 mm corridors and parallel power vias."
  ],
  "sources": [
    "https://www.ti.com/lit/ds/symlink/lmr36510.pdf",
    "https://www.ti.com/lit/ds/symlink/tpd4s480.pdf",
    "https://www.st.com/resource/en/datasheet/usblc6-4.pdf",
    "https://www.jst-mfg.com/product/pdf/eng/ePHD.pdf",
    "https://www.analog.com/media/en/technical-documentation/data-sheets/tmc5160a_datasheet_rev1.18.pdf",
    "https://www.ti.com/lit/ds/symlink/ina240.pdf",
    "https://www.ti.com/lit/gpn/tmp102",
    "https://www.ti.com/lit/ds/symlink/ads1115.pdf",
    "https://www.ti.com/lit/ds/symlink/tlv755p.pdf",
    "https://www.ti.com/lit/ds/symlink/tps2553.pdf",
    "https://www.ti.com/lit/ds/symlink/lm66100.pdf"
  ],
  "manufacturing_orderable": false,
  "open_gates": [
    "TI TPS26750 EPR EEPROM image and programming/negotiation verification",
    "USB current/inrush/backfeed/attach-detach measurements",
    "Motor bring-up and thermal/regeneration validation"
  ],
  "connector_stock": {
    "C471521": "exact indexed stock checked; PA66 glass-filled header, same JST PHD interface",
    "C158017": "not selected: exact index query empty"
  },
  "driver_alternative": "DRV8462DDVR researched but not selected; user requested retaining the present bridges",
  "usb_power_assumption": "DATA USB supplies setup/diagnostics independently; motor power remains PD-only. MCU-only rail and suspend firmware implemented; USB power-state compliance needs hardware qualification.",
  "connector_relocation": {
    "baseline_commit": "3cb470b1edb3a1562233fa85b4c145d706f3ea6c",
    "J7_center_mm": [
      -2,
      -39
    ],
    "J2_center_mm": [
      20,
      -39
    ],
    "SW1_center_mm": [
      -18,
      -40
    ],
    "schematic_records_compared": 2901,
    "schematic_records_unchanged": true,
    "source_matched_pad_geometries": 942,
    "native_drc_violations": 0,
    "unconnected_items": 0,
    "schematic_parity_issues": 0,
    "erc_violations": 0
  },
  "top_side_assembly_change": {
    "requested_at": "2026-10-09",
    "placed_components": 265,
    "fitted_parts": 254,
    "bare_service_pads": 11,
    "bottom_components": 0,
    "schematic_records_unchanged": true,
    "routing_validation": "Native DRC: 0 violations, 0 unconnected, 0 schematic parity; ERC: 0 violations",
    "encoder_magnet_gap_validation": "pending physical assembly"
  },
  "baseline_cad_evidence": {
    "drc_violations": 0,
    "unconnected_items": 0,
    "schematic_parity_issues": 0,
    "erc_violations": 0,
    "thermal_vias_verified": 40,
    "live_available_part_types": 68,
    "board_file": "dist/manufacturing/kicad-project/pd1180-epr-r0.3.kicad_pcb",
    "source_matched_pad_geometries": 942,
    "verification_checks_passed": 29,
    "topology_and_via_tests": 19,
    "test_assertions": 728,
    "delivery_required_files": 38,
    "delivery_zip_archives": 5,
    "mapped_viewer_ports": 934,
    "scope": "Historical pre-telemetry route; does not validate the current source"
  },
  "reference_board_eco": {
    "baseline_commit": "49c3ac7836e0595798955490af49c769ca056bc6",
    "reference_boards": [
      "https://tscircuit.com/imrishabh18/rp2040-motor-controller",
      "https://tscircuit.com/imrishabh18/nema-23-stepper-controller"
    ],
    "driver_decision": "Retain TMC5160A per prior explicit user instruction. DRV8462 DDV requires a separate approved power-stage redesign. Exact C29780285 stock was not verified.",
    "changes": [
      "Compact gate and bootstrap routing; terminal-only Kelvin returns",
      "TMP102 ALERT hardware inhibit with firmware validity and thermal derating request",
      "ADS1115 bus telemetry frees PA0/PA1 for INA240 per-phase diagnostics",
      "Independent DATA USB logic supply with reverse blocking",
      "283 fitted components and 11 service pads on top; 42 constrained bypasses",
      "Separate V3V3_MCU, board-power sense, open-drain CS, power-qualified I2C/telemetry and USB STOP0 with watchdog wake"
    ],
    "validation": "Completed native route: zero DRC violations, unconnected items, schematic parity issues and ERC violations. All 9 Kelvin/analog branches pass terminal-only isolation; 40 drain thermal vias retain correct nets, and 42 local bypass paths are constrained. Motor outputs remain locked and ordering remains on hold.",
    "fabrication_blockers": [
      "Qualify USB startup/suspend current, resume timing and rail handovers on hardware.",
      "Review clipped power-copper necks and validate target-current thermal performance.",
      "Complete TI configuration and staged powered commissioning."
    ],
    "current_sense_paths_mm": {
      "A_LOW": 22.775,
      "A_HIGH": 12.564,
      "B_LOW": 19.2,
      "B_HIGH": 22.765,
      "PHASE_A_PLUS": 3.099,
      "PHASE_A_MINUS": 3.099,
      "PHASE_B_PLUS": 3.099,
      "PHASE_B_MINUS": 3.099
    },
    "reference_evidence": "engineering/reference-board-comparison.json",
    "routing_evidence": "docs/routing-report.json",
    "validation_helper_corrections": [
      "Use actual overlap outside the receiving pad for Kelvin joins; regression distinguishes in-pad from premature joins.",
      "Use KiCad rotation in downward-positive file coordinates for thermal-pad checks.",
      "Measure same-net/layer corridor coverage by geometric length, independent of segment and overlapping zone counts."
    ]
  },
  "completion_work": {
    "status": "cad-and-software-completed-hardware-qualification-pending",
    "firmware": "Integrated and host-tested TMC5160A pipelined SPI, write acknowledgement, disabled startup, mode/fault checks and thermally scaled low-current STEP/DIR service; released ARM image stays locked until hardware/configuration qualification.",
    "ci": "Canonicalized only derived trace_length at 1e-12 mm to prevent cross-platform floating-point evidence mismatch. Review validates CAD with the order hold visible; ordering remains separately blocked.",
    "motor_phase_copper": "Parallel bottom corridor from Q7 drain stitching to R115 input, four new 0.60/0.30 mm transfer vias and 2.4 mm top landing. No Kelvin branch shortcut.",
    "pd_configuration": "Official TI tool v2.0.1 reached; export pending explicit user approval of its application license. No TI binary invented.",
    "physical_evidence": "Assembled-board availability, actual load/RPM/stop time and brake/heatsink data requested, not yet supplied.",
    "usb_routing": "R71 grouped with R72 on top; USB trunks rerouted on B.Cu over a stitched local In2 GND region. Five low-speed signals moved out of the reference layer. Native DRC/parity zero; all four USB reference checks pass, and the previous routing fails the same checker.",
    "schematic_records_unchanged": 3189,
    "pad_comparison": {
      "pad_geometries_checked": 1042,
      "unchanged_except_R71_translation_mm": [
        -15,
        1.5
      ],
      "all_other_pad_geometry_layer_net_unchanged": true,
      "board_sha256": "61bad79e8f07e963e17933d183a309a91dc449ff143098563ce739ee1f07138d"
    },
    "motor_phase_copper_evidence": "engineering/filled-copper-review.json",
    "usb_reference_evidence": "docs/usb-reference-check.json",
    "release_3d": "Release export regenerates GLB from the exact final routed circuit, deletes previous output first and requires a valid complete GLB before packaging.",
    "via_drill_correction": {
      "baseline_commit": "d02df91171e6f44e42e1531dce0d28b64a0d0e21",
      "board_sha256": "ca3715aa25884e35cc3925a0c5e498852de8ee2de2fae081cf484d3a2d74c6bf",
      "pads_compared": 1042,
      "all_pad_positions_geometry_and_nets_unchanged": true,
      "via_count": 561,
      "minimum_finished_via_drill_mm": 0.3,
      "via_pad_drill_counts": {
        "0.50/0.30": 416,
        "0.60/0.30": 145
      },
      "changes": "416 dense-signal vias at 0.50/0.30 mm and 145 power/general vias at 0.60/0.30 mm. Local trace adjustments preserve all footprint/pad geometry and all nine original sense branches. Removed two disconnected pour fragments, merged adjoining SENSE_B pours at a copper sliver, and added one digital-ground via."
    }
  },
  "superseded_by": "engineering/onboard-control-eco.json",
  "historical_note": "Historical architecture record. Current user scope removes J7/external command paths and unsupported mounting fixture; do not use this file as the current connection inventory."
}