techmannih/nema34-mounted-stepper-controller
A 48 V USB‑C PD 3.1 EPR NEMA‑34 stepper controller PCB combining STM32/TMC5160 control, external MOSFET motor bridges, protected power and regenerative braking, USB data, telemetry, diagnostics, status LEDs, and buzzer alarms.
- Version
- 0.3.92
- License
- unset
- Stars
- 1
docs/decoupling-check.json
{
"note": "Checks IC-to-cap placement and the explicit local power trace only. Ground return loop and all other copper still require routing review.",
"results": [
{
"ic": "U1",
"pin": 10,
"capacitor": "C2",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 4.2442466776182695,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.8092871567303344,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U2",
"pin": 32,
"capacitor": "C6",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.160394122736303,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.137266572858895,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U2",
"pin": 1,
"capacitor": "C7",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.5851258021515604,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.500157959502933,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U2",
"pin": 4,
"capacitor": "C8",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.3900179477004522,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.3894575647568375,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U3",
"pin": 8,
"capacitor": "C9",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.4379453880338873,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.063866856930457,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U4",
"pin": 5,
"capacitor": "C10",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8956116887994208,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.8755686501434716,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U5",
"pin": 2,
"capacitor": "C12",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.1000300000000003,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.1000300000000003,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U6",
"pin": 17,
"capacitor": "C21",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.569069484528265,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.5583169455118355,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U7",
"pin": 3,
"capacitor": "C25",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.163127788413532,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.9022376738819706,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U7",
"pin": 5,
"capacitor": "C26",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.0686129607975796,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.8388080801533615,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U7",
"pin": 29,
"capacitor": "C27",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.0876100511034412,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.0876100009206877,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U7",
"pin": 20,
"capacitor": "C28",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8751100765432316,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.8751100010251374,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U7",
"pin": 33,
"capacitor": "C29",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.1751100867382585,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.1751100010013458,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U7",
"pin": 4,
"capacitor": "C61",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.820084833568842,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.6979176630238477,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U10",
"pin": 5,
"capacitor": "C38",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8956116887994188,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.8755686501434707,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U11",
"pin": 5,
"capacitor": "C39",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8956116887994188,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.8755686501434707,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U13",
"pin": 5,
"capacitor": "C40",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.618563392721837,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.538237038064216,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U14",
"pin": 5,
"capacitor": "C41",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.055893303722359,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.29196118235039,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U15",
"pin": 1,
"capacitor": "C43",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.0880360652392076,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.0314524406975423,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U16",
"pin": 6,
"capacitor": "C44",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.2571068652119286,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 3.090711892105119,
"placement_limit_mm": 3.7,
"placement_override_reason": "UFQFPN48 lands move 0.875 mm inward from the previous LQFP row. C44/C45/C46 retain their proven ground returns and top-side branches; measured source paths remain 3.26/3.98/3.77 mm (all below the unchanged 5 mm native limit). This explicit 3.7 mm centre-distance bound preserves the local bypass placement without disturbing the adjacent crystal, USB and buzzer paths. Hardware rail ripple remains unqualified.",
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U16",
"pin": 5,
"capacitor": "C45",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.976501779779961,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 3.6472592449673775,
"placement_limit_mm": 3.7,
"placement_override_reason": "UFQFPN48 lands move 0.875 mm inward from the previous LQFP row. C44/C45/C46 retain their proven ground returns and top-side branches; measured source paths remain 3.26/3.98/3.77 mm (all below the unchanged 5 mm native limit). This explicit 3.7 mm centre-distance bound preserves the local bypass placement without disturbing the adjacent crystal, USB and buzzer paths. Hardware rail ripple remains unqualified.",
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U16",
"pin": 4,
"capacitor": "C46",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.7693985754510053,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 3.3988968798714687,
"placement_limit_mm": 3.7,
"placement_override_reason": "UFQFPN48 lands move 0.875 mm inward from the previous LQFP row. C44/C45/C46 retain their proven ground returns and top-side branches; measured source paths remain 3.26/3.98/3.77 mm (all below the unchanged 5 mm native limit). This explicit 3.7 mm centre-distance bound preserves the local bypass placement without disturbing the adjacent crystal, USB and buzzer paths. Hardware rail ripple remains unqualified.",
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U17",
"pin": 8,
"capacitor": "C51",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.363574589766667,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.3454299666508915,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U18",
"pin": 11,
"capacitor": "C52",
"layer": "bottom",
"same_outer_layer": false,
"approved_layer_transition": true,
"via_count": 1,
"manual_trace_length_mm": 3.8730224196376506,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.9249039999999997,
"placement_limit_mm": 3,
"placement_override_reason": "Only U18 is allowed on the bottom. C52 retains its XY pad centers on top, joined through one 0.60/0.30 mm V3V3 via at source (-0.6,-3.9), native (99.4,103.9). The 5 mm budget includes the 1.6 mm board thickness; all ordinary bypasses remain on the IC side. Encoder supply/ground ripple still requires powered qualification.",
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U22",
"pin": 2,
"capacitor": "C63",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8500300000000003,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.8500300000000003,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U23",
"pin": 1,
"capacitor": "C69",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8149636031196317,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.677964274253778,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U24",
"pin": 1,
"capacitor": "C70",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.100026001958981,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.1000260000466655,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U28",
"pin": 1,
"capacitor": "C74",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.1169910223453186,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.850511708746343,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U25",
"pin": 1,
"capacitor": "C75",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.5250401957061048,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.5250400032133589,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U25",
"pin": 5,
"capacitor": "C76",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.5250401957061048,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.5250400032133589,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U26",
"pin": 1,
"capacitor": "C77",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.7679738258028737,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.7055924130718596,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U27",
"pin": 1,
"capacitor": "C78",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.563871975288938,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.563871975288938,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U29",
"pin": 5,
"capacitor": "C79",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.4679266455904223,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.0808972455002763,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U30",
"pin": 8,
"capacitor": "C80",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 4.032112803555271,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.677259823118406,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U31",
"pin": 6,
"capacitor": "C81",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.627370958593997,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.433652812132412,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U32",
"pin": 6,
"capacitor": "C82",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.627370958593997,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.433652812132412,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U33",
"pin": 5,
"capacitor": "C85",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.641039759526728,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.641039759526728,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U34",
"pin": 2,
"capacitor": "C87",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 4.067433746639325,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 3.1328092736232747,
"placement_limit_mm": 3.3,
"placement_override_reason": "U34 VIN is the second pin of the PowerPAD package. C87 sits directly beside the package courtyard; the allowed 3.3 mm pad-center spacing clears PGND while retaining a <=5 mm top-layer connection. See docs/power-validation.md.",
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U34",
"pin": 6,
"capacitor": "C88",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 3.711758181521616,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.9150136783384046,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U12",
"pin": 4,
"capacitor": "C93",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 2.567057590220791,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 2.471494993258128,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U12",
"pin": 6,
"capacitor": "C94",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.8674150508279945,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.7314878000436502,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U35",
"pin": 16,
"capacitor": "C95",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.49623694647606,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.49623694647606,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U36",
"pin": 8,
"capacitor": "C97",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.9502530380204528,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.9502530380204528,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
},
{
"ic": "U37",
"pin": 5,
"capacitor": "C99",
"layer": "top",
"same_outer_layer": true,
"approved_layer_transition": false,
"via_count": 0,
"manual_trace_length_mm": 1.624901000492339,
"routed_length_pass": true,
"connected": true,
"straight_line_mm": 1.624901000492339,
"placement_limit_mm": 3,
"routed_length_budget_mm": 5,
"placement_pass": true
}
]
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