shibosoftwaredev/f1c100s-linux-nema17-stepper-controller

history/README-before-round12-20261020.md

# F1C100S Linux NEMA 17 stepper controller

## Current local follow-up — round 10, not pushed

The real round-9 width regression is fixed: the motor-area VM bridge is again
**0.80 mm outer-layer copper**, between the exact former crossbar endpoints.
Its actual emitted path has 9.214 mm of planar copper and one full-stack via
transition from bottom to top. The obsolete 0.50 mm VM sections are removed;
the existing fine-pitch pad breakouts remain. The B-phase regulation-shunt
return is rerouted at **at least 0.30 mm**, entirely on outer layers. One VM
via moves from (3.75, -15.90) to (4.20, -16.50). All 352 real vias remain
0.30 mm drill / 0.45 mm pad, through all four layers. No component, connector,
mount, outline, land size, netlist, schematic, CAD or firmware change is made.

The Ethernet warning was not a physical main-path regression: the emitted
R_ETH_RAIL_BC-to-C_ETH_6 route is 0.25 mm, matching its 0.25 mm requirement.
The flagged PCB trace actually belongs to C_ETH_7's separate branch, which is
0.15 mm and meets its own 0.15 mm requirement. The native warning is retained,
not suppressed. The two added Q_USB_ATTACH metadata/refdes warnings compared
with published latest are not lost electrical functionality. All 153 native
warnings remain reported; they are not collectively declared harmless.

Build, all-layer Gerber shorts, emitted-only continuity, independent copper
and drill checks, all four Kelvin checks, mechanics, printed legend, CLI
schematic placement and typecheck pass. All 32 module tests, six BOM tests
and firmware/host tests pass. The comparison downloads exposed another real
tooling issue: TypeScript was compiling source snapshots in reports/. Reports
are now excluded as diagnostics; compiler strictness, source includes and all
actual board/module inputs are retained and verified in the compiler file list.

**Not fabrication-approved:** fresh orderable-stock shortages for unchanged
W5500 C32843 and BSS84-7-F C85202 still block full verification and assembly
export. The 16 intentional thermal-pad/drill records, assembly-process,
stackup/return-path, actual rear-motor interface and hardware qualification
remain. No stock or process gate is waived. Current hash-bound evidence is
`reports/round10-fix-status.json` and `reports/round10-width-proof.json`.
The previous round-9 reports and comparison are historical. Nothing is pushed.

## Historical local follow-up — round 9

All six remaining **ordinary SMT solder-land/via drill conflicts are cleared**:
C_BUCK_OUT1, R_ETH_RAIL_AB, Q_PD_ENABLE, U_MOTOR pins 6 and 9, and
C_ETH_RXP_AC. Seven real placements change, including moving C_ETH_7 to the
top; the associated explicit copper is reconnected and independently checked.
The schematic, electrical net partitions, BOM values/parts, footprint/land
sizes, firmware, outline and all mounting/connector positions are unchanged.
No thermal stitch is deleted. All 352 manufactured vias remain **0.30 mm
drill / 0.45 mm pad, through all four layers**. The board remains 42.3 mm square,
four-layer and 1.6 mm thick, with four holes on the original 31 mm pattern.

The old 0.80 mm motor-area VM crossbar is replaced by an outer-layer routed
section using 0.50 mm copper, alongside the retained 0.80 mm trunks and local
0.30 mm pad breakouts. The six motor/shunt current routes remain at least
0.30 mm on outer layers. This width change is intentional and disclosed, not
a claim that every original copper segment was retained. The roughly 7.96 mm
total of 0.50 mm VM sections has an estimated 7.84 mΩ DC resistance at 20°C
with assumed 35 µm copper (about 6.27 mV / 5.02 mW at 0.8 A). This estimate
does not qualify RMS current, temperature rise, transients or the whole supply.

Native build/errors, all-layer Gerber shorts, emitted-only connectivity,
independent explicit-metal copper/drill checks, mechanical checks, four Kelvin
checks, CLI schematic placement and typecheck pass. All 32 original module
tests, six BOM validation tests, and firmware/host tests pass. The numeric motor
pin labels move 0.20 mm away from their former line, keeping the same 1.7 mm
font and nominal 0.153 mm stroke; actual packaged numeric ink bounds are checked
against the same pad/courtyard clearances. Top/bottom PCB images were inspected.
No fresh cloud AI schematic analysis or 3D inspection is claimed this round.

**Not fabrication-approved:** the fresh JLCPCB audit finds no orderable assembly
stock for W5500 C32843 and BSS84-7-F C85202, despite displayed stock. No part is
silently substituted. Full `npm run verify` therefore fails closed on stock,
and assembly export remains blocked. There are **153 native warnings versus
152**: the additional Ethernet supply path warning requests 0.25 mm and observes
0.15 mm. These warnings are disclosed, not declared harmless. The 16 intentional
thermal-pad/drill records still require double-sided stencil/via/opposite-face
process qualification. USB/Ethernet stackup/return paths, the actual rear motor
interface and hardware calibration/load/thermal/transient tests also remain.

Current evidence: `reports/round9-fix-status.json` and
`reports/round9-regression.json`. The older `verification.json` is historical,
not a passing verification for this circuit. Nothing from round 9 is pushed.

## Historical local follow-up — round 8

The original 32 module tests now all pass, with their test files unchanged.
Carrier-specific placement/route mutations are confined to parent-routing
mode; reusable stored profiles retain their original geometry. The two-sheet
preview keeps physical PCB ownership outside schematic sheets. Unused old
carrier fanout rewrites are removed. The stored-module test fixtures retain
their original 0.20 mm drills; **this motor board uses parent mode and every
manufactured via is still 0.30 mm drill / 0.45 mm pad, through all four layers**.

Seven ordinary solder-land/drill intersections are cleared, reducing 13 to 6:
C_B_AVCC, C_B_VDD_CORE, C_ETH_XI, C_ETH_TCT, C_U_3V3_IN, U_STATUS_BUFFER and
C_STATUS_BUFFER. Four capacitors move and their connections are rerouted. Three existing
stitches move; the SoC stitch stays inside its assigned thermal land, and no
thermal stitch is deleted. The attempted coordinated motor-region reroute is
not adopted because both shunt escapes compete for one available stitch site.
The existing current-carrying routes remain at least 0.30 mm on outer layers.
The broader rail-jumper relocation was rejected when it could not reach its
core-rail terminal at the specified width; no partial route is installed. The
receive-path capacitor is not moved without a differential-routing review.

The board is explicitly 1.6 mm thick rather than using the implicit 1.4 mm
default. Component CAD heights follow its actual surfaces; the outline remains
42.3 mm square, the four hole locations are unchanged, and the motor gap stays
6 mm. Cleared inner-layer GND fills are added with solid via connections;
existing signal traces stay in place. These fills are not a claim of continuous
reference planes or qualified controlled impedance.

The two current-amplifier supply bypasses use orderable C7393837,
TCC0201X7R104K100ZT (100 nF, ±10%, X7R, 0201, **10 V**) instead of the depleted
C18164586 16 V part. Their regulated 3.3 V connection and land pattern do not
change. All other populated part selections and all electrical connections are
retained. Inventory is public assembly-stock data, not a reservation.

**Not fabrication-approved:** six ordinary solder-land/via intersections,
thermal/double-sided solder-process qualification, controlled-stackup/return
path review, the actual motor's rear fastening interface, and bench/thermal/
current-calibration checks remain. Export stays blocked. No premium via filling,
board enlargement, smaller vias, clearance waiver, or new fastener assumption
is used. See `reports/round8-fix-status.json` and `reports/round8-regression.json`.

## Historical local follow-up — round 7

## Local follow-up after v0.4.49 — not pushed

The current local candidate adds hardware DATA-VBUS attach isolation with a
TS3USB31E and an NPN control stage. With host VBUS absent, a 10 kΩ pull-up
disconnects both data channels; with VBUS present the transistor enables them.
This operates independently of Linux and ROM FEL. All DATA VBUS contacts,
the USBLC6 bias pin and its bypass share the host-only 5 V net; that net does
not supply a system rail. The switch and its 100 nF bypass use regulated
3.3 V, not raw PD voltage. Powered/unpowered host attachment, enumeration and
USB signal integrity still require bench qualification.

The stocked C7519 USBLC6-2SC6 now has its manufacturer's SOT-23-6 land pattern,
replacing the incorrect smaller SOT-666 pattern. The larger protector and new
USB parts fit on the bottom without increasing the outline. Six old parts
are repositioned locally, and the bottom N17 label is moved off the output
capacitor. All original non-USB net partitions, firmware, motor-current
sensing, four mounting holes and the 42.3 mm/four-layer envelope are retained.
The new circuit has 199 populated parts / 83 catalog codes. See
`reports/round7-regression.json` for the exact approved USB terminal changes.

This is still **not fabrication approval**: thirteen ordinary solder-land/drill
intersections and the thermal/double-sided solder process remain unresolved,
as do actual rear motor fasteners, the inherited module-test failures and
hardware qualification. No filled/capped via process is silently assumed.
Assembly export remains blocked. This candidate has not been pushed.

### Earlier local routing-only follow-up

Two more ordinary solder-land/drill intersections are removed (15 -> 13):
R_INLINE_A and U_ETH pin 30. The Ethernet XI fanout uses a shorter, explicitly
specified inner-layer trunk, so the relocated via fits the original 15 mm /
two-via clock constraints. Only three replay paths change; all parts/nets,
placements, outline, mounts, thermal arrays, schematic sheets, production
legend, firmware and CAD records remain unchanged. Full-stack vias remain
0.30 mm drill / 0.45 mm pad. See `reports/round6-fix-status.json` and
`reports/round6-regression.json`. The checks pass with 0 native errors and
150 warnings; 26 inherited module failures remain unchanged, not waived.
Assembly export is still blocked by the solder-process gate. This is not
fabrication approval. The following section describes the frozen v0.4.49 upload.

## Development changes since v0.4.48

The v0.4.49 development revision removes four more ordinary solder-pad vias
(C_BUZZER, R_ISEN_B, C_PD_VDD and R_BUCK_BOTTOM), with the oscillator-via
candidate rejected rather than relaxing its 15 mm limit. It widens 51 existing
5 V segments against actual copper/drill obstacles without moving centre lines;
some short 0.12 mm necks remain, so this is not a new board-current rating.
The production legend replaces tiny overlapping reference names with readable
functional markings, while the source/BOM/CPL retain the reference designators.
The four screw rings, footprint polarity marks and motor pin-1 circle remain.
See `reports/round5-fix-status.json` for final check results and remaining gates.

**Still not fabrication-ready:** 15 ordinary pad/drill intersections and the
16 thermal-pad intersection records need solder-process review; the USB data
port's self-powered attach/VBUS detection is not implemented; Ethernet,
analog/load/thermal qualification, inherited module tests and actual motor
hardware/harness qualification remain. Assembly export now fails closed on a
fresh, hash-bound solder-process audit, even after the legend cleanup passes.
Validation reports record the pre-publication local checks; they are not
fabrication approval. The older validation paragraph below describes v0.4.48.

This development revision retains the dual-winding current telemetry and the
earlier catalog-value/package corrections, including the 22 uF/50 V motor bulk
capacitor. The seven drill-clearance violations remaining in v0.4.47 are now
cleared with zero added violations. SoC capacitor-label collisions are fixed,
and ordinary vias have been moved out of the U_FLASH.5 and R_ISEN_A.2 solder
lands. Catalog electrical checks pass for all 193 populated parts / 81 codes.
Normal build, CLI schematic placement, all-layer Gerber shorts, emitted-only
continuity, independent copper preflight and all four Kelvin checks pass.
There are 0 native errors and 150 native warnings, not zero warnings. The
42.3 mm outline, four mounting holes, four layers, connector locations,
230 parts / 213 nets, firmware and 335 full-stack 0.30/0.45 mm vias remain.

**This is not fabrication-ready.** Other ordinary via-in-pad cases and the
thermal/double-sided solder process, silkscreen, Ethernet/power/analog layout,
26 inherited module-test failures and physical qualification remain unresolved.
See `CURRENT_SENSE_PROGRESS.md` and `reports/round3-fix-status.json`. A fresh,
hash-bound independent copper pass is mandatory in the verifier; failed and
stale-audit cases are tested to fail closed. Historical fabrication exports
and older reports are not manufacturing approval. Previous releases and the
restore-verified local checkpoints are retained.

Do not treat exported files as blanket approval to order: the actual motor's
rear fastening interface/bolt length still needs physical confirmation. U_1V2
has been changed to pin-compatible TLV75512PDBVR to resolve the old assembly-stock
shortage. Its rating is 500 mA rather than 600 mA; measure core-rail load at bring-up.
The new motion firmware is compilable and host-tested, but not hardware-qualified.

A 42.3 × 42.3 mm motor-facing body, four-layer, double-sided tscircuit board for the
**StepperOnline 17HS13-0404S1**: a 42 × 42 × 34 mm, four-wire bipolar NEMA 17
stepper rated 0.40 A/phase. Four 3.5 mm NPTH mounting holes follow the standard
31 × 31 mm NEMA 17 flange pattern. This establishes the PCB-side interface;
it does not establish that the rear endbell has the same threaded interface.
Use ordinary ISO 4762 M3 socket-head fasteners without washers (5.5 mm nominal
head diameter), the standard style used on NEMA 17 motors. Each top-side hole
has a checked 5.5 mm head envelope, shown by a top-silkscreen circle and
represented by a matching top-side advisory mechanical keepout. Copper pours and exposed
pads stay out; dense-board signal copper below a head remains solder-mask
covered, and every affected through-via is tented. Because the board is assembled
on both sides, fit a nonconductive spacer no larger than 5.0 mm OD between the
motor and PCB. The manufacturer's drawing specifies four M3 threads, at least
4.5 mm deep, on the motor's shaft-side mounting flange. It does not separately
specify the rear endbell fasteners. A rear-mounted PCB therefore needs either a
verified bracket/standoff interface or measured replacement M3 through-bolts;
choose their length only after measuring the actual motor and spacer stack. The
PCB accepts ordinary M3 socket-head hardware without washers, but this
does not guarantee that the motor's original rear screws are long enough. The
exact 31 mm hole square is axis-aligned with the carrier, so the installed PCB
is not skewed relative to the motor. The 42.3 mm PCB projects 0.15 mm beyond
each side of the 42 mm motor body. At the lower-left hole, the conservative
HR911105A body outline clears the 5.5 mm ISO 4762 head by approximately 0.70 mm.
Drilled/plated features are checked separately. Do not add washers; the land is sized for the screw head
alone.
The fabrication outline is the same strict 42.3 × 42.3 mm square—there are no
edge tabs or enlarged outline regions. Every connector hole and copper annulus
has at least 0.35 mm routed-edge clearance.

The board combines the tested F1C100S Linux carrier with:

- a DRV8825 with 0.397 A/phase default and a fail-safe 0.207 A
  DNP option-resistor preset, plus fixed 1/16 microstepping;
- an STM32G030 real-time motion/safety controller;
- a dedicated USB-C power receptacle with a HUSB238A PD sink requesting 15 V / 3 A
  by default or 12 V / 3 A through a DNP option resistor;
- a TPS54302 5 V buck and the carrier's 3.3 V, 2.8 V, 2.5 V and 1.2 V rails;
- a W5500 and HR911105A jack for 10/100 Ethernet; and
- a second, dedicated USB-C receptacle for USB 2.0 FEL/gadget data.

The local revision also adds signed current telemetry on both windings using
separate 0.300 Ω inline shunts, INA241B1 gain-10 amplifiers and 1 kΩ/100 nF
ADC filters. The original DRV8825 regulation shunts and 0.397 A/phase preset
are unchanged. PA5/ADC5 and PB0/ADC8 are sampled by the motion MCU; Linux can
read them with `python3 firmware/motor-control.py --current`. That command
does not arm, move, disable, or refresh the watchdog. The values are nominal
filtered samples, not calibrated RMS current or a replacement protection loop.
Hardware PWM/noise characterization and calibration remain required.

There are no SPI or I²C expansion headers. SPI1 is dedicated to Ethernet, and
the STM32 owns the local temperature sensor. Compact SWD pads are provided for
factory and recovery use.

## Motor and connector

`J_MOTOR` is JST-PH, 2.00 mm pitch:

| Pin | Phase | 17HS13-0404S1 lead |
|---:|---|---|
| 1 | B+ | Red |
| 2 | B− | Blue |
| 3 | A− | Green |
| 4 | A+ | Black |

The published 3D assembly uses the documented `assembly.motor` and
`assembly.cable` flow. The 34 mm-body/20 mm-shaft motor is mounted 6 mm behind
the PCB with its rear M3 screws installed. The board uses its `bottomedge` as
the mount-rotation anchor and aligns that edge to `MOTOR.wireside`. This keeps
the square PCB parallel to the square motor body while placing the motor outlet
and `J_MOTOR` on the same edge. The four-conductor JST-PH cable curves across
the connector's small along-edge offset.

The manufacturer's current 17HS13-0404S1 listing describes a 1 m cable with a
2.54 mm connector. That is **not** the board's 2.00 mm JST-PH connector and is
not guaranteed to plug in. The modeled `jstph4` endpoint represents a terminated
adapter harness, not a socket built into the motor. The PCB/table are the
electrical pinout authority. See [`motor-harness.md`](motor-harness.md) for an
off-the-shelf PH pigtail option that avoids hand-crimping but requires four
insulated solder splices. A true plug-to-plug adapter needs the exact motor-side
housing and contact order identified first; no generic adapter is promised.

Confirm the two coil pairs with an ohmmeter before connection; wire colours can
change between motor revisions. The 15 V input is appropriate because the
DRV8825 regulates winding current. It must not be applied directly to a motor
winding.

The selected 17HS13-0404S1 winding is specified as 30 Ω and 37 mH ±20% per
phase at 1 kHz. Its nominal electrical time constant is 1.23 ms (approximately
0.99–1.48 ms over the inductance tolerance). At 15 V, an ideal 30 Ω/37 mH
winding reaches 0.40 A in about 1.98 ms; at 12 V it only approaches 0.40 A
asymptotically. The 15 V default therefore preserves more current-regulation
headroom as step rate rises. These values are specific to this motor and must
be rechecked before substituting another NEMA 17.

The motor rail includes a 2 A resettable fuse, reverse-blocking diode, 22 V
bidirectional TVS and local bulk/ceramic capacitance. Eleven 0.30 mm drill /
0.45 mm pad thermal vias serve the DRV8825 PowerPAD. The phase traces request
0.30 mm copper and the protected input path requests 0.80 mm copper. Motor
phase paths remain on the top/bottom surfaces; lower-current sense, logic, and
configuration signals may use the inner signal layers.

### Hardware options

Change option resistors only with all power removed. Both footprints are DNP
in the default assembly; fit the specified 0402 resistor to select the alternate
setting. These are service-time assembly options, not jumpers or headers.

| Option resistor | DNP | Fitted value/state |
|---|---:|---:|
| `R_PD_12V` | 15 V PD request | 13.3 kΩ / 12 V request |
| `R_ISET_210` | 0.396 A/phase | 1.8 kΩ / 0.207 A/phase |

With `R_ISET_210` unpopulated, the limit is approximately 0.396 A/phase. The
parallel selector can only lower that limit, never overdrive the motor. The
options are hardware service settings, not dynamic Linux controls. Confirm the
selected PD voltage and DRV8825 VREF before fitting the motor.

## Control and safety architecture

Linux never generates step pulses. It sends framed commands over UART0 to the
STM32G030; the STM32 timer generates STEP, controls DIR and enable, polls the
TMP102, and monitors DRV8825 nFAULT. The experimental STM32 firmware implements:

- enable the independent watchdog;
- keep the bridge disabled after reset;
- require a valid arm command before motion;
- require a heartbeat at least every 100 ms;
- disable the bridge if no valid command arrives for 250 ms; and
- latch off on driver fault or over-temperature.

The HUSB238A contract-valid output also gates the motor-enable path in hardware,
so loss of the requested PD contract forces the bridge asleep independently of
Linux and MCU software. F1C100S PE2/PE3 control STM32 BOOT0/reset for ROM-UART
updates. SWD and reset remain available on compact factory test pads.

PA1 also measures raw PD voltage through a filtered 1 MΩ / 100 kΩ divider;
PB3 reads a BSS138 level-shifted gate-valid signal. Arming requires both a valid
gate state and measured 10.8–16.5 V VBUS. The original hardware gate remains.
The DRV8825 still regulates both windings through its two current shunts;
there is no separate calibrated MCU coil-current measurement.

The host/MCU wire protocol is documented in
[`firmware/PROTOCOL.md`](firmware/PROTOCOL.md). The Linux reference client is
[`firmware/motor-control.py`](firmware/motor-control.py). A matching STM32
firmware image is required before the hardware can move a motor. Source, build
and factory boot-option requirements are in [`firmware/stm32/README.md`](firmware/stm32/README.md).

## USB-C power, USB-C data and Ethernet

Use a USB-C PD source that offers the selected 12 V or 15 V PDO with adequate
current. The HUSB238A uses 11 kΩ VSET for the default 15 V request; fitting
`R_PD_12V` places 13.3 kΩ in parallel, producing the nominal 6.02 kΩ 12 V
selection. Its 21 kΩ ISET requests 3 A.
Its raw VBUS input cold-starts the controller and is isolated from the system
rail by an HUSB238A-controlled AO4407A high-side switch. The USB receptacle and
power path are 20 V / 5 A-rated, but this board's design point is 15 V. A
5 V-only source is not a valid motor supply. Even if the logic powers up, the
MCU's measured-voltage check must reject arming at 5 V. Verify the sink's
fallback/cold-start behaviour on the actual source during bring-up.

`J_USB_PWR` is power-only and `J_USB_DATA` is the F1C100S USB2 device/FEL
connection. The DATA port has independent 5.1 kΩ CC pull-downs, while its VBUS
pads are intentionally unconnected. Keep the PD port attached while using FEL
or Linux USB gadget mode. This self-powered arrangement prevents a computer's
5 V rail and the PD-derived system rail from backfeeding each other.

This isolation does **not** implement host-VBUS attachment detection. The
present board must not be represented as a USB-compliance-qualified
self-powered peripheral. A hardware USB2 data-path gate controlled by that
receptacle's VBUS is being evaluated so that Linux gadget mode **and ROM FEL
recovery** obey attachment sequencing without joining the two supply rails;
it is not installed here.

### PCB markings

`D` identifies USB data, `PD` power, `R` reset, `FEL` the cuttable boot jumper
and `N17` the board family. Some markings are on the reverse face because this
is a dense double-sided assembly. Motor connector numbers 1–4 are printed on
the reverse face in physical pad order; use the motor/connector table above
to identify phases. Tiny reference names are omitted from production ink,
not from the source, BOM or CPL.

`JP_BOOT` is a normally closed, cuttable copper solder jumper rather than an
assembled header. Leave its bridge intact for normal SPI-flash/Linux boot. Cut
the narrow bridge to isolate flash CS and force USB FEL recovery, then restore
normal boot with a small solder bridge. It is intentionally DNP and absent from
the BOM/CPL; no component needs to be installed there.

The W5500 is a dedicated SPI1 peripheral with PE7 CS, PE8 MOSI, PE9 SCLK,
PE10 MISO, PE5 reset and PE6 interrupt. The Linux device-tree fragment in
[`firmware/carrier.dtsi`](firmware/carrier.dtsi) binds it as the system Ethernet
interface. UART0 is reserved for the motion MCU and must not be the Linux console.

## Build and verification

```sh
npm ci
npm run typecheck
npm run build
npm run check:continuity
npm run render:schematics
npm run stock:audit
npm run verify
npm run check
npm run check:shorts
npx tsci check source dist/index/circuit.json
npx tsci check pin_specification dist/index/circuit.json
npm run export:fabrication
```

The emitted-copper continuity audit needs Python with Shapely. Install the
pinned `requirements-routing.txt` into a virtual environment and set
`ROUTING_PYTHON` to that environment's Python. The audit checks actual built
copper without injecting saved routes; disconnected terminal islands fail even
if the native checker reports no individual missing traces. Fabrication export
requires a passing, hash-matched continuity report.

`scripts/verify.mjs` asserts the board outline/layers, zero emitted DRC errors,
exact 0.30/0.45 mm geometry for every routed via, component bounds, double-sided
assembly, raw/switched USB-PD topology, W5500 MDI termination, motor and safety
connectivity, motor/power copper widths, JLCPCB IDs, and a stock-report hash
tied to the exact circuit JSON. Inventory is a point-in-time
snapshot, not a reservation; rerun the audit before ordering and review JLCPCB's
placement/polarity preview.

The schematic is split into functional sheets for SoC support, Linux interfaces,
unused SoC interfaces, USB-C PD/5 V power, SoC rails, Ethernet, real-time motion,
the driver, diagnostics and PD telemetry. `npm run render:schematics` writes a
PNG and SVG for every sheet under `reports/schematic-sheets/` for visual review.

Generated circuit and previews are under `dist/index/`. The final Gerbers, BOM
and pick-and-place files are under `fabrication/` after export.

## First-article bring-up

This reroute candidate is not yet fabrication-output checked or physically validated.
The required staged measurements—including both PD selections, every VREF
preset, back-EMF/transient capture, driver heating, and shoot-through/current
spike checks—are in [`hardware-validation.md`](hardware-validation.md). Passing
software DRC and shorts checks does not replace those first-article tests.

The design derives from the tested
[F1C100S Linux development board](https://tscircuit.com/seveibar/f1c100s-linux-dev-board)
and takes USB-PD architecture inspiration from Rishabh's
[RP2040 reference design](https://tscircuit.com/imrishabh18/rp2040-motor-controller#files).
The rear-mounted NEMA 17 mechanical concept is benchmarked against the
[41.8 × 41.8 mm uStepper S](https://ustepper.com/productsheets/Product_sheet_S_dual_mount.pdf).
Electrical values are based on the
[StepperOnline 17HS13-0404S1 specification](https://www.omc-stepperonline.com/nema-17-bipolar-1-8deg-26ncm-36-8oz-in-0-4a-12v-42x42x34mm-4-wires-17hs13-0404s1),
the [TI DRV8825 datasheet](https://www.ti.com/lit/ds/symlink/drv8825.pdf), and
the [Hynetek HUSB238A datasheet](https://www.hynetek.com/uploadfiles/site/219/news/ebc04ecb-03e3-4e21-bf36-24dd12fb4448.pdf).
Review annotations follow tscircuit handbook commit
`0c951d65be1b0bbddf989f8179e8591b0441ec8f`.