shibosoftwaredev/f1c100s-linux-nema17-stepper-controller

README.md

# F1C100S Linux NEMA 17 stepper controller

A 42.3 × 42.3 mm motor-facing body, four-layer, double-sided tscircuit board for the
**StepperOnline 17HS13-0404S1**: a 42 × 42 × 34 mm, four-wire bipolar NEMA 17
stepper rated 0.40 A/phase. Two diagonal 3.3 mm mounting holes use the standard
31 mm NEMA 17 mounting pattern so the PCB can mount on the rear of the motor.
The fabrication outline is the same strict 42.3 × 42.3 mm square—there are no
edge tabs or enlarged outline regions. Every connector hole and copper annulus
has at least 0.35 mm routed-edge clearance.

The board combines the tested F1C100S Linux carrier with:

- a DRV8825 set to approximately 0.397 A peak/phase and fixed 1/16 microstepping;
- an STM32G030 real-time motion/safety controller;
- a dedicated USB-C power receptacle with a HUSB238A PD sink requesting 15 V / 3 A;
- a TPS54302 5 V buck and the carrier's 3.3 V, 2.8 V, 2.5 V and 1.2 V rails;
- a W5500 and HR911105A jack for 10/100 Ethernet; and
- a second, dedicated USB-C receptacle for USB 2.0 FEL/gadget data.

There are no SPI or I²C expansion headers. SPI1 is dedicated to Ethernet, and
the STM32 owns the local temperature sensor. Compact SWD pads are provided for
factory and recovery use.

## Motor and connector

`J_MOTOR` is JST-PH, 2.00 mm pitch:

| Pin | Phase | 17HS13-0404S1 lead |
|---:|---|---|
| 1 | B+ | Red |
| 2 | B− | Blue |
| 3 | A− | Green |
| 4 | A+ | Black |

Confirm the two coil pairs with an ohmmeter before connection; wire colours can
change between motor revisions. The 15 V input is appropriate because the
DRV8825 regulates winding current. It must not be applied directly to a motor
winding.

The motor rail includes a 2 A resettable fuse, reverse-blocking diode, 22 V
bidirectional TVS and local bulk/ceramic capacitance. Eleven 0.30 mm drill /
0.45 mm pad thermal vias serve the DRV8825 PowerPAD. The phase traces request
0.30 mm copper and the protected input path requests 0.80 mm copper.

## Control and safety architecture

Linux never generates step pulses. It sends framed commands over UART0 to the
STM32G030; the STM32 timer generates STEP, controls DIR and enable, polls the
TMP102, and monitors DRV8825 nFAULT. The intended STM32 firmware must:

- enable the independent watchdog;
- keep the bridge disabled after reset;
- require a valid arm command before motion;
- require a heartbeat at least every 100 ms;
- disable the bridge if no valid command arrives for 250 ms; and
- latch off on driver fault or over-temperature.

The HUSB238A contract-valid output also gates the motor-enable path in hardware,
so loss of the requested PD contract forces the bridge asleep independently of
Linux and MCU software. F1C100S PE2/PE3 control STM32 BOOT0/reset for ROM-UART
updates. SWD remains available on bottom-edge test pads.

The proposed host/MCU wire protocol is documented in
[`firmware/PROTOCOL.md`](firmware/PROTOCOL.md). The Linux reference client is
[`firmware/motor-control.py`](firmware/motor-control.py). A matching STM32
firmware image is required before the hardware can move a motor.

## USB-C power, USB-C data and Ethernet

Use a USB-C PD source that offers a 15 V PDO with adequate current. The
HUSB238A is strapped for a 15 V / 3 A request with 11 kΩ VSET and 21 kΩ ISET.
Its raw VBUS input cold-starts the controller and is isolated from the system
rail by an HUSB238A-controlled AO4407A high-side switch. The USB receptacle and
power path are 20 V / 5 A-rated, but this board's design point is 15 V. A
non-PD 5 V source can power the logic buck, but the hardware interlock must keep
motor drive disabled without the valid requested contract.

`J_USB_PWR` is power-only and `J_USB_DATA` is the F1C100S USB2 device/FEL
connection. The DATA port has independent 5.1 kΩ CC pull-downs, while its VBUS
pads are intentionally unconnected. Keep the PD port attached while using FEL
or Linux USB gadget mode. This self-powered arrangement prevents a computer's
5 V rail and the PD-derived system rail from backfeeding each other.

`JP_BOOT` is a normally closed, cuttable copper solder jumper rather than an
assembled header. Leave its bridge intact for normal SPI-flash/Linux boot. Cut
the narrow bridge to isolate flash CS and force USB FEL recovery, then restore
normal boot with a small solder bridge. It is intentionally DNP and absent from
the BOM/CPL; no component needs to be installed there.

The W5500 is a dedicated SPI1 peripheral with PE7 CS, PE8 MOSI, PE9 SCLK,
PE10 MISO, PE5 reset and PE6 interrupt. The Linux device-tree fragment in
[`firmware/carrier.dtsi`](firmware/carrier.dtsi) binds it as the system Ethernet
interface. UART0 is reserved for the motion MCU and must not be the Linux console.

## Build and verification

```sh
npm ci
npm run typecheck
npm run build
npm run render:schematics
npm run stock:audit
npm run verify
npm run check
npm run check:shorts
npx tsci check source index.circuit.tsx
npx tsci check pin_specification index.circuit.tsx
npm run export:fabrication
```

`scripts/verify.mjs` asserts the board outline/layers, zero emitted DRC errors,
exact 0.30/0.45 mm geometry for every routed via, component bounds, double-sided
assembly, raw/switched USB-PD topology, W5500 MDI termination, motor and safety
connectivity, motor/power copper widths, JLCPCB IDs, and a stock-report hash
tied to the exact circuit JSON. Inventory is a point-in-time
snapshot, not a reservation; rerun the audit before ordering and review JLCPCB's
placement/polarity preview.

The schematic is split into eight functional sheets: SoC support, Linux
interfaces, unused SoC interfaces, USB-C PD/5 V power, SoC power rails,
Ethernet, real-time stepper control, and the NEMA 17 driver stage. `npm run render:schematics` writes a
PNG and SVG for every sheet under `reports/schematic-sheets/` for visual review.

Generated circuit and previews are under `dist/index/`. The final Gerbers, BOM
and pick-and-place files are under `fabrication/` after export.

## First-article bring-up

This revision is fabrication-output checked, not yet physically validated.
Program the STM32 and Linux flash before attaching a motor. On a current-limited
PD bench setup, first verify 5 V, 3.3 V, 2.8 V, 2.5 V and 1.2 V; then verify the
15 V contract, motor-enable interlock, VREF, nFAULT, watchdog timeout and
temperature shutdown without a motor. Finally test an uncoupled motor at low
speed and monitor the driver, sense resistors, regulators and motor temperature.

The design derives from the tested
[F1C100S Linux development board](https://tscircuit.com/seveibar/f1c100s-linux-dev-board)
and takes USB-PD architecture inspiration from Rishabh's
[RP2040 reference design](https://tscircuit.com/imrishabh18/rp2040-motor-controller#files).
The rear-mounted NEMA 17 mechanical concept is benchmarked against the
[41.8 × 41.8 mm uStepper S](https://ustepper.com/productsheets/Product_sheet_S_dual_mount.pdf).
Review annotations follow tscircuit handbook commit
`0c951d65be1b0bbddf989f8179e8591b0441ec8f`.