seveibar/rp2040-zero

This code defines a hardware schematic with discrete components and modules including voltage regulators, microcontroller (RP2040), flash memory, LEDs, crystal oscillator, and buttons, interconnected through specific pins and footprints for PCB layout.

Usage: To use the RP2040 component from the "@tsci/seveibar.rp2040-zero" package: 1. Import the component: ```tsx import { RP2040 } from "@tsci/seveibar.rp2040-zero/imports/RP2040" ``` 2. Use in a circuit: ```tsx <RP2040 name="U3" connections={{ // Connect pins to nets or other components GPIO0: "net.GPIO0", IOVDD1: "net.V3_3", GND: "net.GND" }} /> ``` Key details: - Supports 57 pins - Pins include GPIO, power, USB, crystal, and debug interfaces - Can be configured with various connections and pin mappings

Version: 0.0.18-pr6-2229c6f4
License: unset
Stars: 1

lib/VoltageRegulator.tsx

import { RT9013_33GB } from "../imports/RT9013_33GB"
import type { GroupProps } from "@tscircuit/props"

export const VoltageRegulator = (groupProps: GroupProps) => (
  <group {...groupProps} pcbX={-5} pcbY={-5}>
    <capacitor
      name="C6"
      schOrientation="vertical"
      footprint="0402"
      capacitance="2.2uF"
    />
    <capacitor
      name="C1"
      schOrientation="vertical"
      footprint="0402"
      capacitance="2.2uF"
    />
    <capacitor
      name="C2"
      schOrientation="vertical"
      footprint="0402"
      capacitance="2.2uF"
    />
    <capacitor
      name="C5"
      schOrientation="vertical"
      footprint="0402"
      capacitance="1uF"
    />
    <RT9013_33GB
      name="U1"
      connections={{
        VIN: ["C6.1", "C1.1", "C2.1", "net.VSYS"],
        GND: ["C6.2", "C1.2", "C2.2", "net.GND"],
        EN: "U1.1",
        VOUT: ["net.V3_3", "C5.1"],
      }}
    />
    <trace from="C5.2" to="net.GND" />
  </group>
)