seveibar/pd-dual-stepper-controller
Bottom-side PCB silkscreen artwork consisting of embedded mirrored TS Circuit SVG logos, with via-clearance-aware lower-board placement.
- Version
- 0.1.0
- License
- unset
- Stars
- 0
scripts/simplify-route-plan.py
"""Remove duplicate and collinear vertices without changing routed copper."""
import json,sys,math
from pathlib import Path
path=Path(sys.argv[1]);plan=json.loads(path.read_text());before=sum(len(t['route']) for t in plan['traces'])
for t in plan['traces']:
out=[]
for p in t['route']:
if out and p['route_type']==out[-1]['route_type']=='wire' and p['layer']==out[-1]['layer'] and p['width']==out[-1]['width'] and p['x']==out[-1]['x'] and p['y']==out[-1]['y']:
for k in ('start_pcb_port_id','end_pcb_port_id'):
if k in p:out[-1][k]=p[k]
continue
out.append(p)
while len(out)>=3:
a,b,c=out[-3:]
if not (a['route_type']==b['route_type']==c['route_type']=='wire' and a['layer']==b['layer']==c['layer'] and a['width']==b['width']==c['width']):break
dx,dy=b['x']-a['x'],b['y']-a['y'];ex,ey=c['x']-b['x'],c['y']-b['y']
if abs(dx*ey-dy*ex)>1e-12 or dx*ex+dy*ey<0 or any(k in b for k in ('start_pcb_port_id','end_pcb_port_id')):break
out.pop(-2)
t['route']=out
path.write_text(json.dumps(plan,indent=2)+'\n');print('Route vertices',before,'->',sum(len(t['route']) for t in plan['traces']))