seveibar/pd-dual-stepper-controller

Bottom-side PCB silkscreen artwork consisting of embedded mirrored TS Circuit SVG logos, with via-clearance-aware lower-board placement.

Version: 0.1.0
License: unset
Stars: 0

engineering/power-pad-clearance-review.json

{
  "revision": "1.0.37",
  "hardMinimumMm": 0.1,
  "preferredMinimumMm": 0.15,
  "rationale": "All 37 previous power-to-pad exceptions have been removed by local routing changes. Every power route must meet 0.15 mm to foreign pads. No spacing exceptions or DRC suppression are permitted.",
  "exceptions": []
}