seveibar/pd-dual-stepper-controller

Bottom-side PCB silkscreen artwork consisting of embedded mirrored TS Circuit SVG logos, with via-clearance-aware lower-board placement.

Version: 0.1.0
License: unset
Stars: 0

engineering/jlcpcb-clearance-rules.json

{
  "revision": "1.0.38",
  "source": "https://jlcpcb.com/capabilities/pcb-capabilities",
  "copper": { "outerOz": 1, "innerOz": 0.5, "layers": 4 },
  "minimumMm": {
    "traceWidth": 0.1,
    "traceToTrace": 0.1,
    "padToTrace": 0.1,
    "padToPad": 0.15,
    "viaToTrace": 0.1,
    "viaToPad": 0.125,
    "motorPowerToPad": 0.15,
    "viaDrillToTrace": 0.2,
    "innerViaDrillToCopper": 0.2,
    "pthDrillToTrace": 0.28,
    "innerPthDrillToCopper": 0.3,
    "npthToCopper": 0.2,
    "viaDrillToViaDrill": 0.2,
    "pthDrillToDrill": 0.45,
    "copperToBoardEdge": 0.2
  },
  "note": "Trace spacing is conservative for 1 oz multilayer fabrication. Motor-power-to-pad 0.15 mm and via-to-pad 0.125 mm are board targets above the general 0.10 mm copper spacing. No power-pad clearance exceptions are permitted."
}