seveibar/f1c1990s-dev-board
This code manages the entire PCB assembly process for a computer hardware module, including component placement, schematic integration, automated routing, copper pouring, and design rule checks, focused on a four-layer carrier board with integrated support components and connectors.
- Version
- 1.8.0
- License
- unset
- Stars
- 0
modules/f1c100s/src/generated/lcd_top_storage_right.metrics.json
PCB
Schematic
{
"profile": "lcd_top_storage_right",
"inputHash": "4b2a5126bacd5733878c0bfece3432bf7d506275dc6d272099b683b6676a7fc6",
"moduleSizeMm": 28,
"rules": {
"traceWidth": 0.12,
"clearance": 0.1,
"viaDiameter": 0.45,
"viaDrill": 0.2,
"layers": 4
},
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 1146,
"vias": 218,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1492.028,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057,
"drcErrors": 0,
"optimization": {
"before": {
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 3886,
"vias": 247,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1547.98,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057
},
"after": {
"platedTestPoints": 71,
"nonTopExitContacts": 69,
"traces": 176,
"wireSegments": 1146,
"vias": 218,
"capacitors": 32,
"localDecouplers": 15,
"routedLengthMm": 1492.028,
"usbDmLengthMm": 8.251748,
"usbDpLengthMm": 8.251805,
"usbSkewMm": 0.000057
}
}
}