seveibar/am3352-dev-board

scripts/render-ddr-report.py

"""Render the measured DDR report; never infer success from target values."""
import json
from pathlib import Path
r=json.load(open('design/ddr-skew-check.json'));passed=all(g['status']=='PASS' for g in r['groups']);rows=[]
for g in r['groups']:
 if 'skewMm' in g:rows.append(f"| {g['group']} | {g['skewMm']:.6f} | {g['limitMm']:.3f} | {g['status']} |")
text=f'''# DDR length matching

**PCB centerline matching: {'PASS' if passed else 'INCOMPLETE'}.** Measured from the compiled circuit, CPU ball center to RAM ball center. The route targets are 18.50 mm for byte 0, 12.10 mm for byte 1, and 35.02 mm for address/control and CK. Each byte includes its eight DQ signals, DM, and both DQS conductors.

| Group | Measured skew (mm) | Maximum (mm) | Result |
|---|---:|---:|---|
'''+ '\n'.join(rows)+'\n\n'
for g in r['groups']:
 if 'maximumLengthMm' in g:
  if 'nominalMm' in g:text+=f"- {g['group']}: {g['minimumLengthMm']:.6f}–{g['maximumLengthMm']:.6f} mm; allowed {g['allowedMinimumMm']:.6f}–{g['allowedMaximumMm']:.6f} mm. **{g['status']}**.\n"
  else:text+=f"- {g['group']}: longest {g['maximumLengthMm']:.6f} mm; maximum {g['limitMm']:.6f} mm. **{g['status']}**.\n"
text+='''
The nominal limits use the longest actual CPU-to-RAM pin-pair Manhattan distance, rather than combining unrelated X/Y maxima. The address/control nominal adds 7.62 mm and permits ±1.27 mm. This is a single x16 RAM with direct point-to-point signal routes; there are no fly-by load branches. RESETn is listed below for reference and is excluded from the synchronous matching groups.

These are **geometric PCB lengths**, not electrical-delay or impedance signoff. The calculation excludes package delay, vertical via travel, dielectric differences between layers, and coupling. CK/DQS pair routing layers and via counts are reported explicitly. Fabricator stackup and signal-integrity review remain necessary before fabrication.

Constraints: [TI AM335x datasheet, Tables 7-68 and 7-69](https://www.ti.com/lit/ds/symlink/am3352.pdf). Recheck with `npm run verify:ddr`; it fails if any measured skew or placement-derived nominal limit fails. The JSX reference constraints are not used as evidence of compliance.

| Net | Pin-to-pin length (mm) | Path vias | Routing layers (mm) |
|---|---:|---:|---|
'''
for n,v in sorted(r['nets'].items()):text+=f"| {n} | {v['pathLengthMm']:.6f} | {v['pathViaSites']} | "+', '.join(f'{l}: {v:.4f}' for l,v in v['planarLengthByLayerMm'].items())+' |\n'
text+=f"\nCompiled circuit SHA-256: `{r['circuitSha256']}`.\n"
Path('DDR-SKEW.md').write_text(text)