seveibar/am3352-dev-board

A 324-ball TI AM3352 ARM processor with DDR3, LCD, USB, Ethernet, storage, serial, analog, clock, reset, power, and JTAG interfaces, paired with configurable JST-GH board connectors and constrained PCB routing.
Version: 1.0.2
License: unset
Stars: 0
design/routing-lengths.json

{
  "note": "Planar copper length only; via barrel delays and stackup must be included in timing signoff.",
  "groups": [
    {
      "name": "DDR_BYTE0",
      "limit": 0.635,
      "names": [
        "DDR_D0",
        "DDR_D1",
        "DDR_D2",
        "DDR_D3",
        "DDR_D4",
        "DDR_D5",
        "DDR_D6",
        "DDR_D7",
        "DDR_DQM0",
        "DDR_DQS0",
        "DDR_DQSn0"
      ],
      "lengths": [
        18.500053848229086,
        18.500108479647594,
        18.470701706652335,
        18.520810261263218,
        18.499999999999996,
        18.47076883355824,
        18.500000000000004,
        18.520709884024523,
        18.50005427767864,
        18.491421824480426,
        18.500000327129538
      ],
      "vias": [
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2
      ],
      "xySkew": 0.05010855461088326
    },
    {
      "name": "DDR_BYTE1",
      "limit": 0.635,
      "names": [
        "DDR_D8",
        "DDR_D9",
        "DDR_D10",
        "DDR_D11",
        "DDR_D12",
        "DDR_D13",
        "DDR_D14",
        "DDR_D15",
        "DDR_DQM1",
        "DDR_DQS1",
        "DDR_DQSn1"
      ],
      "lengths": [
        12.10016285513358,
        12.100061687560148,
        12.120791957584423,
        12.070814123124041,
        12.100000348570518,
        12.070868382554398,
        12.070968995811674,
        12.070828164730866,
        12.070710277303228,
        12.070798966719304,
        12.100217425465084
      ],
      "vias": [
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2,
        2
      ],
      "xySkew": 0.05008168028119542
    },
    {
      "name": "DDR_CK",
      "limit": 0.127,
      "names": [
        "DDR_CK",
        "DDR_CKn"
      ],
      "lengths": [
        35.02015502639641,
        35.04071276450626
      ],
      "vias": [
        2,
        2
      ],
      "xySkew": 0.02055773810985073
    },
    {
      "name": "DQS0",
      "limit": 0.127,
      "names": [
        "DDR_DQS0",
        "DDR_DQSn0"
      ],
      "lengths": [
        18.491421824480426,
        18.500000327129538
      ],
      "vias": [
        2,
        2
      ],
      "xySkew": 0.008578502649111641
    },
    {
      "name": "DQS1",
      "limit": 0.127,
      "names": [
        "DDR_DQS1",
        "DDR_DQSn1"
      ],
      "lengths": [
        12.070798966719304,
        12.100217425465084
      ],
      "vias": [
        2,
        2
      ],
      "xySkew": 0.02941845874578064
    },
    {
      "name": "USB0",
      "limit": 0.127,
      "names": [
        "USB0_DP",
        "USB0_DM"
      ],
      "lengths": [
        32.011747105850624,
        33.080273104197715
      ],
      "vias": [
        2,
        3
      ],
      "xySkew": 1.0685259983470914
    }
  ]
}